validating high-level synthesis

Validating High-Level Synthesis

Sudipta Kundu, Sorin Lerner, Rajesh Gupta

Department of Computer Science and Engineering,

University of California, San Diego

2 University of California, San Diego Validating High-Level Synthesis

Power

Performance

Area

High-Level Synthesis

Algorithmic Design

Register Transfer Level Design (RTL)

FunctionallyEquivalentScheduled Design

FunctionallyEquivalent

FunctionallyEquivalent

Co

ntr

oll

er

S0

S1

S2S3

S4

f!f

Data path

….x = a * b;c = a < b;if (c) then a = b – x;else a = b + x;a = a + x;b = b * x;….

C/C++, SystemC< 100 – 10K lines >

Verilog, VHDL< 1K – 100K lines >

High-Level Synthesis

(HLS)

3 University of California, San Diego Validating High-Level Synthesis

EquivalenceChecker

• For each translation• Does not guarantee => HLS tool is bug free

Checker

• Once and for all• HLS tool always produce correct results

The Problem

Transformations

Input Program

(Specification)

TransformedProgram

(Implementation)

Translation Validation (TV) Optimizing Compiler [Pnueli et al. 98] [Necula 00] [Zuck et al. 05]

Does guarantee => any errors in translation will be caught when tool runs

Is the Specification “functionally equivalent” to the Implementation?

4 University of California, San Diego Validating High-Level Synthesis

Contributions

• Developed TV techniques for a new setting: HLS• Algorithm uses a bisimulation relation approach.

• Implemented TV for a realistic HLS tool: SPARK• Widely used: 4,000 downloads, over 100 active users.• Large Software: around 125, 000 LoC.

• Ran it on 12 benchmarks• Modular: works on one procedure at a time.• Practical: took on average 6 secs to run per procedure.• Easy to Implement: only a fraction of development cost of SPARK.• Useful: found 2 previously unknown bugs.

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Outline

1. Motivation and Problem definition

2. Our Approach using an Example• Definition of Equivalence• Translation Validation Algorithm

• Generate Constraints• Solve Constraints

3. Experiments and Results• SPARK: Parallelizing HLS Framework

4. Conclusion

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Original Program:

An Example of HLS

Specification:

i2: k = p

i1: sum = 0

i3: (k < 10) i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum;

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum; + + <

Resource Allocation:

i5: sum = sum + k

i4: k = k + 1

i2: k = p

i1: sum = 0

a1

a0

i3: (k < 10) i6: ¬ (k < 10)a2

a3

a4

a5

a6

i7: return sum 10

sum = ∑ k

p+1

7 University of California, San Diego Validating High-Level Synthesis

i2: k = p

i1: sum = 0

a1

a0

Loop Pipelining:

t = k + 1

i5: sum = sum + k

An Example of HLS

Specification:

i2: k = p

i1: sum = 0

i3: (k < 10) i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum;

+ + <Resource Allocation:

i4: k = k + 1

i3: (k < 10) i6: ¬ (k < 10)a2

a3

a4

a5

a6

i7: return sum

i2: k = p

i1: sum = 0

a1

a0

t = k + 1

i4: k = t

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Copy Propagation:

t = k + 1

i5: sum = sum + ki5: sum = sum + t

t = p + 1

An Example of HLS

Specification:

i2: k = p

i1: sum = 0

i3: (k < 10) i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum;

+ + <Resource Allocation:

i3: (k < 10) i6: ¬ (k < 10)a2

a3

a4

a5

a6

i7: return sum

i2: k = p

i1: sum = 0

a1

a0

t = k + 1

i4: k = t

t = t + 1

9 University of California, San Diego Validating High-Level Synthesis

a0

i1: sum = 0i2: k = pi41: t = p + 1

Scheduling:

An Example of HLS

Specification:

i2: k = p

i1: sum = 0

i3: (k < 10) i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum;

+ + <Resource Allocation:

t = p + 1

i2: k = p

i1: sum = 0

a1

a0

a2i3: (k < 10) i6: ¬ (k < 10)

a5

a6

i7: return sum

a3

i4: k = t

i5: sum = sum + ta4

t = t + 1

i4: k = ti5: sum = sum + ti42: t = t + 1

Read After Write dependency

10 University of California, San Diego Validating High-Level Synthesis

An Example of HLS

Specification:

i2: k = p

i1: sum = 0

i3: (k < 10) i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

int SumTo10 (int p) int sum = 0, k = p; while (k < 10) sum += ++k; return sum;

b0

j1: sum = 0j2: k = pj41: t = p + 1

b1j3: (k < 10) j6: ¬ (k < 10)

b3

b4

j7: return sum

b2

j4: k = tj5: sum = sum + tj42: t = t + 1

Implementation:

≡

Re-labeled

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Definition of Equivalence

• Specification ≡ Implementation => They have the same set of execution sequences of visible instructions.

• Visible instructions are:• Function call and return statements.

• Two function calls are equivalent if the state of globals and the arguments are the same.

• Two returns are equivalent if the state of the globals and the returned values are the same.

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Technique for Proving Equivalence

• Bisimulation Relation: relates a given program state in the implementation with the corresponding state in the specification and vice versa.

• It satisfies the following properties:

1. The start states are related.

2.

s2

i

s’2

i

s1 s’1

Specification Implementation

• Theorem: If there exists a bisimulation relation between the specification and the implementation, then they are equivalent.

Visible Instruction

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Our Approach

• Split program state space in two parts:• control flow state, which is finite.

=> explored by traversing the CFGs.• dataflow state, which may be infinite.

=> explored using Automated Theorem Prover (ATP).

• Bisimulation relation: set of entries of the form (p1, p2, Ф).• p1 – program point in Specification.

• p2 – program point in Implementation.

• Ф – formula that relates the data.

14 University of California, San Diego Validating High-Level Synthesis

Bisimulation Relation

ps = pi

ks = ki Λ sums = sumi

Λ (ks + 1) = ti

sums = sumi

i2: k = p

i1: sum = 0

i3: (k < 10)i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

b1

b2

b3

b4

b0

j1: sum = 0j2: k = pj41: t = p + 1

j4: k = tj5: sum = sum + tj42: t = t + 1

j7: return sum

j6: ¬ (k < 10)j3: (k < 10)

Specification Implementation

• Bisimulation relation: set of entries of the form (p1, p2, Ф).• p1 – program point in Specification.

• p2 – program point in Implementation.

• Ф – formula that relates the data.

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Translation Validation Algorithm

• Two step approach. • Generate Constraints: traverses the CFGs

simultaneously and generates the constraints required for the visible instructions to be matched.

• Solve Constraints: solves the constraints using a fixpoint algorithm.

• For loops: iterate to a fixed point.• May not terminate in general.• But in practice can find the bisimulation relation.

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Generate Constraints

i2: k = p

i1: sum = 0

i3: (k < 10)i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

b1

b2

b3

b4

b0

j1: sum = 0j2: k = pj41: t = p + 1

j4: k = tj5: sum = sum + tj42: t = t + 1

j7: return sum

j6: ¬ (k < 10)j3: (k < 10)

Constraint Variable

Constraints:

Specification Implementation

Ψ(a2, b1)

b1a2

Ψ(a0, b0)b0a0

i1i2

j1j2j41

Ψ(a2, b1)

Ψ(a2, b1)

b1

b1

a2

a2

i3i4i5

j4j5j42

j3

Ψ(a5, b3)

j6

b1

b3

a2

a5

i6

Ψ(a2, b1)

Ψ(a5, b3) ⇒ sums =

sumi

Ψ(a2, b1) ⇒ ks = ki

Ψ(a0, b0)

Ψ(a2, b1)

Ψ(a5, b3)

Branch Correlation- Strongest Post Condition- Structure of the code

17 University of California, San Diego Validating High-Level Synthesis

Ψ(a2, b1)

Ψ(a0, b0)b0

b1

a0

a2

i1i2

j1j2j41

Ψ(a2, b1)

Ψ(a2, b1)

b1

b1

a2

a2

i3i4i5

j4j5j42

j3

Ψ(a5, b3)

j6

b1

b3

a2

a5

i6

Ψ(a2, b1)

Solve Constraints

Constraints:

i2: k = p

i1: sum = 0

i3: (k < 10)i6: ¬ (k < 10)

i4: k = k + 1

i5: sum = sum + k

a2

a3

a4

a5

a1

a6

a0

i7: return sum

b1

b2

b3

b4

b0

j1: sum = 0j2: k = pj41: t = p + 1

j4: k = tj5: sum = sum + tj42: t = t + 1

j7: return sum

j6: ¬ (k < 10)j3: (k < 10)

Specification ImplementationΨ(a0, b0) : ps = pi

Ψ(a2, b1) : TrueΨ(a2, b1) : ks = ki

Ψ(a5, b3) : True

Ψ(a5, b3) : sums = sumi

X X X

Ψ(a2, b1) : ks = ki Λ

(ks + 1) = ti

Ψ(a2, b1) : ks = ki Λ (ks + 1) = ti

Λ sums = sumi

Ψ(a5, b3) ⇒ sums =

sumi

Ψ(a2, b1) ⇒ ks = ki X

X

Ψ(a0, b0)

Ψ(a2, b1)

Ψ(a5, b3)

b1

b1

a2

a2

Ψ(a2, b1) : ks = ki

Ψ(a2, b1) : ks = ki

j3: (ki < 10)j4: ki = ti

j5: sumi = sumi + ti

j42: ti = ti + 1

i3: (ks < 10)

i4: ks = ks + 1

i5: sums = sums + ks

WP( Ψ(a2, b1) ) : (ki + 1) ⇒ (ks + 1) ⇒ (ks + 1) =

ti

ATP[ Ψ(a2, b1) ⇒ WP( Ψ(a2, b1) ) ]

Ψ(a2, b1): ks = ki ∧ (ks + 1) = ti: ks = ki ∧ WP(Ψ(a2, b1) )

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SPARK: Parallelizing HLS Framework

CProgram

High Level

Synthesis

RTLBinding

Intermediate Representation (IR)

Transformations

Code Motion, CSE, IVA, Copy Propagation, Dead Code Elimination, Percolation, Trailblazing, Chaining Across

conditions, dynamic CSE.

Heuristics

HTG Scheduling Walker, Candidate Op Walker, Get Available Ops, Loop Pipelining

Scheduled IR

SPARK

Pre-Synthesis Optimization

Allocation Scheduling

No PointerNo RecursionNo goto

Validation Engine

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Results

BenchmarksNo. of simulation relation entries

No. of calls to theorem prover

Time

(sec:msec)

1. incrementer 6 9 00:5

2. integer-sum 6 20 00:8

3. array-sum 6 24 00:8

4. diffeq 7 41 01:6

5. waka 11 79 02:6

6. pipelining 12 75 02:3

7. rotor 14 71 02:5

8. parker 26 281 05:2

9. s2r 27 570 26:7

10. findmin8 29 787 14:8

20 University of California, San Diego Validating High-Level Synthesis

Bugs Found in SPARK

• Array Copy Propagation

• Code motion

Code fragment

Before schedulingAfter scheduling

(Buggy)After scheduling

(Correct)

a[0] := b[1];

c := a[0];

a[0] := b[1];

c := b[0];

a[0] := b[1];

c := b[1];

Code fragment

Before schedulingAfter scheduling

(Buggy)After scheduling

(Correct)

ret[1] := blk[0] <<3;

ret[0] := ret[1];

ret[0] := ret[1];

ret[1] := blk[0] <<3;

ret[1] := blk[0] <<3;

ret[0] := ret[1];

Did not copy array indexRead After Write dependency

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Related Work

• Translation Validation• Sequential Programs [Pnueli et al. 98] [Necula 00] [Zuck et al. 05]• CSP Programs [Kundu et al. 07]

• HLS Verification• Scheduling Step

• Correctness preserving transformation [Eveking 99]

• Symbolic Simulation [Ashar 99]

• Formal assertions [Narasimhan 01]

• Relational approaches for Equivalence of FSMDs [Kim 04, Karfa 06]

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Conclusion and Future Directions

• Presented an automated algorithm for translation validation of the HLS process.

• Implemented it for a HLS tool called SPARK.• Modular: works on one procedure at a time.• Practical: took on average 6 secs to run per procedure.• Easy to Implement: only a fraction of development cost of SPARK.• Useful: found 2 previously unknown bugs.

• In future,• Remaining phases of SPARK: parsing, binding and

code generation.

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Thank You