vlsi interconnects in vlsi design - prof. rakesh k. jha corporate institute of science &...

VLSI INTERCONNECTS IN VLSI DESIGN

- PROF. RAKESH K. JHA

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY , BHOPALDEPARTMENT OF ELECTRONICS & COMMUNICATIONS

Chips are mostly made of wires called interconnect.

Wires are as important as transistorsSpeedPowerNoise

Interconnects in integrated circuits distribute clocks and other signals and provides power and ground to various integrated circuits .

Interconnects can either be local or global .

Local Interconnects

Local interconnects are the first and lowest level of interconnects .they usually connect Gate , Source and Drain in MOS technology and Emitter , Base and collector in Bipolar technology.

In MOS technology , a local interconnect polycrystalline serves as a gate electrode .

Silicide gates and silicides source/drain regions and material like TiN can also acts as a local interconnects .

Local interconnects shows higher resistivity than global . They are small in size but can withstand higher process temperature because they are deposited earlier in process flow than global interconnects.

Global interconnects

Global interconnects generally made of Al are all the interconnect levels above the local interconnects.

They often cover large distances between different devices and different parts of a chip. There fore they are low resistance metals.

Cross sectional view of MOS showing interconnects , contacts, vias separated by diaelectric layers .

Global interconnects provides clock and signal distribution between the functional blocks deliver power /ground to all functions.

Global interconnects occupy top one or two layers and more than 4 mm long .

They can be as long as half of the perimeter of the entire chip.

Ohmic contacts connect an interconnects with active regions and devices in silicon substrate.

A high resistive diaelectric layer usually SiO2 separates the active region to global interconnect.

An electric contacts are made between the interconnect and active region in silicon through openings in the diaelectric layers.

Contacts can be made between local and global interconnects because they are separated by same diaelectric. Connection between two levels of global interconnects are called vias.

Interconnect scaling

Wire Geometry

l

w s

t

h

Pitch = w + sAspect ratio: AR = t/w

Old processes had AR << 1Modern processes have AR 2

Pack in many skinny wires

Wire Resistance

l

w

t

1 Rectangular BlockR = R (L/W)

4 Rectangular BlocksR = R (2L/2W) = R (L/W)

t

l

w w

l

l lR R

t w w

Rs = sheet resistance (W/square)Count number of squares

R = RS * (# of squares)

Sheet ResistanceTypical sheet resistances in 180 nm processLayer Sheet Resistance (W/)

Diffusion (silicided) 3-10

Diffusion (no silicide) 50-200

Polysilicon (silicided) 3-10

Polysilicon (no silicide)

50-400

Metal1 0.08

Metal2 0.05

Metal3 0.05

Metal4 0.03

Metal5 0.02

Metal6 0.02

Wire Capacitance

layer n+1

layer n

layer n-1

Cadj

Ctop

Cbot

ws

t

h1

h2

Wire has capacitance per unit lengthTo neighborsTo layers above and below

Ctotal = Ctop + Cbot + 2Cadj

Capacitance Trend

Parallel plate equation: C = eA/dWires are not parallel plates, but obey

trendsIncreasing area (W, t) increases

capacitanceIncreasing distance (s, h) decreases

capacitanceDielectric constant

e = ke0

e0 = 8.85 x 10-14 F/cmk = 3.9 for SiO2

Processes are starting to use low-k dielectrics

k 3 (or less) as dielectrics use air pockets

Major criteria for interconnect design

Delay

Cross talk Noise

electro migration

THE END