webench power designer/architect 1. 222 webench power designer webench visualizer the webench tool...

WEBENCH Power Designer/Architect

1

222

WEBENCH Power Designer

WEBENCH Visualizer

The WEBENCH Tool Suite

FPGA/Power Architect

AlteraPowerPlay

Power Architect & FPGAs

333

Beginning To End: Design And Prototyping

2. Create a Design

Custom Prototype KitOvernight

Custom Prototype KitOvernight

PrototypePrototype

4. Build It!

Generate Schematic/Generate Schematic/Electrical AnalysisElectrical Analysis

Generate Schematic/Generate Schematic/Electrical AnalysisElectrical Analysis

Generate Layout/Thermal Analysis

Generate Layout/Thermal Analysis

3. Analyze a Design

Select PartSelect Part

Enter SpecificationsEnter Specifications

1. Choose a Part

Optimize for Footprint and

Efficiency, Use Graphs to

Visualize Design

Optimize for Footprint and

Efficiency, Use Graphs to

Visualize Design

4

.

44

Two Ways to Access WEBENCH® Designer

• Use the entry panel on http://www.national.com

OR

• Go to the product folder for a part

WEBENCH Navigation5

Navigation Icons

WEBENCH Tools:PowerLEDLED ArchitectPower ArchitectFPGA Power Architect

5

666

Create and View Design

Dashboard1) Graphs2) Schematic3) Optimization4) Operating

values5) BOM6) Reporting

Op Vals Charts Schematic Optimization

Build It®& Report

BOM/Change ComponentsOp ValsInputs

Controls

Simulation

7

Schematic – Buck Converter

Input Load

Current Path with Switch On

Current Path with Switch Off

Components:

Input Capacitor

Regulator with integrated FET

Inductor

Catch Diode

Output Capacitor

Feedback Network

Feature Controls

8

Visualize Behavior – Power Dissipation

Diode:

Isw*Vf *(1-DutyC)

Inductor:

ILRMS2 * DCR

Cin:

ICinRMS2 * ESR

Cout:

ICoutRMS2 * ESR

Switch:

DC: IswRMS2 * Rsw * DutyC

AC: ½ * Vin * Isw *

(Trise + Tfall)/Tsw

Quiescent: Iq * Vin

Efficiency = Pout / Pin

Pin = Vout * Iout + Pdiss

FET Selection: AC Loss

• PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw

Vsw = -VdsIsw

TriseTfall

Regions of power loss (V*I)

Vg

Vth

Miller Plateau

Vth

Miller Plateau

Vdriver

Vsw

Switch Off On Off

9

10

FET Selection: AC Loss

• PswAC = ½ * Vdsoff * Idson * (trise + tfall)/Tsw

Vsw = -VdsIsw

Trise Tfall

Regions of power loss (V*I)

Vg

Vth

Miller Plateau

Vth

Miller Plateau

Vdriver

Vsw

Switch Off On Off

Low Freq = Low LossHigh Freq = High Loss

11

How To Reduce FET Power Loss

• Choose a FET with low RdsOn• Choose a FET with low capacitance• Lower the switching frequency

BUT• Lowering frequency affects the inductor selection• We want to keep the inductor ripple current constant

– Because this changes the peak switch current and the Vout ripple

12

Inductor Current vs Switch Voltage

Inductor Current

Switch Voltage

13

Inductor Ripple Current

Voltage applied

Inductor Ripple Current (also determines peak switch current and Vout ripple)

dI = (1/L)*V*dt

On

Time

14

Inductor Selection – Lower Frequency

Voltage applied

Inductor Ripple Current (also determines peak switch current and Vout ripple)

Lower Frequency =

Increased On Time =

Increased Inductor Ripple Current =

Increased Peak Switch Current and Increased Vout Ripple

Higher frequency:

If L is kept constant, ILpp increases

Lower frequency:

dI = (1/L)*V*dt

On

Time

15

Inductor Selection – Raise Inductance

Voltage applied

Inductor Ripple Current (also determines peak switch current and Vout ripple)

Higher frequency:

If L is kept constant, ILpp increases

Lower frequency:

dI = (1/L)*V*dt

On

Time

So we need to increase L

Lower frequency with higher inductance:

16

Effect Of Lower Frequency On Inductor

• If we keep the inductor ripple current constant by increasing the inductance:– The inductor gets larger (more turns)– The inductor power dissipation goes up (longer wire)

17

Optimization – Efficiency vs Footprint

Left side:

Higher frequency

Smaller footprint

Right side:

Lower frequency

Lower resistance

18

Optimization Summary

• To get high efficiency– Decrease frequency to reduce AC losses– Choose components with low resistance

• To get small footprint– Increase frequency to reduce inductor size– Choose components with small footprint

• Cost• These parameters are at odds with each other and

need to be balanced for a designer’s needs• Tools are available to visualize tradeoffs and make it

easier to get to the best solution for your design requirements

191919

WEBENCH Power Designer

WEBENCH Visualizer

The WEBENCH Tool Suite

Power Architect & FPGAs

202020

WEBENCH Visualizer-Calculates 50 Designs In 2 Seconds

Charts

Recommended Solutions

212121

Calculated BOM Footprint, BOM Cost and Efficiency

Footprint vs Cost vs Efficiency

222222

Graphical Plot Gives At A Glance TradeOffs

Click on square to resize the plot to full screen size

Hover to see details

Click and drag to zoom

Bubble Size = BOM PriceChange plot parameters

23

Why Are The Solutions Different?

23

242424

Give The Customers What They Want:Best Efficiency, Footprint and BOM Cost

• Default Setting: LM22676, 80%, 411mm2, $2.88

• Smallest Footprint: LM25011, 75%, 297mm2, $2.47

• Highest Efficiency: LM3150, 94%, 1320mm2, $6.77

• Comparing different designs up front, achieves better results than optimizing 1 part after creating a design

252525

WEBENCH Power Designer

WEBENCH Visualizer

The WEBENCH Tool Suite

Power Architect & FPGA Architect

262626

Design This Power Supply In Seconds?Many Loads, Many Supplies

• Core Supply 1.25V@3.0A

• FPGA IO 3.3V@0.5A

• Vcca 3.3V@0.2A

• Flash 3.3V@2.0A

• SDRAM 1.8V@1.0A

• CCD 2.5V@0.2A

• PLL 1.25@0.2A

• Motor Control 12V@2.0A

• Miscellaneous 3.3V@2.0A

9 Loads and 5 Voltages

Why Do Designers Use Reference Designs So Frequently For Complex FPGAs?

• Cyclone IV GX - EP4CGX150• User guide: 463 pages, 10MB• 20-30 pages of power details

• Spartan-6 - XC6SLX100T• 40+ separate reference guides and datasheets: ~2000 pages, 90MB• 15 pages critical for power details

• Each specification includes challenging requirements and exceptions– Voltage, current, ripple, frequency, accuracy, soft start, supply

isolation, and pin specific limitations

• Every complete system has additional loads beyond the FPGA loads, adding more to the complexity

27

Minutes, right?

With Confidence?

WEBENCH® FPGA Power Architect

Add FPGA

Select Device From List

Configure Loads

28

2929

Get FPGA Load Current From Vendor Estimation Spreadsheet: Xilinx

29

Spreadsheet calculates the current

3030

Update Load Current Into Preconfigured FPGA Dependency Template

30

Voltage, Current,

and Special

Requirements

Included For:

• Max Voltage Ripple

• Isolated Supplies

• Soft Start

• Post Supply Filters

• LDO Preferred

Add All Of Your Own Additional System Loads

Next

313131

Each Architecture Is Tuned With The WEBENCH Optimizer, Now For Systems

Optimizer Dial

System Efficiency 92%76%

Size

8000

2000

Relative System Cost

WEBENCH FPGA Power Architect Selects The Best Solutions For Every Rail

Intermediate Rail (12V) Supply 2 (1.25V)

Supply 4 (1.8V)

Supply 3 (3.3V)

Supply 5 (2.5V)Lo

ads

32

333333

Presenting The User With The Intermediate Rail Options And Performance Trade-Offs

Intermediate Rail Options Can Be Reviewed & Compared Quickly

23V

3V

No I-Rail

12V

5V

12V

Smallest FootprintHighest Efficiency

Lowest Cost

12V

5V

343434

Analyze Performance, Cost and Footprint for Selected Architecture

Click on Each

Supply To Display

Detail

Go

353535

WEBENCH® FPGA Architect Leverages The WEBENCH Dashboard

Click on Each Supply To Analyze Design

Advanced Tools Are Available For Further Exploration

Power Topology

Bill of Materials

Optimization GraphsCharts

& Design Reports

Drive

Circuits

Simulation

Prototyping

System Op Vals

Optimizer

Share Design

System Summary

36

37

Complete FPGA Power Supply Design Reporting – Automatic Generation

Your Design From The Top: Inputs, Supplies, Schematics,

BOMs

383838

Hands On Exercise

What is the system with the:

Smallest footprint

Highest efficiency

Lowest cost

Source: 18 – 32V

Loads:

LCD Panel: 3.3V, 0.2A

Flash Memory: 1.8V, .05A

Freescale QorIQ P2020

Avdd: 1.05V, 1A

BVdd: 1.8V, .06A

Cvdd: 1.8V, .02A

Gvdd: 1.5V, .9A

LVdd: 2.5V, .1A

OVdd: 3.3V, .01A

SVdd: 1.05V, .4A

Vdd: 1.05V, 5.6A

XVdd: 1.05V, .4A

Design Problem: Goals:

39

Summary

• WEBENCH Visualizer – View up to 50 designs at a time to get the best solution for a

single power supply– Each design optimized for efficiency, cost and size

• WEBENCH Power Architect– System level designs for complex multiple load applications– Provides different rail architectures– Each system optimized for efficiency, cost and size

• WEBENCH FPGA/Processor Power Designer– Preconfigured FPGA and processor loads including

noise/filter requirements

• WEBENCH saves you time!

Thank You!Try WEBENCH® FPGA Power Architect yourself:

http://www.national.com/fpga_power_architect

LED Architect:http://www.national.com/led_architect

Jeff Perry

Jeff.Perry@nsc.com