amsat eagle - 70 cm receiver circuit description

Rev. 3 5-12-2006

AMSAT Eagle – 70 cm Receiver Description

AMSAT Eagle – 70 cm Receiver Circuit DescriptionJ. B. Stephensen, AMSAT-NA

1. Introduction

This document describes the 70-cm receiver to be used in the AMSAT Eagle satellite.Two redundant receivers are used for the U/V and U/S analog transponders. Thetransponder passband is 84 kHz and is established by digital signal processing in theSDX module. This receiver provides the 10.7 MHz input to the SDX and has a widerpassband. It has a 6-dB maximum noise figure and 3-dBm minimum IIP3. The receiveris designed to handle +12 dBm input pulses so that PAVE PAWS RADAR will notdamage any internal circuitry at low altitudes.

Each receiver provides two 10.7 MHz outputs to drive redundant SDX modules. Theoutputs clip at -6 dBm and the total gain is adjusted to 36-37 dB.

2. Description

The receiver is a dual-conversion superheterodyne that covers the 435-438 MHzamateur satellite band using a 199 MHz first IF and 10.7 MHz second IF output, asshown in figure 1. Dynamic range is maximized to minimize RADAR interference.

Figure 1 – Block Diagram

The higher than normal first IF allows the use of high-Q SAW filters to provide a narrowbandwidth as close to the first mixer as possible. The low frequency second IF allowsthe use of inexpensive FET switches in the QSDs contained in the SDX module thatfollows the receiver. The local oscillators are controlled by PLLs. This allows the first LOto be tuned in order to relocate the RF input frequency for use different satellitelaunches and in case of interference from other satellites. The RF amplifier has a veryhigh third-order intercept (IP3) point to prevent intermodulation with RADAR pulses. Ahigh-current Gilbert cell first mixer is used to maximize IP3 within the RF bandpass whileproviding enough gain to compensate for the loss of the first SAW filter.

Rev. 3 5-12-2006


The following sections describe each page of the circuit shown in the 3 page schematicdiagram. Note that the schematic shows several RF chokes, labeled RFC1-RFC11.These are ferrite beads. All components are 0805, unless noted. Capacitors andinductors have a 5% tolerance. Resistors have a 1% tolerance. Thermal analysis wasdone for the 3 highest dissipation devices and is discussed in the following sections.

2.1 RF Amplifier, First LO and First Mixer The receiver input connects to Z1, a single-pole 436 MHz microstrip filter. This is atapped ¼-wavelength resonator that is present to attenuate 2-m and 13-cm transmittersignals and prevent overload of the RF amplifier. The insertion loss is minimal so thatthe receiver noise figure can be as low as possible with minimal gain. Excessive gainwould compromise dynamic range.

U2, a SiGe RF amplifier MMIC with a 3.8 dB max. NF, then boosts signal levels by 20dB. Collector bias of 5 VDC at 82-98 mA is provided via RFC8 and L1. C30 resonateswith L1 at about 436 MHz with a Q of ½ and C3 and C4 bypass the cold end of L1. 4paralleled 1210 resistors form R1 in order to minimize the effect of an open resistor.400-500 mW is consumed in the IC and bias resistors to allow an OIP3 of 31 dBm,which is 6 dB higher than the mixer IIP3 as seen through FL1. The RF amplifier IIP3 isgreater than 17 dBm.

This IC dissipates the most power of any in the receiver and will have a temperaturerise of 24-30 °C in a SOT-89 package, if the case to ambient thermal resistance can bekept below 10 °C/W.

The image is stripped in FL1, a 3-pole helical filter with a 10 MHz bandpass at -1 dB.Attenuation is -30 dB at ±50 MHz and the maximum insertion loss is 4.5 dB. 3 series-connected antiparallel Schottky diode pairs, D1-D3, follow the filter. They limit themaximum input to the first mixer to +11 dBm and also protect the first IF filter, which israted at +15 dBm.

The local oscillator, U6, is a ½” square VCO module with a 3 to 9 dBm output and lessthan -106 dBc/Hz of phase noise at a ±10 kHz offset as shown in figure 2. C17, C18and RFC3 provide power supply bypassing. R3, R4 and R5 form a power splitter with a50Ω input impedance, 100Ω output impedance and 8 dB loss. This matches theimpedance of PCB traces and provides a -5 to +1 dBm drive level for the PLL andmixer.

The VCO is controlled by U4, a silicon-on-insulator CMOS PLL from PeregrineSemiconductor that is immune to latch-up. See figure 3 for a block diagram. The phasedetector operates at 100 kHz and the reference input (pin 20) is at 5 MHz. The VCOinput requires -8 to +2 dBm.

Rev. 3 5-12-2006


Figure 2 – 1st LO Phase Noise

Figure 3 – PLL IC Block Diagram

U5 is a low-noise (4nV/Hz½) rail-to-rail op amp that converts the 3V up and down phasedetector outputs to a 0-9.5V DC level. U5, R10, R11, C23 and C24 form an integrator,with a time constant of approximately 500 ms, which determines the loop bandwidth.C21, C22, R6, R7, R8, R9, R12, C19 and C20 provide additional low-pass filtering atten-times the loop bandwidth to attenuate spurs. The control voltage is halved by avoltage divider (R12 and R62) to provide 0-4.75 V to the VCO. This reducescontributions to phase noise by the op amp. Since U5 controls the VCO frequency, itmust have very clean power. Q1, a high-beta low-noise transistor, R14 and C28 filterout low frequency ripple and noise. R15 and C29 provide high frequency filtering. Q3,R53, R54, C89 and C90 filter VCO power.

Rev. 3 5-12-2006


U3 is a high-level Gilbert-cell mixer that converts the 435-438 MHz RF input to a 199MHz first IF with 1 dB of gain. It has a balanced 18Ω input and a balanced 400Ω output.T1, a 1:1 transformer with a center-tapped secondary, and L2, L3 and C5, which forman L-network, match the input. The output impedance is transformed to 200Ω by L4, L5and C10. L6, L7 and C31 resonate at 199 MHz and provide +5V to the collectors of theoutput stage while C13, C14, C15, C16, RFC1 and RFC2 bypass the power supply.C11, C12 and L8 match the SAW filter, FL2, to 200Ω. The maximum current of 74 mAat 5.25 VDC results in a temperature rise of 15 °C as the exposed pad and ground andvoltage planes provide a heat sink. The LO input is -10 to -2 dBm for lowest NF so a 3dBV voltage divider, R1 and R2, is used.

2.2 First IF, Second LO and Second Mixer

The first IF amplifier uses two 200 kHz wide (-1 dB) SAW filters, FL2 and FL3, toattenuate PAVE PAWS emissions on adjacent frequencies. These filters have 0.5-dBPPripple each. Figure 4 shows the attenuation curve for one filter. U7 is a differentialamplifier, with 19-21 dB of gain, which compensates for the 6-7 dB loss in each filter.The 200Ω I/O impedance is matched to the filters by C32, C33, C59, C60, L10 and L11.Diode pair D4 limits the input signal level to -5 dBm so that the output SAW filter is notdamaged by RADAR pulses.

Figure 4 – 1st IF Frequency Response (1 filter)

The IF output is converted to 10.7 MHz by U8, a low-power Gilbert cell mixer andamplified by U12, a high-frequency low-noise op amp. The mixer converts the 199 MHzIF input to a 10.7 MHz second IF. It has a balanced 18Ω input and a balanced 400Ωoutput. The mixer power gain is 1 dB, but the voltage gain is 10 dBV because of thehigher output impedance. L13, L14, L15, L16, C36 and C37, form a 2-stage L-networkto match the input to 200Ω. L17, L18 and C60 resonate at 10.7 MHz and provide +5V tothe collectors of the output stage while C42, C43, C58, C59, RFC5 and RFC6 bypassthe power supply. The LO input is -10 to -2 dBm for lowest NF so a 2 dBV voltagedivider, R62 and R63, is used.

Rev. 3 5-12-2006


U12 is a voltage-feedback operational amplifier with 3 nV/Hz½ of voltage noise and 3pA/Hz½ of current noise for a 9 dB NF at 400Ω. It provides a voltage gain of 8 dBV,converts from a balanced output to single-ended and provides higher drive currentcapability. The mixer’s +5 V supply provides the common-mode bias and R26, R27,R28 and R29 set the gain.

The local oscillator, U11, is a ½” square VCO module with a 0.5 to 8 dBm output and -107 dBc/Hz of phase noise at ±10 kHz as shown in figure 5. C56, C57 and RFC7provide power supply bypassing. R57, R58 and R59 form a power splitter with a 50Ωinput impedance, 100Ω output impedance and 8 dB loss. This matches the impedanceof PCB traces and 8 dB loss. This matches the impedance of PCB traces and providesa -7.5 to 0 dBm drive level for the PLL and mixer.

The VCO is controlled by U9, a silicon-on-insulator (SoI) CMOS PLL from PeregrineSemiconductor that is immune to latch-up. The phase detector operates at 100 kHz andthe reference input (pin 20) is at 5 MHz. The VCO input requires -8 to +2 dBm.

Figure 5 – 2nd LO Phase Noise

U10 is a low-noise (4nV/Hz½) rail-to-rail op amp that converts the 3V up and downphase detector outputs to a 0-10V DC level to drive the VCO. U10, R23, R24, C52 andC53 form an integrator that determines the loop bandwidth. C50, C51, R19, R20, R21,R22, R25, C54 and C55 provide additional low-pass filtering at ten-times the loopbandwidth to attenuate spurs. Since U5 controls the VCO frequency, it must have veryclean power. Q2, a high-beta low-noise transistor, R16 and C44 filter out low frequencyripple and noise. R17 and C45 provide high frequency filtering. Q4, R55, R56, C91 andC92 filter VCO power.

Rev. 3 5-12-2006


2.3 Clipper, Power Supply and Control Circuits

The final IF amplifier stage, U13, is a clipper IC that has very low distortion near theclipping threshold. R33, R34 and R35 set the clipping level to ±1 V. R40 isolates theinput during clipping. R31, R32 and C67 set the AC gain to 6 dBV while leaving the DCgain at 0 dBV. The output is split by a resistive divider (R36, R37, R38 and R39) andappears on the two output connectors (J2 and J3). The amplifier OIP3 is +41 dBm, but isreduced 2 dB by the intercept points of previous stages.

The common reference oscillator aboard Eagle provides 10 MHz at around 0 dBm viaJ4. C69, L20 and R41 form an L-network that raises the input level which is then issquared by U14, an unbuffered inverter, and then divided by 2 in U15. R42 and C70provide DC bias to the squaring circuit and R43 and R44 provide series termination forthe PCB traces to the PLL ICs. The divider is necessary as the reference dividers in thePLLs have only 6 bits.

The receiver is controlled by an SPI bus that has 1 clock, 1 data and 2 enable signals.U20 interfaces a CANDO module to the receiver by using pull-up resistors and Schmidttriggers to create clean 3-volt CMOS logic levels. The 2 devices being controlled are the1st LO PLL and the 2nd LO PLL. The reference dividers should be set to 50 so that theLO frequencies can be tuned in 100 kHz increments.

Three voltages are required inside the receiver. The analog circuitry operates from +10V, +5.5 V and +5 V while the digital circuitry uses +3V.

10 V is generated from the 14 V input by U16, a 500 mA low-noise, low-dropout linearregulator. R51 and R52 set the output voltage. C81, C82, C83 and C84 provide inputand output bypassing. C85 bypasses the internal voltage reference. The maximumvoltage drop is 4 VDC and 340 mW is dissipated with 85-mA output current and thetemperature rise could reach 25 °C. Heat is dissipated though an exposed metal pad onthe bottom of the SO-8 case. This must be soldered to the PCB and adequate copperarea and feed-through holes must be provided to thermally couple to the mountinghardware and conduct heat to mounting surface of the module.

The lower voltages are created by converting the 14 V input to 6.6 V with U17, a high-efficiency 200 kHz switching regulator. This is much lower than the 2nd IF frequency butthe circuitry may still require shielding. C71, C72, C86 and RFC8 provide input filtering.D3 is the catch diode and L21 and C73 provide filtering of the PWM output waveform.C74, C87 and RFC9 provide additional output filtering and D6 protects against transientvoltage spikes. Note that D3 must be a Schottky rectifier in order to minimize theforward voltage drop and maximize efficiency. L21 must be wound on a highpermeability iron-powder or ferrite core and flux density must be well below saturationlevels over -20 to +70 C. A torroidal or pot core should be used to minimize externalmagnetic field strength. The switcher output is converted to 5.5 V, 5 V and 3 V by threelow-dropout linear regulators.

Rev. 3 5-12-2006


The 5V regulator, U18, is a low-noise fixed-voltage unit that powers analog circuitry.C75, C76 and C80 provide input and output bypassing. C88 bypasses the internalvoltage reference. Note that C75 must have a series resistance less than 3 ohms. Thisis easily met with any tantalum capacitor. Ceramic capacitors should be avoided. Amaximum of 450 mW is dissipated with 240 mA output current and the temperature risecould reach 32 °C. Heat is dissipated though an exposed metal pad on the bottom ofthe SO-8 case. This must be soldered to the PCB and adequate copper area and feed-through holes must be provided to thermally couple to the mounting hardware andconduct heat to mounting surface of the module.

U20, a standard low-dropout voltage adjustable regulator, provides 5.5 V for the VCOs,in order to allow for a voltage drop in the active filters, Q3 and Q4. R57 and R58 set theoutput voltage and C93 provides bypassing. Note that C93 must be a capacitor with aseries resistance of 0.2-10 Ω in order to prevent instability. Tantalum capacitors areadequate.

The 3V supply runs logic so U19 is a standard regulator. C77, C78 and C79 bypass theinput and output pins. C77 must have a series resistance of 0.2-10 Ω.

3. Conclusions

The receiver meets the 70-cm receiver requirements for third-order input intercept pointat ±1 MHz (2 dBm) and noise figure (7 dB) as shown in figures 6 and 7. Gain isassumed to vary by ±1 dB and noise figure by +1 dB from nominal values.

Figure 6 - Worst Case Front End Input Intercept Point

Rev. 3 5-12-2006


Figure 7 – Worst Case Noise Figure

Figure 8 shows that the worst-case narrow-band third-order input intercept point occurswhen the IIP3 of each stage is at the minimum and the gain of each stage is at themaximum. The –80 dBc OIP3 requirement is just met when signals have an 80 dB SNR.

Figure 8 – Worst Case Narrow-Band Input Intercept Point

Rev. 3 5-12-2006


Note that the gain of U12 is adjusted between +8 and +18 dBV to compensate forvariations in the gain of the amplifiers, mixers and filters. This compensates forvariations in the IC manufacturing process. There will be a residual gain variation of upto ±1.5 dB over the operating temperature range. After assembly, selecting the valuesof R28 and R29 sets the receiver gain.

Unlike previous receivers, the passband frequency may be varied in 100 kHzincrements by the IHU so that the uplink frequency band can be adjusted to avoid futureinterference sources.

The DC power requirement is 250 mA, assuming an 85% efficient switching regulatorand maximum quiescent current drain on every IC. With 14 VDC input, the receivermodule dissipates 3.5 W so no special mounting considerations are required.

amsat eagle - 70 cm receiver circuit description

Documents