an-104 qfn pcb layout guidelines rev8 · pad (cpl) to be minimum 0.15mm to prevent solder bridging....

AN-104 Rev 8, 26-May-17

Innovative PowerTM ActiveSwitcherTM is a trademark of Active-Semi.

1

PCB Layout Guidelines for QFN Package

Abstract This Application Note provides PCB designers with a set of guidelines for successful board mounting of Active-Semi’s widely used QFN. It includes example PCB land patterns, thermal via designs, stencils, and solder mask openings.

Introduction The QFN package is a leadless package which makes electrical contact to the PCB by soldering the bottom surface of the package to the PCB (Figure 1 and Figure 2). The QFN package’s Exposed Pad enhances the thermal and electrical properties of the package. The die pad attaches to the Exposed Pad on the bottom of the package, providing excellent thermal conduction between die and exterior of the package. Proper footprint and thermal design is critical for reliable mechanical connection of the package to the PCB and for taking full advantage of the QFN thermal properties.

Figure 1. Bottom view of a QFN55-40 package

Figure 2. Section view of QFN55-40 package soldered onto a PCB

AN-104 Rev 8, 26-May-17


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PACKAGE DIMENSION For robust board assembly and board level reliability, the PCB layout and stencil designs are critical to ensure sufficient solder coverage between package and PCB. When designing the PCB layout, please refer to the Active-Semi’s package Outline and Dimension drawing in the datasheet to obtain the package dimensions and tolerances. Figure 3 shows an example of a QFN55-40, 0.4mm pitch package outline drawing. The D, E, b, e, L, D2, E2 dimensions are critical to design and layout the PCB.

Figure 3. QFN55-40 Package Outline Drawing

AN-104 Rev 8, 26-May-17


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PCB LAYOUT GUIDELINES Figure 4 below demonstrates how to design the PCB landing pattern for a 5 x 5 mm - 40-pin, 0.4mm -pitch package. The PCB designer needs to design the Pads and Thermal Pad according to the Package Outlines and Dimensions provided in the Active-Semi datasheet. Below are recommended basic calculation for each dimension:

ZDmin = Dmax + 2(0.25)

ZEmin = Emax + 2(0.25)

GDmin = Dmin - 2Lmax - 0.1

GEmin = Emin - 2Lmax - 0.1

PDmax = GDmin - 2CPL where CPL = 0.15

PEmax = GEmin - 2CPL where CPL = 0.15

Figure 4. PCB land pattern of a QFN40L Package

CPL

CLL

PCB land pattern (Orange)

Lead finger dimension (Green)

ZE

MIN

GE

MIN

PE

MA

X

PDMAX

ZDMIN GD

MIN

AN-104 Rev 8, 26-May-17


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PCB Lead Figure Land Pattern Design In general, the PCB lead finger pad should be designed slightly wider and longer than the IC Exposed Leads.

The Pad length (Y) should be designed at least 0.3mm longer than the package terminal length (L) for good filleting. The pad length should be extended 0.05mm towards the center line of the package.

The Pad width (X) should be a minimum 0.05mm wider (0.025mm each side) than the package terminal width (b) as shown in Figure 5 below.

Figure 5. Lead Pads Notice: PCB designer must keep enough clearance between Lead Pads (CLL) and from Lead Pads to Thermal Pad (CPL) to be minimum 0.15mm to prevent solder bridging.

PCB Thermal Pad Land Pattern Design The PCB’s Thermal Pad is the exposed copper area which is not covered by the solder mask. This Thermal Pad must be soldered directly to the Exposed Pad on the bottom of the IC. This thermal Pad should be made as large as possible to improve the thermal and electrical characteristics.

AN-104 Rev 8, 26-May-17


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Thermal Pad Via Design

Active-Semi highly recommends using multiple vias inside the thermal pad area to conduct heat from the top layer to the inner or bottom layers. Correct layout of these vias greatly improves the thermal characteristics of the IC as well as electrical performance. Figure 6 shows example via placement. The following are dimensional rules for thermal pad area vias:

Pitch: 1mm to 1.2mm pitch

Diameter: 0.3mm to 0.33mm

The number of vias included in a PCB layout is application-specific and depends upon the package power dissipation and electrical conductivity requirements. Thermal and electrical analysis and/or testing are recommended to determine the minimum number of vias required. Figure 7 shows Active-Semi’s recommendations for solid vias which directly connect to copper. Active-Semi does not recommend thermal relief vias.

Thermal Pad Via Design (Continued)

Figure 6. Thermal Via Placement

Figure 7. Solid vs Thermal Relief Via

(Recommended)

Copper

(Not Recommended)

Solid Via Thermal Relief Via

AN-104 Rev 8, 26-May-17


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Solder Mask Openings Pads can be either Non-solder mask defined (NSMD) or solder mask defined (SMD). A NSMD pad is defined by having a metal pad on the PCB that is smaller than the solder mask opening. A SMD pad is defined where the copper is larger than the solder mask opening. In this case, the solder mask opening is smaller than the copper and defines the size of the pad.

Active-Semi recommends Non Solder Mask Defined (NSMD) pads when possible. NSMD pads provide better solder joint reliability. Solder mask should surround each pad, with masking pattern 60 - 70μm larger than the pad size. The solder mask can be designed around each individual lead pad for lead pitches greater than 0.65mm. However, most of the Active-Semi QFN package products use lead-to-lead pitch equal to 0.5mm or smaller. For these packages it is recommended to design the solder mask around all pads on each side. In order to maximize the solder mask between adjacent sides, it is necessary to round the inner corner on each row. This will ensure sufficient solder mask in the corner of the PCB footprint design as shown in the Figure 8 below.

Figure 8. PCB Pads and Solder Mask Opening Design

AN-104 Rev 8, 26-May-17


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SOLDER PASTE AND STENCIL

Solder Paste Type

Active-Semi highly recommends customer to use type3 or type 4 solder paste in mounting QFNs to archive high assembly yield. Follow JEDEC/IPC J-STD-20D.1 for standard reflow procedure recommendations.

Solder Stencil for Lead Pads

The stencil aperture opening should be designed to maximum paste release. This is typically accomplished by considering the following two ratios:

AREA RATIO = Area of Aperture opening / Aperture Wall Area

ASPECT RATIO = Aperture Width / Stencil Thickness

Area Ratio should be greater than 0.66.

Aspect Ratio should be greater than 1.5.

Solder Stencil for Thermal Pads

For large Thermal Pad area with the size larger than 25mm2, Active-Semi recommends using cross-hatching in the thermal pads stencil opening of a QFN package (as shown in Figure 9). Cross-hatching will prevent excessive amount of applied solder paste, thus reducing the risk of solder bridging.

Figure 9. Thermal Pad Stencil Opening for Large Thermal Pad

Layout Guideline Examples The following pages provide recommended PCB land pattern, thermal vias, solder mask opening, and stencil design for different packages.

Recommended Not Recommended

Solder Paste applied No Solder Paste applied

AN-104 Rev 8, 26-May-17


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40L-FCSLP EXAMPLE

4.1

3.2

3.2

40x0.25

5.8

36x0.4

5.8 PCB Layout Pattern Solder Mask Opening

Thermal Vias Design Stencil Design

Note1: All dimensions in mm

Note2: The ACT8870 uses this special package

1.4

4.0

5.9

4x3.9

AN-104 Rev 7, 5-Apr-17


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28L-FCSLP EXAMPLE

PCB Layout Pattern Solder Mask Opening

Thermal Vias Design Stencil Design Note1: All dimensions in mm


24x0.5

4.0

5.7

1.32

1.16

1.51

0.65

0.85

1.34

1.06

2.05

28x0.3

5.7

2.8

1.25

3.0

1.8

0.7

2.85

1.31.3

1.2

AN-104 Rev 7, 5-Apr-17


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32L-FCSLP EXAMPLE



For the Thermal Via Design, the PCB designer may put 4x of 0.3mm vias in the middle pad. Note1: All dimensions in mm


1.85

3.1

32x0.25

4.8

28x0.4

4.81.85

0.72x0.5

3x0.5

0.7

1.525

1.2

3.4

1.15

0.3

1.7

0.3

0.3

19x0.85

45o

0.95

2.35

4.9

4.9

1.95

3x0.852x0.85

1.625

1.25

2.65

1.15

0.35

1.575

0.95

0.75

0.75

0.75

0.851.1

1.55

3.15

10.95

0.95

1.05

1.95

1.2

1.8

32x0.2228x0.4

4.8

1.8

0.7

2x0.5

3x0.5

0.7

3.35

1.7

0.75

0.25

0.25

1.2

AN-104 Rev 7, 5-Apr-17


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TQFN1010-57 EXAMPLE




Note2: The PAC5250 uses this special package

10.6

3.0

22

1

4.254.25

0.625 1.6251.125

0.625

0.99

1.4

8.9

3.15

1.5

75

1.57

5

3.0

1

1.715

10.57

0.5 (51x)0.22 (57x)

2.25

2.754.250.82

0.25

AN-104 Rev 7, 5-Apr-17


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TQFN88-43 EXAMPLE




Note2: The PAC5253 uses this special package

8.6

1.53

0.5 (37x)0.25 (43x)

3

1

Ø0.3 (20x)

3.453.25

0.850.6256

.9

4.6

5

1.4

1.8

8.57

2.675

3.25

3.25

0.625

0.625

2.675

an-104 qfn pcb layout guidelines rev8 · pad (cpl) to be minimum 0.15mm to prevent solder bridging....

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