An 802.11a/b/g SoC for Embedded WLAN Applications

Lalitkumar Nathawad1, David Weber2, Shahram Abdollahi2, Phoebe Chen1, Syed Enam1, Brian Kaczynski2, Alireza Kheirkhahi1,

MeeLan Lee2, Sotirios Limotyrakis1, Keith Onodera2, Katelijn Vleugels2, Masoud Zargari1, Bruce Wooley3

1Atheros Communications, Irvine, California2 Atheros Communications, Santa Clara, California3 Stanford University, Stanford, California

Outline

• Introduction⇒ Embedded WLAN applications

• SoC block diagram

• Power management

• Transceiver architecture⇒ 5GHz/2.4GHz transmitter

⇒ 5GHz/2.4GHz receiver including ADC

⇒ Frequency synthesizer

• Measurement results

Embedded WLAN

• Applications: Wi-Fi phones, digital cameras, networked gaming, PDAs, MP3 players, etc.

⇒ Long battery life → low sleep/standby power

⇒ Small form-factor → single chip integration

• Support for wide range of crystal frequencies⇒ Share crystal oscillator with host system

• Support for common I/O interfaces⇒ SDIO, SPI, CF, etc.

• Dual-band operation at 2.4GHz and 5GHz

SoC Block Diagram

RFTransceiver

Dat

a C

on

vert

ers

Dig

ital P

HY

& M

AC

I/O In

terf

ace

Power Management CPUBB

19.2, 24, 26, 38.4, 40 or 52 MHz crystal or external reference

Low frequency32kHz crystal

SoC

RX

/TX

& D

iver

sity

Sw

itch

es

5G

2.4G

5G

2.4G

Ant1

Ant2

PLL

HostSystem

Power Management

• Operating modes: Sleep, Standby, RX, TX

• Programmable LDO regulators used to lower the supply voltage in sleep mode

⇒ All register states maintained.

⇒ Reduced supply leakage current

• Standby power depends on RX duty cycle⇒ Reduce power by staggering the power-on of

analog blocks based on settling time.

⇒ Gate clock signals to inactive digital circuits

⇒ Run off of the 32kHz clock when idle

Sliding-IF Architecture

• Only one synthesizer needed to generate LO frequencies

• fVCO = 2/3 fRF5, 4/3 fRF2 → No LO Pulling

LO1 = 2/3 fRF fRF

LO2 = 1/3 fRF

IFBaseband

2.4GHz Band: 2.412 - 2.484 GHz5GHz Band: 4.9 - 5.925 GHz

I & Q

Dual-Band Transmitter

DAC

DAC

÷2

÷2

–Σ

Σ–

I

Q

I

Q

5G

2.4G

11

11Q

I

RF/IF Gain Ctrl

LORF5 =

RF Gain Ctrl

BB Gain Ctrl

fRF523

LORF2 = fRF223

PA RFVGA1 & 2

PA RFVGA IFVGA

3rd-Order LPF

160/176 MS/s

Transmit Power Control

• 5b DAC to correct power detector DC offset

• TX gain adjusted on a per packet basis

Transmitter

External PA

DAC

SoC

Σ

DigitalControl

5

TX gain

average2nd OrderΣ-∆ ADC

Coupler

PowerDetector

Dual-Band Receiver

DAC

BB Gain Ctrl

÷2

I

Q

5G

9

9Q

I

LORF5 =

RF Gain Ctrl

fRF523

LNA RFVGA

DualInputADC

÷2

I

Q

2.4G

LORF2 =

RF Gain Ctrl

fRF223

LNA RFVGA

DAC

I Offset Correction

Q Offset Correction

40/44 MS/s

5GHz: NF = 5.5dB2.4GHz: NF = 5.0dB

Dual-Input A/D Converter

• Time-multiplexed pipeline architecture⇒ I & Q inputs are sampled simultaneously

⇒ Pipeline stages run at 80/88 MHz (2×fS)

• Almost half the area and similar power as 2 non-multiplexed ADC’s

⇒ Area: 0.45mm x 1.0mm, Power: 48mW

S/HI

Q

6 stage pipeline1.5b/stage

4-bitFlash

Decode &

De-mux

9

9I

Q

ADC Sample/Hold Circuit

φS

φS

Ip

In

Qp

Qn

φH,Q

φH,I cmioutn outp

φH,Q

φH,I

φS

1/fS, fS = 40 / 44 MS/s

φS

+– +

–

Sample Hold I Hold QWait

C1

C2

C3

C4

Fractional-N Synthesizer

VCO

fREF

fVCO

up

dn

3.2 - 4 GHz

Σ-∆Modulator

3

P & S counters

÷ 8/9Prescaler

Regulator

To LO Buffersand Dividers

3rd Order Loop Filter

Ref.Div.

19.2 - 52 MHz

coarse tuning

8

R,C cntrl

Regulator

VC

ICP cntrl

ICP

Frequency Divider

fVCO8P+S+NΣ-∆

PFD

CPZ(s)

Xtal Osc

CMOS LC-tank VCO• Tuning range:

3.2 - 4 GHz⇒ 8-bit switch-capacitor

bank for coarse tuning

⇒ diode varactor for continuous fine tuning

• Voltage-to-freq. gain:

• Large variation in KVCO:KVCO = 34MHz/V @3.2GHzKVCO = 66MHz/V @4GHz

KVCO 2π2

L fVCO3 C∂

VC∂-----------⋅ ⋅=

Vbias

VC

Synthesizer Design

• Loop Gain = , where

⇒ ICP is digitally varied as 1/ for constant loop gain over tuning range.

• On-chip programmable loop filter, Z(s)⇒ Program for 50° PM with given fREF

⇒ Optimize loop BW for low integrated PN

⇒ For stability, 3rd pole of Z(s) >> loop BW.

ICP Z s( ) KVCO⋅ ⋅

s Ndiv⋅----------------------------------------------- Ndiv

fVCOfREF--------------=

fVCO2

LO Buffer with AGC

• Inductively-tuned

• 3.2GHz < LORF5 < 4GHz

• Desire an LO amplitude ≈1Vdiff

• Use AGC to minimize bias current⇒ 3.5mA < Itail < 12mA

over P.V.T. & freq.Itail

LOin

LOout

Vref

peakdetector

5GHz TX Phase Noise

10M1M100k10kFrequency Offset (Hz)

–93dBc/Hz

–110dBc/Hz

-80

-100

-120

-140

Center Frequency: 5.32GHz

Ph

ase

No

ise

(dB

c/H

z)

Σ-∆ Modulator Noise Contribution

10M1M100k10kFrequency Offset (Hz)

-80

-100

-120

-140

Center Frequency: ≈5.2GHz

Ph

ase

No

ise

(dB

c/H

z)

With Σ-∆ Modulation

9dB

No Modulation

Transmit EVM @Pout ≈ –4dBm

2400

2420

2 440

246 0

2 480

Channel Frequency (MHz)

-30

-29

-28

-27

-26

-25

-24

EV

M (

dB

)

5000

520 0

5 400

560 0

5 800

6000

2.4GHz Band 5GHz Band

802.11g spec. 802.11a spec.

2.7dB 2.2dB

Receiver Sensitivity

2400

2420

2440

2460

2480

Channel Frequency (MHz)

-100

-95

-90

-85

-80

-75

-70

-65

-60

Sen

sitiv

ity

(dB

m)

5000

5200

5400

5600

5800

2.4GHz Band 5GHz Band

6 Mbps

6 Mbps

54 Mbps

54 Mbps

802.11g spec.

11dB

12dB

802.11a spec.

4dB

5dB

Die Photo

Digital MAC & Baseband

CPU

Ho

st I/

F

RX

BB

FIL

TE

R

ADC

BIAS

PLL DA

C TX BB FILTER

SYNTH

2.4/5GHzRX RF

2.4/

5GH

zT

X R

F

• Process: 0.18µm CMOS with 3V I/O

• Die Size:6.6 × 6.7 mm2

• Analog Area:13.5 mm2

• Packages: 216-pin BGA or CSP

Performance SummaryParameter 2.4GHz Band 5GHz Band

Transmit EVM at 54Mbps -27.5dB@-3.5dBm -28dB@-4dBm

Receiver Sensitivity for 6Mbpsfor 54Mbps

-94dBm-76dBm

-91dBm-73dBm

Receiver Noise Figure 5.0dB 5.5dB

SoC Power DissipationRX modeTX mode (Pout=-4dBm)

424mW380mW

398mW425mW

RF Transceiver PowerRX (excl. ADC)TX (Pout=-4dBm, excl. DACs)

287mW272mW

267mW310mW

Sleep Power Dissipation < 300µW

Technology Standard 0.18µm CMOS w/ 3V I/O

Die Area (analog area) 44.6 (13.5) sq. mm

Conclusions

• Demonstrated a single-chip IEEE 802.11a/b/g SoC suitable for embedded WLAN

• Receiver sensitivity of -76dBm and -73dBm at 54Mbps for 2.4GHz and 5GHz, respectively

• Fractional-N frequency synthesis allows operation with a range of crystal frequencies

• Power management features reduce sleep and standby current

Acknowledgements

• Support of the Digital Design, Algorithms, System Test, CAD and IT groups at Atheros Communications.