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AN 901: Implementing Analog-to-Digital Converter Dual Link Designwith Intel® Agilex™ FPGA E-TileJESD204C RX IP

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Contents

1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™FPGA E-Tile JESD204C RX IP......................................................................................31.1. ADC to Intel Agilex Dual Link Design Overview.......................................................... 41.2. ADC to Intel Agilex Dual Link Design Implementation Guidelines..................................41.3. Synchronized ADC to Intel Agilex Dual Link............................................................... 6

1.3.1. Design Simulation Guidelines...................................................................... 81.3.2. Design Synthesis Guidelines...................................................................... 27

1.4. Downloading and Operating the Design Example...................................................... 321.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter

Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IP............................... 32

Contents

AN 901: Implementing Analog-to-Digital Converter Dual Link Design withIntel® Agilex™ FPGA E-Tile JESD204C RX IP

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1. Implementing Analog-to-Digital Converter Dual LinkDesign with Intel® Agilex™ FPGA E-Tile JESD204C RX IP

This application note provides guidelines on how to scale up the single link of theJESD204C Intel® FPGA IP design example generated from the Intel Quartus® Primesoftware to handle a dual link system. A single link in JESD204C has one or more highspeed transceiver lanes or channels.

In some JESD204C applications, multiple analog-to-digital converters (ADCs) are usedto sample the analog signals synchronously. Hence, synchronization between multipleconverters in the array is required. In these applications, multiple converters interfacewith a single logic device, such as the Intel Agilex™ FPGA E-tile.

Before implementing the dual link design, you must generate the receiver (RX) single-link design example from the Intel Quartus Prime software. Intel recommends thatyou perform an RTL simulation on this single link design example to confirm thefunctionality matches your expectation before transforming the design example to thedual link design. The guidelines in the following section assume the JESD204Cparameters for each link in the dual link design are identical.

Figure 1. JESD204C Dual LinkFigure shows one dual link. All lanes are aligned.

FPGA

ADC

ADC

1 Link, L Lanes

1 Link, L Lanes

ADC DeviceClock 1

Logic DeviceDevice Clock 2

JESD204CIntel FPGA IP

JESD204CIntel FPGA IP

Related Information

• Serial Interface for Data Converters JEDEC Standard: JESD204CFigure 2 —Scope of original JESD204 and revisions A, B, and C in theJESD204C JEDEC Standard visualizes a dual link system.

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• Design Store: Synchronized ADC-Intel Agilex E-Tile Dual Link ImplementationDesign Example Files

Contains design example files of the synchronized ADC to Intel Agilex dual linkdescribed in the following sections. Refer to the Downloading and Operatingthe Design Example section in this document to download and operate thedesign example.

• JESD204C Intel Agilex FPGA IP Design Example User Guide

1.1. ADC to Intel Agilex Dual Link Design Overview

The design example Platform Designer system and top-level HDL file are designed foreasy implementation of a JESD204C dual link use case. In the top-level HDL file, eachlink in a JESD204C link use case corresponds to an instantiation of a JESD204C IntelFPGA IP and a pattern checker. The dual link design is created by adding multipleJESD204C Intel FPGA IPs and pattern checkers to a single link design example. TheLINK parameter at the top-level HDL generates multiple pattern checkers. You mustduplicate JESD204C Intel FPGA IPs in the Platform Designer and make connections tothe pattern checkers. For a synchronized dual link, AND gates are used to combine thealignment signals.

Figure 2. Platform Designer System of the Single Link Design Example

SPI 3 Wire

Reset Release IP(ninit_done)

Reset Debounce

VCC

PatternChecker

PatternGenerator

j204c_rx_ss Top Level Platform Designer System

ED Control

IOPLL

PIO IN and OUT

SPI

Reset Sequencer

JTAG to AvalonMaster Bridge

JESD204CDuplex PHY

Transceiver ResetController and PLL

JESD204C TX

tx/rx_reconfig_clk

refclk_core

refclk_xcvr

RX Serial Data

Note: 1. The JESD204C IP is part of the Platform Designer system.2. The JESD204C TX FPGA IP is used to represent the ADC in the simulation testbench.

in_sysref sysref_out

SYSREFGenerator

mgmt_clk

global_rst

To Host Computer(JTAG/Platform Designer)

tx/rx_frame_clktx/rx_link_clk

tx/rx_phase

JESD204C RX

JESD204C Intel FPGA IP (Duplex)

j204c_rx_ip Subsystem

(1)

ADC (2)

The j204c_rx_ip subsystem in the design example contains one RX IP to interfacewith one ADC. To interface with multiple synchronized converters, the j204c_rx_ipshould contain multiple IPs.

1.2. ADC to Intel Agilex Dual Link Design ImplementationGuidelines

Figure 3. Design Simulation and Synthesis Implementation Guidelines

Design Simulation Guidelines Design Synthesis Guidelines

Implementing Dual Link Design

Simulation Flow Synthesis Flow

1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-TileJESD204C RX IP

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Before you implement the design in the FPGA, you can simulate the design to verifyfunctionality. You can migrate your simulated design for synthesis, and implement thedesign on the FPGA. Alternatively, you can follow the synthesis flow guidelines tocreate the dual link design for implementation on a FPGA, without performing thesimulation.

Here are the steps required to perform simulation and synthesis:

1. Simulation flow:

a. Generate the single link JESD204C example design using Intel Quartus PrimePro Edition software version 20.1 or later with the Synthesis and Simulationoptions enabled. Ensure that the Multilink mode option is enabled in theJESD204C Configuration tab.

Note: Refer to JESD204C Intel Agilex FPGA IP Design Example User Guide forthe steps to generate the design example.

b. Simulate the design, and confirm that the functionality meets yourexpectations.

The testbench prints the status of the simulation results.

c. Modify the RX Platform Designer system to include the additional JESD204CIntel FPGA IPs needed to form the dual link.

d. Modify the RX top-level module to adjust the reset signal connections and toconnect the additional JESD204C Intel FPGA IPs needed for the patterncheckers.

e. Modify the link partner TX Platform Designer system to include the additionalJESD204C Intel FPGA IPs needed to form the dual link.

f. Modify the link partner TX top-level module to adjust the reset signalconnections and to connect the additional JESD204C Intel FPGA IPs to thepattern generators.

g. Modify the testbench to include additional links.

h. Optionally, you can add signals to the simulation waveform for all links of thedual link design.

i. Update the simulation script.

j. Elaborate and simulate the dual link design.

k. Review the simulation results.

Note: Perform steps 2d to 2f only if you migrate your simulated design forsynthesis and implement the design on the FPGA to interface with the ADC.

2. Synthesis flow:

a. Generate the single link JESD204C example design using the Intel QuartusPrime Pro Edition software version 20.1 or later with the Synthesis andSimulation options enabled. Ensure that the Multilink mode option isenabled in the JESD204C Configuration tab.

b. Modify the RX Platform Designer system to include the JESD204C Intel FPGAIPs needed to form the dual link.

c. Modify the RX top-level module to adjust the reset signals connections and toconnect the JESD204C Intel FPGA IPs needed to the pattern checkers.


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d. Perform pin assignment in the Intel Quartus Prime Pro Edition assignmenteditor.

e. Modify the timing constraint SDC file to include the additional link or links.

f. Compile the design in the Intel Quartus Prime Pro Edition software.

Related Information

JESD204C Intel Agilex FPGA IP Design Example User Guide

1.3. Synchronized ADC to Intel Agilex Dual Link

To synchronize multiple RX IPs within the Intel Agilex device, connect the followingsignals from each IP with an AND gate respectively:

• j204c_rx_dev_lane_align

• j204c_rx_dev_emblock_align

The output of the AND gate connects to the j204c_rx_alldev_lane_align andj204c_rx_alldev_emblock_align ports of each IP. Refer to Figure 4 on page 7for the required connections. The IPs need to be out of reset simultaneously tocomplete the link initialization sequence. Multiple IPs are put into the same JESD204Csubsystem so that the reset of each IP is released by the same reset sequencersimultaneously.

Table 1. IP Ports Connection SummaryTable summarizes the IP ports connection for each subclass in the dual link for multi-device synchronization.

Subclass j204c_rx_alldev_lane_align j204c_rx_alldev_emblock_align Reset Remark

0 ANDed and re-distribute ANDed and re-distribute Simultaneous Refer to Figure 4 on page7

1

For subclass 1, the SYSREF pulse is the timing reference of the entire JESD204Csubsystem. It is important to phase-align the SYSREF pulses to the FPGA andconverters.

Note: For Subclass 0 IPs, connect the j204c_rx_sysref port to ground.


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Figure 4. Dual Link Use Case of the Synchronized ADCs and FPGA

Test PatternChecker (Link 0)

RXJESD204CIP (link 0)

ADC(Link 0)

ADC(Link 1)

Avalon Streaming User Data (Link 0)

Avalon Streaming User Data (Link 1)

One Lane orMultiple Lanes ADC

One Lane orMultiple Lanes ADC

rx_serial_data (link 0)

rx_serial_data (link 1)

Clock Generator

SYSREF for FPGA(Subclass 1 only)

SYSREF for ADC

(Subclass 1Only)

j204c_rx_alldev_lane_align

j204c_rx_dev_lane_align

j204c_rx_dev_lane_align

SYSREF for ADC

(Subclass 1Only)Test Pattern

Checker (Link 1)

Top Level RTL (intel_j204c_ed_rx.sv)

Top Level Platform Designer System j204c_rx_ss.qsys

JESD204C Sub-System j204c_rx_ip.qsys

Command ChannelTest Pattern Checker

(Link 0)

Command ChannelTest Pattern Checker

(Link 1)

j204c_rx_dev_emblock_align

j204c_rx_dev_emblock_align

j204c_rx_alldev_emblock_align

RXJESD204CIP (link 1)

Figure 5. Clock and Reset Scheme of the Synchronized Dual Link

ResetSequencer

Core PLL(IO PLL)

TestPatternChecker(Link 0)

TestPatternChecker(Link 1)

RX/DuplexJESD204CIP (link 0)

RX/DuplexJESD204CIP (link 1)

Global Reset

refclk_core

Core PLLReset

JESD204C Sub-System(j204c_rx_ip.qsys)

Top Level Platform Designer System (j204c_rx_ss.qsys)

Top Level RTL (intel_j204c_ed_rx.sv)

Link/Frame Reset

ED Control

refclk_xcvr

Frame ClockLink ClockPhase Clock

Note: To add JESD204C Intel FPGA IPs for interfacing with more than one ADC, modificationsare needed to the Platform Designer system and top-level HDL of the design example.


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1.3.1. Design Simulation Guidelines

When the JESD204C RX design example is generated, the JESD204C TX FPGA IP isused to represent the ADC in the simulation testbench.

Figure 6. Simulation Testbench Block Diagram

Test PatternGenerator

CommandChannel

Test PatternGenerator

Link 1

Link Partner Simplex TX Subsystem (1)

AvalonStreamingUser Data

AvalonStreamingUser DataLink 0 & 1

Link 0 & 1

Test PatternChecker

CommandChannel

Test PatternChecker

Link 1

Link Partner Simplex RX Subsystem (2)

AvalonStreamingUser Data

AvalonStreamingUser DataLink 0 & 1

Link 0 & 1

Testbench

refclk_xcvr

tx_link_error

refclk_core

mgmt_clk

refclk_xcvr

rx_link_error

data_valid/error

sh_lock/emb_lock

cmd_data_valid/error

mgmt_clk

refclk_core

Notes:1. The simulation model is located at the simulation/models/j204c_tx folder.2. The simulation model is located at the rtl folder.

JESD204CTX IP

Link 0

JESD204CRX IP

Link 0

The steps in the following sections guide you to add RX and TX IPs into the respectiveRX and TX subsystems.

1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADCto Intel Agilex Dual Link

1. Open the Intel Quartus Prime project of the generated design example,intel_j204c_ed_rx.qpf, in the ed/quartus/ folder.

2. Open the top-level system, j204c_rx_ss.qsys, in Platform Designer. TheRX .qsys file is located in the ed/rtl/rx/ folder.

3. In the System View tab, right-click the j204c_rx_ip instance and select Drillinto Subsystem. This opens the j204c_rx_ip Platform Designer subsystem.

4. Right-click the intel_jesd204c component and select Duplicate.

This duplicates the JESD204C Intel FPGA IP. Rename the duplicated IP asintel_jesd204c_1.


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Note: Select No if the Platform Designer prompts the following: Do you want toalso duplicate the IP Variant file on the disk? This isbecause the duplicated JESD204C Intel FPGA IP has the same parametersas the original JESD204C Intel FPGA IP .

5. Double click at the export column to export all the JESD204C Intel FPGA IP portsexcept for the j204c_tx2rx_lbdata port.

6. Move up one level of the hierarchy to j204c_rx_ss; this is the top level of thePlatform Designer system.

7. Connect the duplicated IP port as shown in the following table.

Ports for Duplicated IP Connection

j204c_rx_phy_rst_n rst_seq_1.reset_out0

j204c_pll_refclk refclk_xcvr.out_clk (1)

j204c_reconfig_clk mgmt_clk.out_clk

j204c_reconfig_reset reset_controller_0.reset_out

j204c_reconfig jtag_avmm_bridge.master

j204c_rx_avs_clk mgmt_clk.out_clk

j204c_rx_avs_rst_n rst_seq_1.reset_out0

j204c_rx_avs mm_bridge.m0

j204c_rxlink_clk ed_control.rxlink_clk

j204c_rxframe_clk rxframe_clk.out_clk

8. Change the connection of the j204c_rx_avs_rst_n port of the originalJESD204C IP to rst_seq_1.reset_out0.

Note: You can assert the Avalon® memory-mapped interface reset for the IPcontrol and status register (CSR) at the same time as the PHY reset. Referto the JESD204C TX/RX Reset Sequence figure in the JESD204C Intel FPGAIP User Guide.

9. Export the rest of the ports by clicking on the Double-click to export in theExport column of the System View tab.

10. At the address map, adjust the starting address of j204c_rx_avs andj204c_reconfig interfaces so that there is no conflict with other components orinterfaces. For example, you can set the starting address of theintel_jesd204c_1 IP to 0x000d_0400 as shown in the following table.

(1) You cannot share the same transceiver reference clock pin for transceiver channels located indifferent transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clocksources in Platform Designer and connect them to the transceiver reference clock pins indifferent transceiver tiles.


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Table 2. Synchronized ADC-FPGA Dual Link Address Map for Design Example withSystem Console Control

jtag_avmm_bridge.master mm_bridge.m0

j204c_rx_ip.intel_jesd204c_j204c_rx_avs

N/A 0x000d_0000 – 0x000d_03ff

j204c_rx_ip.intel_jesd204c_1_j204c_rx_avs

N/A 0x000d_0400 – 0x000d_07ff

j204c_rx_ip.intel_jesd204c_j204c_reconfig

0x0200_0000 – 0x021f_ffff (2) N/A

j204c_rx_ip.intel_jesd204c_1_j204c_reconfig

0x0220_0000 – 0x023f_ffff (2) N/A

11. Repeat step 4 on page 8 through step 10 on page 9 for subsequent links in yourdesign. Refer to the following figure for the screenshot of link 1 of the JESD204CIP.

12. Click Generate HDL to generate the design files needed for Intel Quartus Primecompilation.

a. Ensure that you select the HDL language of your choice in the Simulationsection of the Generation window to generate the simulation models.

b. Click Generate and Yes to save and generate the design files needed forsimulation.

(2) The address span of the PHY reconfiguration interface depends on the number of transceiverchannels.


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13. After the HDL generation is completed, select Generate from the menu of thePlatform Designer. Select Show Instantiation Template…, and click Copy.

14. Paste the instantiation template of j204c_rx_ss Platform Designer into a texteditor.

You must update the instantiated Platform Designer ports at the top-level HDL.

15. Click Finish to save your Platform Designer settings, and exit the PlatformDesigner window.

Related Information

JESD204C Intel FPGA IP User Guide

1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to IntelAgilex Dual Link

The generate statement in the Verilog HDL file uses the LINK system parameter as anindex variable to generate the requisite number of instances for the dual link use case.

1. Open the top-level HDL file (intel_j204c_ed_rx.sv) in a text editor.

2. Modify the LINK system parameter to reflect the number of links in your design.

3. Insert the newly exported ports from the j204c_rx_ss Platform Designer systeminstantiation.

4. To make the connections for the Platform Designer ports:

a. For RX link reset and frame reset, distribute the rx_rst[0] wire from thereset sequencer in Platform Designer to the IPs and pattern checkers of thesecond and subsequent links. One way to achieve this is to hard code theindex in the rx_rst[i] wire in the pattern checker and the synchronizer(j204c_pulse_CDC) instantiations generation loop with rx_rst[0]. Refer tothe following figures for the RX reset distribution.

Figure 7. JESD204C RX IP Link Reset


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Figure 8. Pattern Checker for the Frame Reset for the Data Channel and Link Reset forthe Command Channel


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Figure 9. JESD204C RX IP, Data Channel, and Command Channel Pattern Checker ErrorFlag Synchronizer Reset

Figure 10. Sysref Synchronizer Reset

b. Change the dimension of the following wires. This example is shown in VerilogHDL:


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i. wire [LINK-1:0] j204c_rx_dev_lane_align;

ii. wire [LINK-1:0] j204c_rx_dev_emblock_align;

c. Add an index to the following wires at the Platform Designer ports of theJESD204C RX IP. Use index [0] for link 0, index [1] for link 1, and so forth.Example:

i. j204c_rx_dev_lane_align[0]

ii. j204c_rx_dev_emblock_align[0]

d. Connect the j204c_rx_dev_lane_align port of each IP to an AND gate.Distribute the output of the AND gate to thej204c_rx_alldev_lane_align port of each IP.

// Example in Verilogassign j204c_rx_alldev_lane_align = &j204c_rx_dev_lane_align;

e. Connect the j204c_rx_dev_emblock_align port of each IP to an ANDgate. Distribute the output of the AND gate to thej204c_rx_alldev_emblock_align port of each IP.

// Example in Verilogassign j204c_rx_alldev_emblock_align = &j204c_rx_dev_emblock_align;

f. Create the following wires:

i. rx_pma_ready_in_all

ii. rx_xcvr_ready_in_all

g. Connect the rx_pma_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to rx_pma_ready_in_all.

// Example in Verilogassign rx_pma_ready_in_all = &rx_pma_ready_in;

h. Connect the rx_xcvr_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to rx_xcvr_ready_in_all.

// Example in Verilogassign rx_xcvr_ready_in_all = &rx_xcvr_ready_in;

i. Replace the rx_pma_ready_in[0] connection at therst_seq_1_reset2_dsrt_qual_reset2_dsrt_qual port of the PlatformDesigner system with the output of the AND gate of rx_pma_ready_in_all.

j. Replace the rx_xcvr_ready_in[0] connection at therst_seq_1_reset3_dsrt_qual_reset3_dsrt_qual port of the PlatformDesigner system with the output of the AND gate ofrx_xcvr_ready_in_all.

k. For the rest of the ports, increase the index wires from 0 to 1, and usesubsequent numbers for the subsequent links.

Example: The rx_avst_data[1] wire should be connected to link 1 IP.


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5. Connect the j204c_rx_emb_lock output port of each IP to the input of an ANDgate. Connect the output of the AND gate to the emb_lock_out output port ofthe design example. Perform a similar action for the rx_sh_lock port.

// Example in Verilogassign emb_lock_out = &rx_emb_lock;assign sh_lock_out = &rx_sh_lock;

6. For subclass 1 subsystem, comment out or delete the sysref_out port and itsassignment. SYSREF should be sourced from the clock generator, which suppliesthe device clock to the ADC and the FPGA. The fpga_sysref signal from EDControl block is meant for debug purpose only.

// Example in Verilog // output wire sysref_out, // assign sysref_out = fpga_sysref;

7. Save the top-level HDL file changes.

1.3.1.3. Editing TX Simulation Model Platform Designer System for SynchronizedADC to Intel Agilex Dual Link

1. Open the top-level system, j204c_tx_ss.qsys, in Platform Designer.

a. The TX .qsys file is located in the simulation/models/j204c_tx/ folder.

b. To open the .qsys file in Platform Designer, you must have an associatedIntel Quartus Prime project. Copy the intel_j204c_ed_rx.qpf andintel_j204c_ed_rx.qsf files from the ed/quartus/ folder into thesimulation/models/j204c_tx/ folder.

c. Select intel_j204c_ed_rx.qpf, and click Open.

d. When the IP Synchronization Result window opens, click OK to proceed.

2. In the System View tab, right-click the j204c_tx_ip instance and select Drillinto Subsystem. This opens the j204c_tx_ip.qsys Platform Designersubsystem.

3. Right-click the intel_jesd204c component, and select Duplicate to duplicatethe JESD204C Intel FPGA IP. You can rename the duplicated IP asintel_jesd204c_1.

Note: Select No if the Platform Designer prompts Do you want to alsoduplicate the IP Variant file on the disk? This is because theduplicated JESD204C Intel FPGA IP has the same parameters as the originalJESD204C Intel FPGA IP.

Note: The Multilink mode option at the JESD204C Configurations tab does notaffect the number of ports for the JESD204C transmitter. Leave this optionon or off.

4. Export all JESD204C Intel FPGA IP ports except for j204c_tx2rx_lbdata.

5. Move up one level of the hierarchy to j204c_tx_ss, the top level of the PlatformDesigner System.

6. Connect the duplicated IP port as shown in the following table:


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j204c_tx_phy_rst_n rst_seq_0.reset_out1

j204c_pll_refclk refclk_xcvr.out_clk




j204c_txlink_clk ed_control.txlink_clk

j204c_txframe_clk txframe_clk.out_clk

j204c_tx_avs_clk mgmt_clk.out_clk

j204c_tx_avs_rst_n rst_seq_0.reset_out1

j204_tx_avs mm_bridge.m0

7. Change the connection of the j204c_tx_avs_rst_n port of the original JESD204CIP to rst_seq_0.reset_out1.

Note: You can assert the Avalon memory-mapped interface reset for the IP controland status register (CSR) at the same time as the PHY reset. Refer to theJESD204C TX/RX Reset Sequence figure in the JESD204C Intel FPGA IP UserGuide.

8. Export the rest of the ports to the top-level Platform Designer system. To export aport, click Double-click to export in the Export column of the System Viewtab.

9. At the address map, adjust the starting address of the j204c_tx_avs andj204c_reconfig interfaces of the newly added JESD204C Intel FPGA IP code sothat there is no conflict with other components or interfaces. For example, you canset the starting address of intel_jesd204c_1 IP to 0x000c_0400 as shown inthe following table:

Table 3. Synchronized ADC to FPGA Dual Link TX Platform Designer Simulation ModelAddress Map for System Console Control


j204c_tx_ip.intel_jesd204c_j204c_tx_avs

N/A 0x000c_0000 – 0x000c_03ff

j204c_tx_ip.intel_jesd204c_1_j204c_tx_avs

N/A 0x000c_0400 – 0x000c_07ff

j204c_tx_ip.intel_jesd204c_j204c_reconfig

0x0200_0000 – 0x021f_ffff (3) N/A

j204c_tx_ip.intel_jesd204c_1_j204c_reconfig

0x0220_0000 – 0x023f_ffff (3) N/A

10. Repeat step 3 on page 15 through step 9 on page 16 for subsequent links in yourdesign.

11. Click Generate HDL.



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12. Ensure you select the HDL language of your choice in the Simulation section ofthe Generation windows to generate the simulation models.

13. Click Generate and Yes to save and generate the design files needed forsimulation.

14. After the HDL generation is completed, select Generate from the menu, selectShow Instantiation Template…, and click Copy.

15. Paste the instantiation template of the j204c_tx_ss Platform Designer in a texteditor.


16. Click Finish to save your Platform Designer settings and exit the PlatformDesigner window.

Related Information


1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to IntelAgilex Dual Link

The generate statement in the Verilog HDL file uses the LINK system parameter as anindex variable to generate the requisite number of instances for the dual llink usecase.

1. Open the top-level HDL file (intel_j204c_ed_tx.sv) in a text editor.


3. Insert the newly exported ports from the Platform Designer at the PlatformDesigner instantiation.


a. For TX link reset and frame reset, distribute the tx_rst[0] wire from thereset sequencer in Platform Designer to the IPs and pattern generators of thesecond and subsequent links. One way to achieve this is to hard code theindex in the tx_rst[i] wire in the pattern generator and the synchronizer(j204c_pulse_CDC) instantiations generation loop with tx_rst[0].

b. Create the following wires:

i. tx_pma_ready_in_all

ii. tx_xcvr_ready_in_all

c. Connect the tx_pma_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to tx_pma_ready_in_all.

// Example in Verilogassign tx_pma_ready_in_all = &tx_pma_ready_in;

d. Connect the tx_xcvr_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to tx_xcvr_ready_in_all.

// Example in Verilogassign tx_xcvr_ready_in_all = &tx_xcvr_ready_in;

e. Replace the tx_pma_ready_in[0] connection at therst_seq_0_reset3_dsrt_qual_reset3_dsrt_qual port of the PlatformDesigner system with the output of the AND gate of tx_pma_ready_in_all.


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f. Replace the tx_xcvr_ready_in[0] connection at therst_seq_0_reset4_dsrt_qual_reset4_dsrt_qual port of the PlatformDesigner system with the output of the AND gate oftx_xcvr_ready_in_all.

g. For the rest of the ports, increase the index wires from 0 to 1, and usesubsequent numbers for the subsequent links.

Example: tx_avst_data[1] wire should be connected to link 1 IP.


1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex DualLink

The simulation testbench, tb_top.sv, is located in the simulation/models folder.Follow these steps to edit the testbench.

1. Open the testbench (tb_top.sv) in a text editor.

2. Add the LINK parameter at the localparam declaration section. Example:

localparam LINK = 2; // Number of IP core in the dual link design

3. In the instantiation of the TX and RX JESD204C example design modules, includethe LINK parameter. Example:

intel_j204c_ed_rx #( .LINK (LINK), intel_j204c_ed_tx #( .LINK (LINK),

4. Add the TX_REG and RX_REG text macros for each additional link. The additionalIP instance in this example is intel_jesd204c_1 and the text macro isTX_REG_1 and RX_REG_1. Example:

`define TX_REG_1 tb_top.u_intel_j204c_ed_tx.u_j204c_tx_ss.j204c_tx_ip.intel_jesd204c_1.intel_jesd204c.j204c_tx_base_inst.j204c_tx_csr_inst.j204c_tx_regmap_inst`define RX_REG_1 tb_top.u_intel_j204c_ed_rx.u_j204c_rx_ss.j204c_rx_ip.intel_jesd204c_1.intel_jesd204c.j204c_rx_base_inst.j204c_rx_csr_inst.j204c_rx_regmap_inst

5. Comment out or delete the sysref_out port at the instantiation of theintel_j204c_ed_rx and intel_j204c_ed_tx subsystems.

// Example in Verilog //.sysref_out (sysref),

6. Change the dimension and assignment of the following wires and registers:

• reg [LINK-1:0] tx_link_error_reg = {LINK{1’b0}};

• reg [LINK-1:0] rx_link_error_reg = {LINK{1’b0}};

• reg [LINK-1:0] data_error_reg = {LINK{1’b0}};

• reg [LINK-1:0] cmd_data_error_reg = {LINK{1’b0}};

• wire [LINK*L-1:0] tx_serial_data;

• wire [LINK*L-1:0] tx_serial_data_n;

• wire [LINK*L-1:0] rx_serial_data;


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• wire [LINK*L-1:0] rx_serial_data_n;

• wire [LINK-1:0] data_valid;

• wire [LINK-1:0] data_error;

• wire [LINK-1:0] tx_link_error;

• wire [LINK-1:0] rx_link_error;

• wire [LINK-1:0] rx_avst_ready;

• wire [LINK-1:0][(TOTAL_SAMPLE*N)-1:0] rx_avst_data;

• wire [LINK-1:0] cmd_data_valid;

• wire [LINK-1:0] cmd_data_error;

• wire [LINK-1:0][L*18-1:0] cmd_data;

• wire [LINK-1:0] tx_err_sysref_lemc_err;

• wire [LINK-1:0] tx_err_dll_data_invalid_err;

• wire [LINK-1:0] tx_err_frame_data_invalid_err;

• wire [LINK-1:0] tx_err_cmd_invalid_err;

• wire [LINK-1:0] tx_err_tx_ready_err;

• wire [LINK-1:0] tx_err_pcfifo_full_err;

• wire [LINK-1:0] tx_err_tx_gb_underflow_err;

• wire [LINK-1:0] tx_err_tx_gb_overflow_err;

• wire [LINK-1:0] rx_err_sysref_lemc_err;

• wire [LINK-1:0] rx_err_dll_data_ready_err;

• wire [LINK-1:0] rx_err_frame_data_ready_err;

• wire [LINK-1:0] rx_err_cmd_ready_err;

• wire [LINK-1:0] rx_err_cdr_locked_err;

• wire [LINK-1:0] rx_err_pcfifo_full_err;

• wire [LINK-1:0] rx_err_pcfifo_empty_err;

• wire [LINK-1:0] rx_err_lane_deskew_err;

• wire [LINK-1:0] rx_err_invalid_sync_header;

• wire [LINK-1:0] rx_err_invalid_eomb;

• wire [LINK-1:0] rx_err_invalid_eoemb;

• wire [LINK-1:0] rx_err_cmd_par_err;

• wire [LINK-1:0] rx_err_crc_err;

• wire [LINK-1:0] rx_err_rx_gb_underflow_err;

• wire [LINK-1:0] rx_err_rx_gb_overflow_err;

• wire [LINK-1:0] rx_err_sh_unlock_err;

• wire [LINK-1:0] rx_err_emb_unlock_err;


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• wire [LINK-1:0] rx_err_eb_full_err;

• wire [LINK-1:0] rx_err_ecc_corrected_err;

• wire [LINK-1:0] rx_err_ecc_fatal_err;

7. Scale the dimensions of the tx_ready, rx_ready, and rx_avst_readyassignments according to the number of links. Example for LINK = 2:

//Scale the dimension to [number of link-1:0]assign tx_ready = &u_intel_j204c_ed_tx.all_tx_ready[1:0]; assign rx_ready = &u_intel_j204c_ed_rx.all_rx_ready[1:0];assign rx_avst_ready = u_intel_j204c_ed_rx.rx_avst_ready[1:0];

8. Add the LINK parameter to the assignment statements for rx_serial_data andrx_serial_data_n as shown below:

//Internal Loopbackassign rx_serial_data = INTERNAL_SERIAL_LB ? {LINK*L{1'b0}} : tx_serial_data; assign rx_serial_data_n = INTERNAL_SERIAL_LB ? {LINK*L{1'b0}} : tx_serial_data_n;

9. Add an index to each assignment of the TX and RX IP error. Assign the errors foreach link according to the TX and RX IP text macro. Example:

//TX Error Link 0assign tx_err_sysref_lemc_err[0] = `TX_REG.tx_err_sysref_lemc_err;//TX Error Link 1assign tx_err_sysref_lemc_err[1] = `TX_REG_1.tx_err_sysref_lemc_err;//RX Error Link 0assign rx_err_sysref_lemc_err[0] = `RX_REG.rx_err_sysref_lemc_err;//RX Error Link 1assign rx_err_sysref_lemc_err[1] = `RX_REG_1.rx_err_sysref_lemc_err;

10. Create the generation loops for the data and link error signals:

genvar i;

// Pass/Fail Mechanism // generate for (i=0; i

always @ (posedge cmd_data_error or negedge rx_rst_n) begin if (!rx_rst_n) cmd_data_error_reg[i]

if (|rx_link_error_reg===1'b1) begin //OR the error signals $display("JESD204C Rx Core(s): Rx link error(s) found!");end else begin $display("JESD204C Rx Core(s): OK!");end

1.3.1.6. Adding IP Signals to the Simulation Waveform

Note: This is an optional step.

You can add the signals of the IPs to the simulation waveform to monitor the linkinitialization. For the ModelSim-Intel FPGA Edition, include the signals of interest intothe tb_top_waveform.do file in the simulation/mentor folder. Example:

add wave -noupdate -divider {RX LINK 1}

add wave -noupdate /tb_top/u_intel_j204c_ed_rx/u_j204c_rx_ss/j204c_rx_ip/intel_jesd204c_1/j204c_rx_sysref

A sample of the tb_top_waveform.do file is included in the design exampleavailable at the Design Store.

Related Information

Design Store: Synchronized ADC-Intel Agilex E-Tile Dual Link Implementation DesignExample Files

Contains design example files of the synchronized ADC to Intel Agilex dual linkdescribed in the following sections. Refer to the Downloading and Operating theDesign Example section in this document to download and operate the designexample.

1.3.1.7. Updating the Simulation Script

Because of the additional JESD204C Intel FPGA IPs and connection changes in thePlatform Designer system, some of the generated Platform Designer filenames arechanged. This includes filenames of components within the Platform Designerinterconnect. You may encounter the following elaboration error, for example, inModelsim:

# ** Note: (vsim-3812) Design is being optimized...# ** Error: ../../ed/rtl/rx/j204c_rx_ss/sim/j204c_rx_ss.v(569): Module 'j204c_rx_ss_altera_mm_interconnect_191_gpcal4y' is not defined.# ** Error: ../../ed/rtl/rx/j204c_rx_ss/sim/j204c_rx_ss.v(599): Module 'j204c_rx_ss_altera_mm_interconnect_191_5wgszea' is not defined.# ** Error: ../models/j204c_tx/j204c_tx_ss/sim/j204c_tx_ss.v(544): Module 'j204c_tx_ss_altera_mm_interconnect_191_lwybday' is not defined.# ** Error: ../models/j204c_tx/j204c_tx_ss/sim/j204c_tx_ss.v(574): Module 'j204c_tx_ss_altera_mm_interconnect_191_syluiea' is not defined.# Optimization failed# Error loading design# Error: Error loading design# Pausing macro execution# MACRO ./modelsim_sim.tcl PAUSED at line 28


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https://fpgacloud.intel.com/devstore/platform/20.1.0/Pro/an901-implementing-synchronized-adc-agilex-e-tile-multipoint-link-design-with-jesd204c-rx-ip-core/https://fpgacloud.intel.com/devstore/platform/20.1.0/Pro/an901-implementing-synchronized-adc-agilex-e-tile-multipoint-link-design-with-jesd204c-rx-ip-core/mailto:[email protected]?subject=Feedback%20on%20AN%20901:%20Implementing%20Analog-to-Digital%20Converter%20Dual%20Link%20Design%20with%20Intel%20Agilex%20FPGA%20E-Tile%20JESD204C%20RX%20IP%20(AN-901%202020.09.21)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you.

Follow these steps to update the simulation script due to changes in the PlatformDesigner interconnect components:

1. The TCL simulation script for each simulator is located in simulation/setup_scripts/common folder. Open the simulation script of the simulator ofyour choice.

2. Based on the error messages, locate the impacted Platform Designer interconnectcomponent files in ed/rtl/rx/j204c_rx_ss/altera_mm_interconnect_1920/sim and simulation/models/j204c_tx/j204c_tx_ss/altera_mm_interconnect_1920/sim folders.

3. Edit the simulation script to update the random string suffix of the PlatformDesigner interconnect components. Example of altera_mm_interconnect:

• Update j204c_rx_ss_altera_mm_interconnect_1920_h7c7mby.v toj204c_rx_ss_altera_mm_interconnect_1920_loohupi.v

• Update j204c_rx_ss_altera_mm_interconnect_1920_zampnoi.v toj204c_rx_ss_altera_mm_interconnect_1920_hx4knoq.v

• Update j204c_tx_ss_altera_mm_interconnect_1920_toxdddy.v toj204c_tx_ss_altera_mm_interconnect_1920_ry3uqzq.v

• Update j204c_tx_ss_altera_mm_interconnect_1920_6nf5zji.v toj204c_tx_ss_altera_mm_interconnect_1920_yejlffi.v

4. Add entries in the simulation script to resolve all the elaboration errors related tothe interconnect components of both RX and TX Platform Designer systems.Examples of the components include:

• altera_merlin_router

• altera_merlin_burst_adapter

• altera_merlin_demultiplexer

• altera_merlin_multiplexer

• altera_merlin_width_adapter

• altera_merlin_traffic_limiter_altera_avalon_sc_fifo

• altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage

5. Save the simulation script changes.

1.3.1.8. Simulating the Dual Link Design

After modifications to the j204c_rx_ss.qsys, j204c_rx_ip.qsys,intel_j204c_ed_rx.sv, j204c_tx_ss.qsys, j204c_tx_ip.qsys,intel_j204c_ed_tx.sv, tb_top.sv, and _files.tcl, you areready to simulate the dual link design using the simulator of your choice. The followingexample uses the ModelSim-Intel FPGA Edition.

1. Launch the ModelSim-Intel FPGA Edition.

2. From the File menu, select Change Directory.

3. Select simulation/mentor.

4. To run the simulation script, type the following command at the transcript prompt:

do modelsim_sim.tcl


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Note: Depending on your simulator, the simulation may take a few hours tocomplete. For the Modelsim-Intel FPGA Edition, the simulation takes 2 to 3hours.

1.3.1.9. Viewing the Simulation Results

The simulation testbench prints the results at the transcript or terminal where youexecute the simulation script.The following example shows the printout and waveformof the simulation in the ModelSim-Intel FPGA Edition:

If the simulation passes, the transcript section prints TESTBENCH_PASSED: SIMPASSED! as shown in the following figure.

Figure 11. ModelSim-Intel FPGA Edition Simulation Results Transcript

If the simulation fails, the transcript section prints TESTBENCH_FAILED: SIMFAILED! along with the failure reason.

If you want to view the waveform, the following events occur during link initialization.

1. After the /tb_top/ninit_done and global reset are deasserted, the resetsequencer deasserts the resets of the TX and RX transceivers in both Link 0 andLink 1 of the JESD204C Intel FPGA IPs.

2. /tb_top/tx_ready is asserted when the TX transceiver channels of Link 0 and 1are ready.

3. The link reset for TX JESD204C IPs, /tb_top/tx_rst_n, is deasserted when thecore IO PLL is locked and intel_jesd204c/tx_pma_ready andintel_jesd204c/tx_ready are asserted.

4. When TX channels send data to the RX channels, the RX transceiver channelsready signal, /tb_top/rx_ready, is not asserted. The link reset for the RXJESD204C IPs, /tb_top/rx_rst_n, is asserted.


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Figure 12. ModelSim-Intel FPGA Edition Simulation Waveform After Global ResetDeassertion

12

3

4

5. When the RX transceiver channels successfully recover the data and clock, /tb_top/rx_ready is asserted.

6. The link reset for the RX JESD204C IPs, the /tb_top/rx_rst_n, is deassertedwhen the core IO PLL is locked and the intel_jesd204c/rx_pma_ready andintel_jesd204c/rx_ready are asserted.

Figure 13. ModelSim-Intel FPGA Edition Simulation Waveform when RX TransceiverChannels are Ready

56

7. The RX transport layer is out of reset when the /tb_top/rx_rst_n isdeasserted. The RX transport layer asserts the j204c_rx_avst_ready signal tothe JESD204C Intel FPGA IP.

8. The RX JESD204C IPs achieve sync header alignment (j204c_rx_sh_lock isasserted) when 64 consecutive valid sync headers are detected.

9. The RX JESD204C IPs achieve extended multiblock alignment(j204c_rx_emb_lock is asserted) when 4 consecutive valid sequences aredetected. A valid sequence is defined as correct EoEMB and EoMB values for a fullE*32-bit sync transition stream.


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10. j204c_rx_alldev_lane_align is asserted when both RX JESD204C IPsachieve lane alignment.

11. j204c_rx_avst_valid is asserted when the RX transport layer streams userdata to the application layer together with the start-of-multiblock(j204c_rx_somb) and start-of-extended-multiblock (j204c_rx_soemb)markers.

12. The command channel of the RX JESD204C IP outputs the CRC-12 signal in thesync header stream. No CRC error (j204c_rx_crc_err) is detected. No parityerror (j204c_rx_cmd_par_err) is detected at the command channel.

Figure 14. ModelSim-Intel FPGA Edition Simulation Waveform for Successful LinkInitialization

7

89

10

11

11

12

Figure 15. ModelSim-Intel FPGA Edition Simulation Waveform for No Data Error

13

14

15


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13. The pattern checker checks the received sample data from the RX transport layer.No error (/tb_top/data_error) is detected.

14. The pattern checker checks the received sync header from the RX JESD204C IP.No error (/tb_top/cmd_data_error) is detected.

15. No TX and RX link errors or interrupts (/tb_top/tx_link_error and /tb_top/rx_link_error) are being asserted by both TX and RX JESD204C IPs. Thetestbench asserts the test_passed flag.

1.3.2. Design Synthesis Guidelines

1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADCto Intel Agilex Dual Link

1. Open the Intel Quartus Prime project of the generated design example,intel_j204c_ed_rx.qpf, in the ed/quartus/ folder.

2. Open the top-level system, j204c_rx_ss.qsys, in Platform Designer. TheRX .qsys file is located in the ed/rtl/rx/ folder.

3. In the System View tab, right-click the j204c_rx_ip instance, and select Drillinto Subsystem. This opens the j204c_rx_ip Platform Designer subsystem.

4. Right-click the intel_jesd204c component, and select Duplicate.

This duplicates the JESD204C Intel FPGA IP. Rename the duplicated IP asintel_jesd204c_1.

Note: Select No if the Platform Designer prompts the following: Do you want toalso duplicate the IP Variant file on the disk? This isbecause the duplicated JESD204C Intel FPGA IP has the same parametersas the original JESD204C Intel FPGA IP.

5. Export all JESD204C Intel FPGA IP ports except for the j204c_tx2rx_lbdataport.

6. Move up one level of the hierarchy to j204c_rx_ss; this is the top level of thePlatform Designer system.

7. Connect the duplicated IP port as shown in the following table:


j204c_rx_phy_rst_n rst_seq_1.reset_out0

j204c_pll_refclk refclk_xcvr.out_clk (4)




j204c_rx_avs_clk mgmt_clk.out_clk

continued...

(4) You cannot share the same transceiver reference clock pin for transceiver channels located indifferent transceiver tiles. For this case, you should instantiate multiple refclk_xcvr clocksources in Platform Designer and connect them to the transceiver reference clock pins indifferent transceiver tiles.


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j204c_rx_avs_rst_n rst_seq_1.reset_out0

j204c_rx_avs mm_bridge.m0

j204c_rxlink_clk ed_control.rxlink_clk

j204c_rxframe_clk rxframe_clk.out_clk

8. Change the connection of the j204c_rx_avs_rst_n port of the originalJESD204C IP to rst_seq_1.reset_out0.

Note: You can assert the Avalon memory-mapped interface reset for the IP controland status register (CSR) at the same time as the PHY reset. Refer to theJESD204C TX/RX Reset Sequence figure in the JESD204C Intel FPGA IP UserGuide.

9. Export the rest of the ports by clicking on the Double-click to export in theExport column of the System View tab.

10. At the address map, adjust the starting address of the j204c_rx_avs andj204c_reconfig interfaces so that there is no conflict with other components orinterfaces. For example, you can set the starting address of intel_jesd204c_1IP to 0x000d_0400 as shown in the following table:

Table 4. Synchronized ADC-FPGA Dual Link Address Map for Design Example withSystem Console Control


j204c_rx_ip.intel_jesd204c_j204c_rx_avs

N/A 0x000d_0000 – 0x000d_03ff

j204c_rx_ip.intel_jesd204c_1_j204c_rx_avs

N/A 0x000d_0400 – 0x000d_07ff

j204c_rx_ip.intel_jesd204c_j204c_reconfig

0x0200_0000 – 0x021f_ffff (5) N/A

j204c_rx_ip.intel_jesd204c_1_j204c_reconfig

0x0220_0000 – 0x023f_ffff (5) N/A

11. Repeat step 4 on page 27 through step 10 on page 28 for subsequent links in yourdesign.

12. Click Generate HDL to generate the design files needed for Intel Quartus Primecompilation.

a. Click Generate and Yes to save and generate the design files.

13. After the HDL generation is completed, select Generate from the menu. SelectShow Instantiation Template…, and click Copy.

14. Paste the instantiation template of j204c_rx_ss Platform Designer into a texteditor.


15. After the HDL generation is completed, click Finish to save your Platform Designersettings, and exit the Platform Designer window.



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Related Information


1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to IntelAgilex Dual Link

The generate statement in the Verilog HDL file uses the LINK system parameter as anindex variable to generate the requisite number of instances for the dual link use case.

1. Open the top-level HDL file (intel_j204c_ed_rx.sv) in a text editor.


3. Insert the newly exported ports from the Platform Designer at the PlatformDesigner instantiation.


a. For RX link reset and frame reset, distribute the rx_rst[0] wire from thereset sequencer in Platform Designer to the IPs and pattern checkers of thesecond and subsequent links. One way to achieve this is to hard code theindex in the rx_rst[i] wire in the pattern checker and the synchronizer(j204c_pulse_CDC) instantiations generation loop with rx_rst[0].

b. Change the dimension of the following wires. This example is shown in VerilogHDL:

i. wire [LINK-1:0] j204c_rx_dev_lane_align;

ii. wire [LINK-1:0] j204c_rx_dev_emblock_align;

c. Add an index to the following wires at the Platform Designer ports of theJESD204C RX IP. Use index [0] for link 0, index [1] for link 1, and so forth.Example:

i. j204c_rx_dev_lane_align[0]

ii. j204c_rx_dev_emblock_align[0]

d. Connect the j204c_rx_dev_lane_align port of each IP to an AND gate.Distribute the output of the AND gate to thej204c_rx_alldev_lane_align port of each IP.

// Example in Verilogassign j204c_rx_alldev_lane_align = &j204c_rx_dev_lane_align;

e. Connect the j204c_rx_dev_emblock_align port of each IP to an ANDgate. Distribute the output of the AND gate to thej204c_rx_alldev_emblock_align port of each IP.

// Example in Verilogassign j204c_rx_alldev_emblock_align = &j204c_rx_dev_emblock_align;

f. Create the following wires:

i. rx_pma_ready_in_all

ii. rx_xcvr_ready_in_all


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g. Connect the rx_pma_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to rx_pma_ready_in_all.

// Example in Verilogassign rx_pma_ready_in_all = &rx_pma_ready_in;

h. Connect the rx_xcvr_ready_in of each link to the input of an AND gate.Connect the output of the AND gate to rx_xcvr_ready_in_all.

// Example in Verilogassign rx_xcvr_ready_in_all = &rx_xcvr_ready_in;

i. Replace the rx_pma_ready_in[0] connection at therst_seq_1_reset2_dsrt_qual_reset2_dsrt_qual port of the PlatformDesigner system with the output of the AND gate of rx_pma_ready_in_all.

j. Replace the rx_xcvr_ready_in[0] connection at therst_seq_1_reset3_dsrt_qual_reset3_dsrt_qual port of the PlatformDesigner system with the output of the AND gate ofrx_xcvr_ready_in_all.

k. For the rest of the ports, increase the index wires from 0 to 1, and usesubsequent numbers for the subsequent links.

Example: The rx_avst_data[1] wire should be connected to link 1 IP.

5. Connect the j204c_rx_emb_lock output port of each IP to the input of an ANDgate. Connect the output of the AND gate to the emb_lock_out output port ofthe design example. Perform a similar action for the rx_sh_lock port.

// Example in Verilogassign emb_lock_out = &rx_emb_lock;assign sh_lock_out = &rx_sh_lock;

6. For subclass 1 subsystem, comment out or delete the sysref_out port and itsassignment. SYSREF should be sourced from the clock generator, which suppliesthe device clock to the ADC and the FPGA. The fpga_sysref signal from EDControl block is meant for debug purpose only.

// Example in Verilog // output wire sysref_out, // assign sysref_out = fpga_sysref;


8. Ensure that any additional pins that are created from the addition of links (forexample, rx_serial_data pins) have proper pin assignments in the IntelQuartus Prime settings file (intel_j204c_ed_rx.qsf).

9. Because the sysref_out port is commented in the top level HDL, you mustdisable the assignment for this port at the Quartus Prime setting file.

set_instance_assignment -name VIRTUAL_PIN ON -to sysref_out -disable


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1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADCto Intel Agilex Dual Link

Several modifications to the top-level SDC constraint, intel_j204c_ed_rx.sdc, areneeded to ensure that the newly added IPs are fully constrained:

1. In the set_clock_groups constraints, add entries for the newly added IPs.

set_clock_groups -asynchronous -group {mgmt_clk} \-group {ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk} \-group {u_j204c_rx_ss|core_pll|core_pll_clk_1x u_j204c_rx_ss|core_pll|core_pll_clk_2x u_j204c_rx_ss|core_pll|core_pll_refclk } \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch0} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch1} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch2} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch3} \-group {altera_reserved_tck}

set_clock_groups -async -group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch0} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch1} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch2} \-group {u_j204c_rx_ss|j204c_rx_ip||intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch3} \-group {u_j204c_rx_ss|core_pll|core_pll_clk_1x u_j204c_rx_ss|core_pll|core_pll_clk_2x } \-group {mgmt_clk}

is the name for the duplicated copy of theJESD204C Intel FPGA IP that you named in step 4 on page 27.

The following example has the newly added design entities:

-group {u_j204c_rx_ss|j204c_rx_ip|intel_jesd204c_1|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_clkout|ch0} \

-group {u_j204c_rx_ss|j204c_rx_ip|intel_jesd204c_1|intel_jesd204c|j204c_rx_phy_hip_inst|j204c_rx_hip_inst|inst_xcvr|rx_transfer_clk|ch0} \

2. Edit the set_multicycle_path constraint by changing the index of the resetsynchronizer data register from 0 to 1 (in other words, dreg[1]). Change the toplevel Platform Designer system instance name from u_j204c_rx_tx_ss tou_j204c_rx_ss:

set_multicycle_path -setup -from reset_synchronizer|u|dreg[1] -to u_j204c_rx_ss|core_pll|core_pll|tennm_pll~pll_ctrl_reg 2

set_multicycle_path -hold -from reset_synchronizer|u|dreg[1] -to u_j204c_rx_ss|core_pll|core_pll|tennm_pll~pll_ctrl_reg 1

1.3.2.4. Compiling the Design in Intel Quartus Prime Software

After modifying the Platform Designer system, top-level HDL file, Quartus setting file,and top-level SDC constraint file, compile the design with the Intel Quartus Primesoftware. Intel recommends that you perform Analysis and Synthesis and use the RTLViewer to check the correctness of the connections before fully compiling your duallink design.


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1.4. Downloading and Operating the Design Example

The design example has L=4, M=8, and F=4 configurations from the JESD204C IntelFPGA IP preset. This design example is verified using simulation, and no hardwaretesting is performed. The top-level design file is a synthesis design that is migratedfrom the simulation design. The simulation folder contains the simulation design. Thertl folder contains the RX dual link design and the simulation/models/j204c_txfolder contains the link partner TX dual link design.

Follow these steps to download and operate the design example:

1. Download the design example file (.par) from Design Store and restore thedesign using Intel Quartus Prime Pro Edition software version 20.1 and above.

2. In the Intel Quartus Prime Pro Edition software, click File ➤ Open Project toextract the .par design example.

The .par file includes simulation.zip and README.txt files.

1. Extract the files and folders from the simulation.zip file into simulation folder.Place the simulation folder at the directory structure as described in theReadme.txt file.

Note: The directory structure of the design example in the Design Store isdifferent from the directory structure of the design example generated bythe Intel Quartus Prime Pro Edition software. Refer to the README.txt filefor more details about the directory structure.

2. Follow the instructions in the Simulating the Dual Link Design section.

The explanations of the simulation results are presented in the Viewing the SimulationResults section.

Related Information

• Simulating the Dual Link Design on page 23

• Viewing the Simulation Results on page 24

1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-TileJESD204C RX IP

DocumentVersion

Changes

2020.09.21 Initial release.


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AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IPContents1. Implementing Analog-to-Digital Converter Dual Link Design with Intel® Agilex™ FPGA E-Tile JESD204C RX IP1.1. ADC to Intel Agilex Dual Link Design Overview1.2. ADC to Intel Agilex Dual Link Design Implementation Guidelines1.3. Synchronized ADC to Intel Agilex Dual Link1.3.1. Design Simulation Guidelines1.3.1.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex Dual Link1.3.1.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex Dual Link1.3.1.3. Editing TX Simulation Model Platform Designer System for Synchronized ADC to Intel Agilex Dual Link1.3.1.4. Editing TX Simulation Model Top-Level HDL for Synchronized ADC to Intel Agilex Dual Link1.3.1.5. Editing Simulation Testbench for Synchronized ADC to Intel Agilex Dual Link1.3.1.6. Adding IP Signals to the Simulation Waveform1.3.1.7. Updating the Simulation Script1.3.1.8. Simulating the Dual Link Design1.3.1.9. Viewing the Simulation Results

1.3.2. Design Synthesis Guidelines1.3.2.1. Editing Design Example Platform Designer System for Synchronized ADC to Intel Agilex Dual Link1.3.2.2. Editing Design Example Top-Level HDL for Synchronized ADC to Intel Agilex Dual Link1.3.2.3. Editing Design Example Top-Level SDC Constraint for Synchronized ADC to Intel Agilex Dual Link1.3.2.4. Compiling the Design in Intel Quartus Prime Software

1.4. Downloading and Operating the Design Example1.5. Document Revision History for AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Intel Agilex FPGA E-Tile JESD204C RX IP

an 901: implementing analog-to-digital converter dual link ......an 901: implementing...

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