An abnormal PowerPC termination problem in PPC405

1. Abstract

Hello! I am a Software engineer, in the past three years, the Xilinx platform

studio system works fine, and the project is going to finish, but now I encounter

something beyond my knowledge. I spend too much time in this case, and I wish

I can get your help.

2. Environment and Phenomenon

My PPC405 works in XC2VP40 FPGA.

After a normal edit of the PowerPC source file, the PowerPC in my project

suddenly stop one day. I exclude several possibilities by deleting none-relative

codes. In the end, a small project was built which can reveal the problem. It’s

composed by a logic which provides clock, reset, and interrupt signals, and a XPS

system built by Xilinx Platform Studio.

Enviroment:

a. Logic part: clock, reset, and interrupt signals. Clk 40MHz, reset signal first

valid then invalid, interrupt signal faster than 10Khz.

b. The simplified program contains 3 parts as below: main function, called

subfunction and interrupt handling function.

Main function:

while(1)

{

SendToCCam(0x11,0x22);

SendToCCam(0x11,0x22);

SendToCCam(0x11,0x22);

SendToCCam(0x11,0x22);

SendToCCam(0x11,0x22);

}

return 0;

}

Called subfunction:

void SendToCCam(Xuint8 data,Xuint8 data2)

{

}

Interrupt handling function

void Ext_Exception_Handler (void)

{

}

The main function include “while (1)”, which should run all the time. A test

function “void SendToCCam(Xuint8 data, Xuint8 data2) {}” was

continuously called in while (1). The test function content was Void.

c. The interrupt function content was Void too.

d. The program termination occurred only when an external interrupt

happened and the interrupt handling function was called.

e. The plb BUS was not used. All code and data sectors distributed in OCM.

f. The project was attached.

Phenomenon

The CPU suddenly terminated when the interrupt happened (not every time

but frequently). The phenomenon below occurred when CPU terminated:

a. Read write reorder

The SendToCCam function was assembled to:- 0xfffe2294 <SendToCCam>: stwu r1,-24(r1)- 0xfffe2298 <SendToCCam+4>: stw r31,20(r1)- 0xfffe229c <SendToCCam+8>: mr r31,r1- 0xfffe22a0 <SendToCCam+12>: mr r0,r3- 0xfffe22a4 <SendToCCam+16>: mr r9,r4- 0xfffe22a8 <SendToCCam+20>: stb r0,8(r31) //step1 write- 0xfffe22ac <SendToCCam+24>: stb r9,9(r31) //step2 write

----------------external interrupt happens----------------------------------------------------------Cpu abnormal termination------------------------------------------ 0xfffe22b0 <SendToCCam+28>: lwz r11,0(r1) //step3 read- 0xfffe22b4 <SendToCCam+32>: lwz r31,-4(r11) //step4 read- 0xfffe22b8 <SendToCCam+36>: mr r1,r11

- 0xfffe22bc <SendToCCam+40>: blr

Usually, these 4 steps display as: step1 ->step3->step2->step4, with a sequence

which was reordered for optimization. When abnormal termination happens, the

order was reset, displayed as: step1->step2, the step3 and step4 was invisible.

Note: For signal bram_wen_a, two write pulses continuously happened before the trigger time. (In normal time, it

happens with write-read-write-read)

Normal write and read sequence (For comparison)

b. The Plb and OCM bus disused

The PLB bus was not used at all, but several read pulses was found in Plb Bus

in the very moment when CPU terminated. And the address in the plb bus

match the address OCM missed. So I can say that the CPU mistaken the bus

cause this problem.

Note: See signal plbdcuabus and plbdcurequest, the plb bus was not used, but several signals

happen when CPU abnormal termination

3. Experience

a) Effective ways to eliminate the problem (But I have to

know how to make sure it would not occur forever).

i. Use PowerPC internal timer interrupt instead of my

interrupt from logic (external).

ii. Change the function SendToCCam. A simple way was

to add one “nop” instruction to the function (which

was empty originally). Then everything was Ok.

iii. Change SendToCCam: add

“XExc_mDisableExceptions(XEXC_NON_CRITICAL)”

in the beginning ,

“XExc_mEnableExceptions(XEXC_NON_CRITICAL)”

in the end . Maybe same reason as above.

iv. Change SendToCCam parameters to 32bits (change to

16bits was useless).

v. Add NOP between calling SendToCCam in while (1).

vi. Close external interrupt (of course…）vii. Change isocm and dsocm frequence to 20MHz, while

PowerPC frequency kept in 40MHz. (All the three are

40Mhz originally)

b) Excluded possibilities

i. Cache. Cache was not enabled at all.

ii. Stack/Heap breakdown. Stack/heap was distributed in

the on chip memory (OCM). I analyzed the interface

of the on chip memory, and nothing was wrong

before this abnormal termination.

iii. MMU module. This module was disabled.

iv. Related General-Purpose Registers breakdown. I

analyzed the chipscope signals and the assembled

code, and I could see that the related General

Purpose Registers : r1…r32 were all right before this

abnormal termination.

v. PLB bus not initialized. Some arguments were

allocated in PLB and initialized before while(1)

function, the problem did not disappear.

vi. Interruption too frequent has been excluded.

4. Discussion

After many experiments, I prefer to say I encounter a CPU

defect. But I cannot find any precedent case on the web, so

maybe there was still something wrong somewhere.

5. Other Settings

a) Compile option / Optimization Level choose “NO

Optimization”

b) External interruption used EICC405EXTINPUTIRQ pin in

PowerPC. EIC (external interrupt controller) was not

used, and interrupt was level sensitive.

c) Several relevant materials are provided under my case

uc_8i_8d_1ppc_vhdl.rar which is my testing project.

Build Sequence.docx is how I build the XPS project . xmd

error record.docx is the XMD debug error information.

6. Conclusion

Due to team desire, I need to know the reason about this

PLB BUS disuse error, to make sure it wouldn’t happene

again, or the safe way to revive from this error. Any

suggestion will be useful! Thank you very much for your

time!

7. Keywords

PowerPC, Xc2Vp40, ppc405, ocm reorder, Plb and OCM

bus disused.