an alternative scheme of fom bit mux with pre-interleave

HUAWEI TECHNOLOGIES CO., LTD. IEEE 802.3bs 400 GbE Task Force

An Alternative Scheme of FOM Bit Mux

with Pre-interleave

Tongtong Wang, Wenbin Yang, Xinyuan Wang

HUAWEI TECHNOLOGIES CO., LTD. IEEE 802.3bs 400GbE Task Force

Background

PMA options as in “gustlin_3bs_04_0714” are:

• Bit Muxing, used in 802.3ba

• FEC Orthogonal Multiplexing

• Block muxing

• There might be a complex line encoding that has a unique multiplexing

method

In this presentation, we provide an optimized choice of FEC Orthogonal

Multiplexing by pre-interleaving to relax the constraints on layout

implementation and support any lane to anywhere feature.

http://www.ieee802.org/3/bs/public/14_07/gustlin_3bs_04_0714.pdf


Brief Introduction of FOM Bit Mux

FEC Orthogonal Multiplexing is a general approach to help FEC

performance, it is mature technology and already deployed to face correlate

error applications.

From previous analysis, we can see the improvement of coding gain by FOM

symbol mux and FOM bit mux against burst errors.*

Some concerns raised about FOM for its constraints on layout of CDAUI as

stated in “wang_400_01a_0114”, although we think implementation with this

restriction is feasible.

Can we have tradeoff between flexibility and performance if any FEC lane to

anywhere architecture is preferable?

FOM symbol mux vs. NonFOM symbol mux FOM bit mux vs. NonFOM bit mux

*refer to anslow_3bs_02_0714

http://www.ieee802.org/3/400GSG/public/14_01/wang_400_01a_0114.pdf

http://www.ieee802.org/3/bs/public/14_07/anslow_3bs_02_0714.pdf


Optimize FOM Bit Mux with Pre-interleave

PMD

MAC/RS

400G PCS

The same color

lanes from sub-

FECs distribute to

different Mux/Demux

group.

Medium

MDI

2nd

stage PMA[16:4/8]

or PMA[8:4] in module

1st stage

PMA[16:16] in PCS

Optical Module

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes from different sub-FEC

Bit muxBit mux Bit muxBit mux Bit mux Bit muxBit mux Bit mux

PMD

MAC/RS

400G PCS

Pre-interleave between different

FEC lanes

Each electrical lane

is multiplexed from

all 4 sub-FECs.

Medium

MDI

2nd

stage PMA[16:4/8]


1st stage

PMA[16:16] in Host

Optical Module

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes


PMA

Interleave on symbol/bit

from different FEC lanes

to get data pattern on

Electrical Lanes

Does Pre-interleave

require additional logic?

00.0

40.0

80.0

120.0

00.9

40.9

80.9

120.9

01.0

41.0

81.0

121.0

FEC0

&

FEC lanes

[3:0]

01.9

41.9

81.9

121.9

02.0

42.0

82.0

122.0

02.9

42.9

82.9

122.9

03.0

43.0

83.0

123.0

03.9

43.9

83.9

123.9

00.0

40.0

80.0

120.0

00.9

40.9

80.9

120.9

01.0

41.0

81.0

121.0

FEC1

&

FEC lanes

[7:4]

01.9

41.9

81.9

121.9

02.0

42.0

82.0

122.0

02.9

42.9

82.9

122.9

03.0

43.0

83.0

123.0

03.9

43.9

83.9

123.9

00.0

40.0

80.0

120.0

00.9

40.9

80.9

120.9

01.0

41.0

81.0

121.0

FEC2

&

FEC lanes

[11:8]

01.9

41.9

81.9

121.9

02.0

42.0

82.0

122.0

02.9

42.9

82.9

122.9

03.0

43.0

83.0

123.0

03.9

43.9

83.9

123.9

00.0

40.0

80.0

120.0

00.9

40.9

80.9

120.9

01.0

41.0

81.0

121.0

FEC3

&

FEC lanes

[15:12]

01.9

41.9

81.9

121.9

02.0

42.0

82.0

122.0

02.9

42.9

82.9

122.9

03.0

43.0

83.0

123.0

03.9

43.9

83.9

123.9

Electrical

Lanes

[3:0]

00.0

01.0

02.0

03.0

00.1

01.1

02.1

03.1

00.0

01.0

02.0

03.0

00.9

01.9

02.9

03.9

00.0

01.0

02.0

03.0

00.0

01.0

02.0

03.0

40.0

41.0

42.0

43.0

40.1

41.1

42.1

43.1

40.0

41.0

42.0

43.0

40.9

41.9

42.9

43.9

40.0

41.0

42.0

43.0

40.0

41.0

42.0

43.0

80.0

81.0

82.0

83.0

80.1

81.1

82.1

83.1

80.0

81.0

82.0

83.0

80.9

81.9

82.9

83.9

80.0

81.0

82.0

83.0

80.0

81.0

82.0

83.0

120.0

121.0

122.0

123.0

120.1

121.1

122.1

123.1

120.0

121.0

122.0

123.0

120.9

121.9

122.9

123.9

120.0

121.0

122.0

123.0

120.0

121.0

122.0

123.0

00.1

01.1

02.1

03.1

40.1

41.1

42.1

43.1

80.1

81.1

82.1

83.1

120.1

121.1

122.1

123.1

00.1

01.1

02.1

03.1

40.1

41.1

42.1

43.1

80.1

81.1

82.1

83.1

120.1

121.1

122.1

123.1

00.1

01.1

02.1

03.1

40.1

41.1

42.1

43.1

80.1

81.1

82.1

83.1

120.1

121.1

122.1

123.1

00.9

01.9

02.9

03.9

40.9

41.9

42.9

43.9

80.9

81.9

82.9

83.9

120.9

121.9

122.9

123.9

Electrical

Lanes

[7:4]

Electrical

Lanes

[11:8]

Electrical

Lanes

[15:12]

Pre-interleave


Hardware Implementation of Pre-interleave

Take TX logic for example,

each FEC encoder output

parallel data bus according to

100Gbps throughput.

It is just different logic place

and route option inside host

ASIC to feature

One FEC Lane to one

Serdes interface Or,

Symbols from multiple

FEC Lanes to one Serdes

interface

No multiplexers involved

No additional latency cost

No additional area cost

RX logic procedure is similar

and operable on parallel logic.

sym

sym

sym

sym

Serders interface 0

sym

Serders interface 4

Serders interface 8

Serders interface 12

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

sym

symsymsymsym

RS

FE

C1

En

co

de

rR

SF

EC

2 E

nc

od

er

RS

FE

C3

En

co

de

rR

SF

EC

4 E

nc

od

er

16x10b

Serders interface 0

Serders interface 4

Serders interface 8

Serders interface 12

symsym

sym

sym

sym

sym

sym

symsym

sym

sym

sym

sym

sym

symsym

sym

sym

sym

sym

sym

FEC symbol lanes FOM Bit Mux with Pre-interleave

Only for logic illustration, not

necessarily a physical register

Ele

ctica

l L

an

es 0

~1

5

RS

FE

C1

En

co

de

rR

SF

EC

2 E

nc

od

er

RS

FE

C3

En

co

de

rR

SF

EC

4 E

nc

od

er

Ele

ctica

l L

an

es 0

~1

516x10b

16x10b

16x10b

16x10b

16x10b

16x10b

16x10b

10b


RX Side: Alignment and Reorder Before De-interleave

Use alignment and reorder mechanism in RX side across all lanes as in 100GE.

PMD

MAC/RS

400G PCS

Each Output Lanes is bit mux by FEC Lanes

from different Sub-FECs

Electrical lanes[15:0] is

un-restrict route to any

bit mux/Demux group

Medium

MDI

2nd

stage PMA[16:4/8]


1st stage

PMA[16:16] in Host

Optical Module

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

Each bit mux block based on 4/2 electrical lanes


Pre-interleave on

all FEC Lanes and

Output Electrical

Lanes

12

3

45

67

89

1011

1213

1415

0

FEC Lanes [15:0]

With different AM ID

PMA0

18

15

45

29

133

147

126

1011

MAC/RS

400G PCS

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

802.3bj

FEC

610

1211

42

9 5

147

133

158

10

Bit

Demux

Bit

Demux

Bit

Demux

Bit

DemuxOptical

Module

PMD

MediumMDI

PMAAlignment Lock & Deskew

Lane0Lane1

Lane2Lane3

Lane4Lane5

Lane6Lane7

Lane8Lane9Lane10

Lane11

Lane12Lane13

Lane14Lane15

Reorder

Each Input Lanes is bit De-mux to recovery FEC

Lanes By de-interleave


Example: 2:1 Bit Mux with CDAUI-16 interface

Two 50Gbps Optical Link

02.0

02.0

02.0

02.1

02.1

03.0

03.0

03.0

03.0

03.1

03.1

Bit Mux

2:1

02.001.0 03.000.0

Egress PCS/PMA

Elane 0Elane1 Elane2 Elane3

4X25Gbps Electrical lanes

after pre-interleave

TX:CDAUI-16

02.1

02.001.0 03.000.002.001.0 03.000.002.001.0 03.000.002.101.1 03.100.102.101.1 03.100.1

Bit mux group pattern depends

on different skew

and trace implementation

01.0

01.0

01.1

01.1

00.0

00.0

00.0

00.1

00.0

01.0

01.0

00.1

00.000.000.000.000.100.1

01.001.001.001.001.101.1

02.002.002.002.002.102.1

03.003.003.003.003.103.1

Data stream on16 electrical lanes is bit interleaved

from different Sub-FECs by Pre-interleaving.

Use 16 electrical lanes on CDAUI-16 and multiplex

to 50G optical lanes.

As bit pattern on each electrical lanes is from 4

different sub-FECs, any two electrical lanes can bit-

mux together. NO layout restriction on CDAUI

interface.

Use AM Lock/Alignment and Reorder on RX side to

restore all FEC lanes before de-interleave;

The worst case of FEC performance is showed in

RED block in right diagram, when bits from same

FEC are aligned.


Error Symbol Number and Probability

- Worse case FEC Orthogonal Bit Mux 2:1 with Pre-interleave

A bl bit burst corrupts x bits on each symbol lane.

This x corrupted bits cause erroneous symbols as in following equation.

Total number of erroneous symbol is the sum of error symbols from 2 lanes.

𝑥 = 𝑐𝑒𝑖𝑙 𝑏𝑙%8

8 + 𝑓𝑙𝑜𝑜𝑟(

𝑏𝑙

8)

1

2 1

% 1( ) 1;

( ); 1

x mxceil of prob

m mError Symbol Numberx

ceil of prob probm

1 2 1 * 2;lane lane lane laneError Symbol Number error_number error_number of prob Prob Prob

Burst Error

Adjacent bits from the perspective of one FEC codeword

Pre-interleaved

Electrical Lanes


Comparison of Error Symbol Number and Probability

Number of erroneous symbols caused by burst errors for different PMA muxing

methods are listed.

Pre-interleaving method has better resistance of burst errors than NonFOM

bitmux(random muxing), but worse than FOM bitmux.

The advantage of Pre-interleaving method is supporting any lane to anywhere.

Table 1: Non FOM bitmux (worst case) Table 2: PreInterleave bitmux(worst case) Table 3: FOM bitmux(no worst case)

Burst Length

(bits )

E rroneous

symbols

Probability

2-8 2 100%

3 10%

2 90%

4 1%

3 18%

2 81%

4 2%

3 26%

2 72%

4 4%

3 32%

2 64%

9

10-16

17

18-24

Burst Length

(bits )

E rroneous

symbols

Probability

2 2 100%

3 10%

2 90%

4 1%

3 18%

2 81%

4 6%

3 38%

2 56%

4 4%

3 32%

2 64%

3

6

4

5

Burst Length

(bits)

Erroneous

symbols

Probability

2 1 100%

2 5%

1 95%

2 10%

1 90%

2 15%

1 85%

2 20%

1 80%

5

6

3

4


FEC performance of FOM 2:1 Bit Mux

with Pre-interleave

FOM bit mux with Pre-interleave require ~0.3dB/0.25db CG Penalty

compare to 802.3bj KR4/KP4 FEC in burst error application


Summary

Pre-interleaving gives another way to do FOM bit mux. It can

support any lane to anywhere routing with compromised coding

gain.

We have tradeoff between FEC performance and flexibility for

FOM bit mux.

For BER objective 1e-13

Gray coding in PAM4 could limit correlated error to one bit per PAM4

symbol and help to improve FEC performance in bit mux. We will

investigate it in the future.

Any to any conncetion

Coding Gain BERin Coding Gain BERin

Random Errors 5.4 4.00E-05 6.64 3.00E-04 Yes

1:2 FOM symbol mux 5.4 4.00E-05 6.64 3.00E-04 No, Partial lane order required

1:2 FOM bit mux 5.3 1.90E-05 6.34 2.00E-04 No, Partial lane order required

1:2 NON FOM symbol mux 4.7 1.40E-05 6.26 2.40E-04 Yes, as .bj

1:2 FOM bit mux with Pre-interleave 4.4 5.00E-06 6.02 1.20E-04 Yes

1:2 NON FOM bit Mux 3 3.50E-07 5.57 5.50E-05 Yes

RS(528,514) RS(544,514)

Thank you

HUAWEI TECHNOLOGIES CO., LTD.

an alternative scheme of fom bit mux with pre-interleave

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