AN ATPG FOR LOW POWER VLSI DESIGN USING VARIABLE

LENGTH RINGCOUNTER & LFSR

R.Dhanagopal,ECE,Jayaram College of Engg & Tech

A.Kavitha ECE,Jayaram College of Engg & Tech

Trichy,India e.mail:dhangopal.ram@gmail.com

Trichy,India e.mail:mani_vasakaa@yahoo.co.in

Abstract- A new built-in self-test (BIST) test pattern

generator (TPG) for low power testing is presented in this paper. The principle of the proposed approach is to reconfigure the CUT’s partial-acting-inputs into a short ring counter (RC), and keep the CUT’s partial-freezing-inputs unchanged during testing. Experimental results based on ISCAS’85 and ISCAS’89 benchmark circuits show that 17% reductions in the test data storage, 43% reductions in the number of test pattern, 30% reductions in the average power, 19% reductions in the average power and 46% reductions in the total power consumption are attained during testing with a small size decoding logic.

I. DESIGN FOR TESTABILITY

Design for Testability (DFT) is one of the critical requirements in a design - additional test logic is added to detect any manufacturing defects such as opens/shorts on a silicon die. A chip or a die can be tested at various levels (at wafer level, package level, board level, system level or in the field). By detecting the manufacturing defect beforehand the manufacturing costs can be lowered.

Fig a

DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.

II. BUILD IN SELF TEST

Fig b

Built-in Self-Test (BIST) is a design-for-test (DFT) technique in which testing is achieved through built-in hardware features. The steps in a typical BIST approach are:

(1) On-chip test pattern generation

(2) Application of patterns to the circuit under test (CUT)

(3) Analysis of CUT responses via on-chip output response analyzer (ORA)

(4) Making decision whether chip is faulty or not.

Fig c

Efficient TPG design is related to the step (1) and it is an important subject in BIST. Generation of test vector sequences with high fault coverage in minimal hardware size and testing time is the main objective .In recent years, power consumption during test became an important issue in test manufacturing

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because high circuit activity rate during test generation and/or high fan-out of BIST components may result in passing the package power consumption limits which in turn may risk the health of the test. It has been reported in that power consumption of VLSI during test application can be as high as 200% of that in normal mode. Therefore, reducing power consumption in test mode is becoming an important objective in circuit design. In it was pointed out that statistically, low activity production at the primary inputs of the CUT results in reduction at CUT’S power consumption. Based on this observation, many approaches using TPG design. A low power TPG combining an original LFSR and a twisting-ring counter (TRC) has been proposed. A new low power BIST methodology by altering the structure of LFSR has been proposed. In this Project, we propose a low power deterministic on chip TPG based on a variable-length RC. In the proposed scheme, the multiple seeds are stored in ROM, which are used to skip the non-detecting vectors. For each seed, the inputs of CUT are divided into two groups (partial-acting inputs and partial-freezing-inputs) according to the pre computed test subset. During testing, the partial-freezing inputs are frozen, and keep their values unchanged; and the partial-acting-inputs are reconfigured into a short RC. The input-division technique is based on the observation that identical sequences often appear in many test patterns that are applied to CUT. In order to efficiently divide the inputs, an algorithm based on cluster analysis is proposed.

III. MOTIVATION EXAMPLE

Fig d

In this section, we’d like to illustrate the basic idea of input-division technique through a simple example. The circuit diagram of this example is shown in Fig .d. It is composed of a 3-input AND gate and a 2-input OR gate with their outputs AND ed together. As shown in Table 1 the size of the collapsed fault list is 18. Test vectors for each fault are listed under left column and they, as a whole, constitute the complete test set for the circuit. In order to detect the stuck-at faults a/0, a/1, b/0, b/1, c/0, c/1, f/0and f/1, g needs to be set to 1 to propagate the faulty values to the output, which requires that the primary inputs “de” be set to “00”. Thus the sequence

“00” appears at the primary inputs “de” in the four test patterns to detect the above stuck-at faults. In order to generate the above six test patterns during testing, we can make the partial-freezing inputs (de) keep their values (00) unchanged, and configure the other inputs (partial-acting-inputs) into a TPG. Based on this observation, we extract a number of partial-freezing inputs from each deterministic test subset in which all test patterns contain the same more-frequently-occurring sequences. During testing, the partial-freezing-inputs keep their values (more-frequently-occurring sequences) unchanged, and the partial-acting-inputs are reconfigured into a RC. In this way, the low activity test patterns can not only be generated by a variable-length RC, but also guarantee high fault coverage (FC), short test application time, and few test data storage.

IV. PROPOSED APPROACH

A. Uniform cluster analysis

Complete test set and collapsed fault list (Table 1given below)

Table 2

complete test set fault list

1 11000 a sat 1,g sat 1

2 10100 b sat 1

3 11000 c sat 1

4 11100 f sat 0

5 0xx10 d sat 0

6 0xx01 c sat 0

cluster Max. Num.

Associated index set

1 3 2,3,4

2 5 1,3,4,5,6

3 5 1,2,4,5,6

4 5 1,2,3,4,6

5 5 1,2,3,4,5

b

c

a

f

g

d

e

h

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Table 3

Table 4

Fig. e Partial freezing input: C3, C4, C5.

Cluster analysis is used for numerical classification in many fields. We use a uniform clustering algorithm based on BDD for the inputs grouping. The test set is first represented as a graph, to which the proposed algorithm is applied. In the graph, each node denotes a column of the test set. The basic idea is to first view each node in the graph as a cluster, then continuously merge pairs of similar clusters until a predefined threshold is reached. This

threshold can be either the number of the vectors which contain the same bit- sequence, referred to as MinVectorNum. The details of the grouping algorithm are described in above Fig. e.

B. Architecture

Twisting-ring counter (TRC) and ring counter (RC) are commonly used as deterministic BIST TPG, because it can build with the simple and uniform BIST control logic. Suppose that if all inputs of the CUT are configured into a TRC/RC, it will subsequently cause more transitions. Fortunately, we discover that the identical sequences often appear in many test patterns that are applied to CUT. Based on the observation, a variable-length RC BIST TPG is proposed in this paper.

The bypassing and Freezable scan flip-flop Fig. f

In this proposed scheme, all inputs are divided into two groups. One part is the partial-freezing inputs, and the other part is the partial-acting-inputs. In order to implement the proposed scheme, we improve the conventional scan flip-flop (see Fig. f). When sel=0, the improved scan flip-flop is frozen, and its output is connected to input si. When sel=1, it works as a conventional scan flip-flop. Based on the improved scan flip-flop, the proposed BIST TPG is shown in Fig. g. For each seed, there are two stages of the test session. In the first stage of the test session, the selecting signals sel0 to seln are firstly set to 1s, and an n-bit seed is then loaded into the input scan registers for n clock cycles.

cluster Max. Num. Associated index set

5,4,1 3 2,3,4

5,4,2 3 1,3,4

5,4,3 3 1,2,4

cluster Max. Num.

Associated index set

5,1 3 2,3,4

5,2 4 1,3,4,5

5,3 4 1,2,4,5

5,4 4 1,2,3,4

sel mode

0 bypassing & freezing

1 scan

C3

C5

C4

5/0

4/0

3/0

1/1

1/1

1/1

x

x

si

clk

sel

q

clk

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At this point, the BIST TPG goes into the second stage of the test session. In the second stage of the test session, the selecting signal sel0 and these

selecting signals which are connected to the freezing input registers (partial freezing- inputs) are set to 0s. At the same time, these selecting signals which are connected to the acting input registers (partial-acting-inputs) are set to 1s. In this way, all acting input registers are reconfigured into a RC whose length is the number of the acting input registers (m). The RC then generates m test vectors for m clock cycles.

SEEDROM

The proposed BIST TPG Fig. g

An example of merging compatible sel signals

In order to implement the proposed BIST TPG, a decoding logic which is utilized to generate the selecting signals sel0 to seln is required. If each scan cell requires a dedicated sel signal from the decoding logic, the size of decoding logic and routing overhead can make the proposed scheme impractical. Fortunately, we find out there are many compatible sel signals. If all compatible sel signals are merged, the routing overhead and the size of decoding logic can be reduced. An example of merging compatible sel signals is shown in Fig. h. The architecture of the decoding logic is implemented by synthesizing with the design compiler of Synopsis.

V. RESULT ANALYSIS

a) RTL VIEW OF CUTTING RING

sel1 sel2 sel3 sel4 sel5 sel6

1st Seed'

0 1 1 0 1 1

2nd Seed'

0 0 0 1 1 1

3rd Seed'

1 0 1 0 0 0

4th Seed'

0 0 1 0 1 1

5th Seed'

0 0 0 1 1 1

F6

Decoding logic

F1 F2 F3 F4 F5

sel1 sel2

sel3

sel4 sel5 sel6

RC

F1 F2 F3 Fn1 Fn

LOAD COUNTER

DECODING LOGIC

CUT

…

sel1

selni

sel2 sel3

seln

sel0

01

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b)RTL VIEW OF LFSR COUNT

c)POWER ANALYSIS

VI. CONCLUSION

A BIST TPG which can highly reduce power consumption during test application is proposed. The power consumption reduction is achieved by furthest freezing some inputs of the CUT. The proposed 2PRC-TPG consists of a variable-length RC and some control logic. For each seed, the inputs of CUT are divided into two groups (partial acting- inputs and partial-freezing-inputs). During testing, the partial-acting-inputs are reconfigured into a short RC, and the partial-freezing-inputs are frozen, and keep their values unchanged. Experimental results show that the proposed BIST scheme based on the 2PRC-TPG can efficiently reduce the data storage, test time, the peak power and the total power consumption during testing with a small size decoding logic. Moreover, these results are obtained with no loss of stuck-at fault coverage (FC).

REFERENCES:

1. Steininger, A., “Testing and hit-In Self-Test -A Survey,’’Journal of Systems Architecture, Vol 46, 2000, pp. 721-747.

2. Zorian, Y., “A Distributed BIST Control Scheme for Complex VLSI Devices,” IEEE VLSI Test Symposium, pp. 4-9, 1993.

3. He Ronghui, Li Xiaowei, Gong Yunzhan, “A Low Power BIST TPG Design,” Proc. IEEE 5th

International ASIC Conference, pp. 1136-1139, 2003.Generator Design IEE Proceedings- Circuits, Devices and System, 145, No: 3, pp155-161, 1998.

5. Rui Li, Chen Hu, Jun Yang, Zhe Zhang, Yonghua Shi and Longxing Shi, “A new low power BIST methodology by Altering the structure of linear feedback shift registers,” Proc.IEE International Conference on ASIC, 2001.

6. B. Zhou, Y.-Z Ye, and Y.-S Wang, “Simultaneous reduction in test data volume and test time for TRC-reseeding,” Proc. GLSVLSI. pp. 49-54, 2007.

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