An Implementation of Electronic Shopping Cart

Transaction and Display System Using Wireless

Technology

ABSTRACT:

RFID generally encompasses any wireless (or partially wireless)

communication that allows for remote retrieval of information associated with a

particular commodity, product, component, or other item. In RFID

environments, each suitable item is tagged with an RFID tag that includes and

(actively or passively) transmits one or more pieces of information including,

for example, a unique identifier and such. These pieces of information are

requested or retrieved by an RFID reader. Typical RFID readers are either small

handheld devices that operate in a limited RFID space or are stationary devices

located at, for example, doors, gates, and other non-mobile or fixed sites. The

handheld RFID reader generally requires the operator to be within five feet to

query the desired RFID tags. Some stationary or fixed mount devices offer

relatively greater distance communications, but are also usually larger than the

handheld devices. Moreover, the RFID often must be manually docked or

interfaced with a port such that the collected RFID information can be

processed. In many circumstances, RFID technology allows the two devices

(the tag and reader) to communicate with one another while not maintaining a

line-of-sight in various weather conditions.

ABOUT OUR PROJECT:

Our project An Implementation of Electronic Shopping Cart

Transaction and Display System Using Wireless Technology, aims at

providing the convenince to the customer and to reduce the time taken while

shopping. Here we made use of EMBEDDED SYSTEM in developing a

module, Shoppers can be guided electronically to find desired products that are

tagged with RFID chips and whose locations are tracked by RFID readers in the

store. Smart shopping carts with electronic displays, in communication with a

retail computer system, can display a map associated with a shopping list

downloaded by a shopper to identify a route to obtain the desired items. The

smart cart, also equipped with RFID tags, can also verify the purchase of the

items as they are placed in the cart and, if desired, communicate with a billing

system to automatically bill the shopper for the purchases.

In addition to the systems that have been demonstrated and widely discussed in

the literature, several additional improvements can be expected as RFID

technology begins to become more ubiquitous. In general, these concepts can be

described in the context of guided shopping experiences for consumers,

enhanced by the information flow enabled with RFID technology and other

electronic systems.

The main objective of this system is to automate the billing and trolley movements according to the customers.

EXISTING SYSTEMS:

Total Prices are calculated at the end billing only.

Trolley movements are done by manually.

Didn’t know the exact manufacture and expiry date

PROPOSED SYSTEM:

Billing of products by means of automatically.

Trolley can be dragged with help of users Remote.

Final amount can be seen in the Trolley it self.

Microprocessors and Microcontrollers :A digital computer typically consists of three major components: the

Central

Processing Unit (CPU), program and data memory, and an Input/Output (I/O) system.

The CPU controls the flow of information among the components of the computer. It

also processes the data by performing digital operations. Most of the processing is

done in the Arithmetic-Logic Unit (ALU) within the CPU. When the CPU of a

computer is built on a single printed circuit board, the computer is called a

minicomputer. A microprocessor is a CPU that is compacted into a single-chip

semiconductor device.

Microprocessors are general-purpose devices, suitable for many applications. A

computer built around a microprocessor is called a microcomputer. The choice of I/O

and memory devices of a microcomputer depends on the specific application. For

example, most personal computers contain a keyboard and monitor as standard

input

and output devices.

A microcontroller is an entire computer manufactured on a single chip.

Microcontrollers are usually dedicated devices embedded within an application. For

example, microcontrollers are used as engine controllers in automobiles and as

exposure and focus controllers in cameras. In order to serve these applications, they

have a high concentration of on-chip facilities such as serial ports, parallel input-

output ports, timers, counters, interrupt control, analog-to-digital converters, random

access memory, read only memory, etc. The I/O, memory, and on-chip peripherals of

a microcontroller are selected depending on the specifics of the target application.

Since microcontrollers are powerful digital processors, the degree of control and

programmability they provide significantly enhances the effectiveness of the

application.

Embedded control applications also distinguish the microcontroller from its

relative,the general-purpose microprocessor. Embedded systems often require real-

time operation and multitasking capabilities. Real-time operation refers to the fact

that the embedded controller must be able to receive and process the signals from its

environment as they are received. That is, the environment must not wait for the con-

troller to become available. Similarly, the controller must perform fast enough to

output control signals to its environment when they are needed. Again, the

environment must not wait for the controller. In other words, the embedded controller

should not be a bottleneck in the operation of the system. Multitasking is the

capability to perform many functions in a simultaneous or quasi-simultaneous

manner.

The embedded controller is often responsible of monitoring several aspects of a system and responding accordingly when the need arises.

The 8051 is the first microcontroller of the MCS-51 family introduced by Intel

Corporation at the end of the 1970s. The 8051 family with its many enhanced

members enjoys the largest market share, estimated to be about 40%, among the

various microcontroller architectures. The architecture of the 8051 family of the

microcontrollers is presented in this chapter. First, the original 8051 microcontroller

is discussed, followed by the enhanced features of the 8032, and the 80C515.

The 8051 Microcontroller Family Architecture:

The architecture of the 8051 family of microcontrollers is referred to as the MCS-51

architecture, or sometimes simply as MCS-51. The microcontrollers have an 8-

bit

data bus. They are capable of addressing 64K of program memory and a separate

64K of data memory. The 8051 has 4K of code memory implemented as on-chip

Read Only Memory (ROM). The 8051 has 128 bytes of internal Random Access

Memory (RAM). The 8051 has two timer/counters, a serial port, 4 general purpose

parallel input/output ports, and interrupt control logic with five sources of interrupts.

Besides internal RAM, the 8051 has various Special Function Registers (SFR), which

are the control and data registers for on-chip facilities. The SFRs also include the

accumulator, the B register, and the Program Status Word (PSW), which contains the

CPU flags. Programming the various internal hardware facilities of the 8051 is

achieved by placing the appropriate control words into the corresponding SFRs. The

8031 is similar to the 8051, except it lacks the on-chip ROM.

As stated, the 8051 can address 64K of external data memory and 64K of external

program memory. These may be separate blocks of memory, so that up to 128K of

memory can be attached to the microcontroller. Separate blocks of code and data

memory are referred to as the Harvard architecture. The 8051 has two separate read

signals, RD# (P3.7) and PSEN#. The first is activated when a byte is to be read from

external data memory, the other, from external program memory. Both of these

signals are so-called active low signals. That is, they are cleared to logic level 0 when

activated. All external code is fetched from external program memory. In addition,

bytes from external program memory may be read by special read instructions such

as the MOVC instruction. There are separate instructions to read from external data

memory, such as the MOVX instruction. That is, the instructions determine which

block of memory is addressed, and the corresponding control signal, either RD# or

PSEN# is activated during the memory read cycle. A single block of memory may be

mapped to act as both data and program memory.

EMBEDDED SYSTEM:

Def: An embedded system is a computer systems that is part of a larger system.Embedded computing—the use of programmable processors in application-specific systems—has been around for quite some time. However, embedded computing courses that teach students how to design complex embedded systems are relatively new to the curriculum1. Many modern embedded systems contain tens of thousands of lines of code; quite a few include multiple processors. Designing such

systemsrequires quite a few skills. One of the most important skills is an understanding of computer architecture. Since CPUs are critical components of embedded computing systems, their characteristics must be very well understood in order to have any chance of creating an efficient system design.

An embedded computing course is not (at least in my view) a traditional microprocessor-based systems design course. Elsewhere2, Jan Madsen and I outlined the differences between early microprocessor courses and what modern embedded system designers need to know. Early microprocessors were very limited and could perform relatively few computations; they were primarily used as I/O controllers.

This introduced two biases in microprocessor courses. First, the courses were very hardware oriented and spent little time on software—usually almost no time on software above assembly language. Second, they were grounded in the details of a particular microprocessor with knowledge that could be hard to translate to a different microprocessor. Modern embedded computing courses take advantage of high-performance microprocessors that can perform very expensive calculations. This requires us to introduce software as a first-class concept. It also allows us to generalize away from the particulars of one microprocessor to the general principles underlying high-performance microprocessor systems.

Computer science and computer engineering students have always studied computer architecture. In many cases, architecture was an end unto itself. Embedded systems gives the study of computer architecture new motivation: the characteristics of CPUs help determine the characteristics of the embedded system. This doesn’t require us to substantially change what we teach in architecture courses in order to helpstudents understand embedded system design. However, the end-use application does provide a slightly different spin on the traditional subjects of architecture

courses: rather than looking at problems through the lens of the CPU, embedded system designers tend to focus on the characteristics of their programs as determined by the CPU characteristics.

Characteristics of Embedded Systems:

Embedded computing systems generally exhibit rich functionality—complex functionality is usually the reason for introducing CPUs into the design. However, they also exhibit many non-functional requirements that make the task especially challenging:• real-time deadlines that will cause system failure if not met;• multi-rate operation;• in many cases, low power consumption;

• low manufacturing cost, which often means limited code size.•Often mass products 98% of the processors are in ES Sometimes very specialized systems•No or minimal user interface•Resource constraints•Must usually fulfill strict timing•Usually runs forever (no reboot)

Workstation programmers often concentrate on functionality. They may consider the performance characteristics of a few computational kernels of their software, but rarely analyze the total application. They almost never consider power consumption and manufacturing cost. The need to juggle all these requirements makes embedded system programming very challenging and is the reason why embedded systemdesigners need to understand computer architecture.

Examples:

1.Washing machine

2.Car engine control

3.Mobile phone

AT89S51:

Features:• Compatible with MCS®-51 Products

• 4K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 10,000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Fast Programming Time

• Flexible ISP Programming (Byte and Page Mode)

• Green (Pb/Halide-free) Packaging Option

AT89S51

Description:The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but

freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

Pin Description:VCC: Supply voltage.

GND: Ground.

Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1:

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

TABLE 1: Port Pin Alternate Functions

P1.5 MOSI (used for In-System Programming)

P1.6 MISO (used for In-System Programming)

P1.7 SCK (used for In-System Programming)

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.

TABLE 2:

Port Pin Alternate Function

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data memory write strobe)

P3.7 RD (external data memory read strobe)

RST: Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG: Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the

oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.

Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN: Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP: External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1: Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2: Output from the inverting oscillator amplifier.

Memory Organization: MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory:

If the EA pin is connected to GND, all program fetches are directed to external memory.On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.

Data Memory:

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out): The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT: To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will

periodically be executed within the time required to prevent a WDT reset.

WDT During Power-down and Idle:

In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

UART:

The S3CA400A01 UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit.The S3CA400A01 UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.

Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure11-1. The baudrate generator can be clocked by PCLK. The transmitter and the receiver contain 16-byte FIFOs and data shifters.Data, which is to be transmitted, is written to FIFO and then copied to the trans-mit shifter. It is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and then copied to FIFOfrom the shifter.

FEATURE— RxD0,TxD0,RxD1,TxD1 with DMA-based or interrupt-based operation— UART Ch 0 with IrDA 1.0 & 16-byte FIFO— UART Ch 1 with IrDA 1.0 & 16-byte FIFO— Supports handshake transmit / receive

UART OPERATION

The following sections describe the UART operations that include data trans-mission, data reception, interrupt generation, baud-rate generation, loopback mode, infra-red mode, and auto flow control.

Data TransmissionThe data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the break condition. The break condition forces the serial output to logic 0 state for one frame transmission time. This block transmits break signal after the present transmission word transmits perfectly. After the break signal transmission, it continously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode).

Data ReceptionLike the transmission, the data frame for reception is also programmable. It con-sists of a start bit, 5 to 8 data bits,an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error, parity er-ror, frame error and break condition, each of which can set an error flag.- The overrun error indicates that new data has overwritten the old data before the old data has been read.- The parity error indicates that the receiver has detected an unexpected parity condition.- The frame error indicates that the received data does not have a valid stop bit.- The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one frame transmission time.Receive time-out condition occurs when it does not receive data during the 3 word time(This interval follows the setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode.

Auto Flow Control(AFC)S3CA400A01's UART supports auto flow control with nRTS and nCTS signals, in case it would have to connect UART to UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the sig-nal of nRTS by software.In AFC, nRTS is controlled by condition of the receiver and operation of trans-mitter is controlled by the nCTS signal. The UART's transmitter transfers the data in FIFO only when nCTS signal active(In AFC, nCTS means that the other UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte(In AFC, nRTS means that its own receive FIFO is ready to receive data).

Non Auto-Flow control(Controlling nRTS and nCTS by S/W) ExampleRx operation with FIFO1. Select receive mode(Interrupt or DMA mode)2. Check the value of Rx FIFO count in UFSTATn register. If the value is less than 15, users have to set the value of UMCONn[0] to '1'(activate nRTS), and if it is equal or larger than 15 users have to set the value to '0'(inactivate nRTS).3. Repeat item 2.

Tx operation with FIFO1. Select transmit mode(Interrupt or DMA mode)2. Check the value of UMSTATn[0]. If the value is '1'(nCTS is activated), users write the data to Tx FIFO register.

RS-232C interfaceIf users connect to modem interface(not equal null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals areneed. In this case, users control these signals with general I/O ports by S/W be-cause the AFC does not support theRS-232C interface.

Timer/Counters :The Atmel 80C51 Microcontrollers implement two general purpose, 16-bit timers/ counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. When operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. When operating as a counter, the timer/counter counts negative transitions on an external pin. After a preset number of counts, the counter issues an interrupt request.The various operating modes of each timer/counter are described in the follow-ingsections.

Timer 0 Timer 0 functions as either a timer or event counter in four modes of operation. Timer 0 is controlled by the four lower bits of the TMOD register and bits0, 1, 4 and 5 of the TCON register. TMOD register selects the method oftimer gating (GATE0), timer or counter operation (T/C0#) and mode of opera-tion (M10 and M00). The TCON register provides timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0). For normal timer operation (GATE0= 0), setting TR0 al-lows TL0 to be incremented by the selected input. Setting GATE0 and TR0 al-lows external pin INT0# to control timeroperation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generat-ing an interrupt request. It is important to stop timer/counter before changing mode.

Mode 0 (13-bit Timer):

Mode 1 (16-bit Timer):

Mode 2 (8-bit Timer with reloader):

Mode 3 (two 8-bit Timer):

Timer 1: Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode. The following comments help to understand the differences:• Timer 1 functions as either a timer or event counter in three modes of opera-tion. Timer 1’s mode 3 is a hold-count mode.• Timer 1 is controlled by the four high-order bits of the TMOD register and bits 2, 3, 6 and 7 of the TCON register.The TMOD register selects the method of timer gating (GATE1), timer or counteroperation (C/T1#) and mode of operation (M11 and M01). The TCON registerprovides timer 1 control functions: overflow flag (TF1), run control bit (TR1), interruptflag (IE1) and interrupt type control bit (IT1).• Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is bestsuited for this purpose.• For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be incre-mented by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control timer operation.• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag gen-eratingan interrupt request.• When timer 0 is in mode 3, it uses timer 1’s overflow flag (TF1) and run con-trol bit(TR1). For this situation, use timer 1 only for applications that do not require anTimer/Counter 1 Mode 0: 13-bit Counter

interrupt (such as a baud rate generator for the serial port) and switch timer 1 in andout of mode 3 to turn it off and on.Timer/Counter 1 Mode 2: 8-bit Auto-reload

• It is important to stop timer/counter before changing modes.

Timer Interrupt System:

Interrupts:The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in figure.Each timer handles one interrupt source; that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vec-toring to the timer interrupt routine. Interrupts are enabled by setting ETx bit in IE0 register. This assumes interrupts are globally enabled by setting EA bit in the IE0 register.Each of these interrupt sources can be individually enabled or disabled by set-ting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.Note that table shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in fu-ture AT89 products.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.

Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amp-lifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven. There are norequirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but min-imum and maximum voltage high and low time specifications must be observed.

Idle ModeIn idle mode, the CPU puts itself to sleep while all the on-chip peripherals re-main active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.Note that when idle mode is terminated by a hardware reset, the device nor-mally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhib-its access to internal RAM in this event, but access to the port pins is not inhib-ited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

Power-down ModeIn the Power-down mode, the oscillator is stopped, and the instruction that in-vokes Power-down is the last instruction executed. The on-chip RAM and Spe-cial Function Registers retain their values until the Power-down mode is termin-ated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activ-ated before VCC is restored to its normal operating level and must be held act-ive long enough to allow the oscillator to restart and stabilize.

Status of External Pins During Idle and Power-down Modes: