An Improved Dynamic Latch Based Comparator for8-bit Asynchronous SAR ADC

Anush Bekal1, Rohit Joshi1, Manish Goswami1∗, Babu.R.Singh1 and Ashok Srivatsava21Microelectronics Division, Indian Institute of Information Technology (IIIT-A), Allahabad, INDIA

2Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803, U.S.A

Email:{

rs132}{

imi2013004}{

manishgoswami}{

brs}

@iiita.ac.in1, eesriv@lsu.edu2

Abstract—High speed analog to digital converters (ADC),memory sense amplifiers, RFID applications, data receivers withlow power and area efficient designs has attracted a wide varietyof dynamic comparators. This paper presents an improved designfor a dynamic latch based comparator in achieving higher speedof conversion targeting 8-bit asynchronous successive approxima-tion register (ASAR) ADC. The comparator has two differentstages comprising of a dynamic differential input gain stageand an output latch. The objective of improving the speed ofconversion is done by removing the dead time required for reset inthe differential input stage. In the proposed work the output nodein the differential gain stage requires lesser time to regain highercharge potential. The proposed methodology has been designedand simulated using 180nm CMOS technology operated on asingle 1V power supply and achieves complete 8-bit conversionin 75nsec.

Keywords—Dynamic clocked comparator, Latched compara-tor, analog to digital converter (ADC), Asynchronous SAR ADC(ASAR), digital-to-analog converter (DAC).

I. INTRODUCTION

Comparators are considered to be one of the rudimentarybuilding blocks in most ADCs. Major criterion for an ADCdesign is high speed, low power and lesser real estate overthe chip [1]. In the conventional dynamic latched comparatorsa small input-voltage difference at the input terminals ispulled up to a full scale digital level in a short span of time,by a positive feedback mechanism (regenerative latch). Dueto the random offset errors and internal parasitic/externalload capacitances mismatches they suffer a lot of accuracyissues [2] [3] [4]. To overcome this inaccuracy issue, theconventional architecture used a separate preamplifier stageanteceding the positive feedback stage due to which itcould amplify a small difference in the input voltage to afull scale digital output, negating the kickback noise [5].But for an ADC with a feature of high speed and lowpower application, a comparator without the preamplifier ispreferred since it suffers from high static power dissipation [6].

The present work deals with increasing the speed ofconversion for an 8-bit ASAR ADC which is done byincubating a modified dynamic latch based comparator asproposed. In the reset phase the output nodes has to be chargedup to the initial supply voltage level. This charging of theoutput nodes induces latency in the process of comparison. Wepropose a modified approach to tackle this dead time requiredto reset and improve the speed of comparison. This will inturn make the ASAR ADC to fasten the process of conversion.

In the paper the sections are categorized as follows:Section II describes the working of comparator, proposeddynamic latch based comparator and proposed comparatorperformance, Section III discusses the overall architectureof low power 8-bit ASAR ADC, discusses the simulationresults of ASAR ADC and comparison with other proposedarchitectures while Section IV concludes the paper.

II. PROPOSED DYNAMIC LATCH BASED COMPARATOR

The comparator [7] in Figure 1 has a clk that is used tooperate the circuit in two different modes i.e. reset phaseand the evaluation phase. During the reset phase, when clk=0the output nodes charges to supply voltage while in theevaluation phase, when clk=1 the output nodes generate aninput dependent output. This information is then transmittedto the regenerative latch stage which will then convert to thefull-scale digital values.

However the major pitfall of comparator design is thedead time required to reset the output nodes of the differentialgain stage back to supply voltage. Since the circuit has towait for the next reset phase it significantly requires a largertime to charge the output node capacitances. This will slowerthe process of comparison which limits the speed of thecomparator.

The proposed design is shown in Figure 2. It retains allimportant features of a comparator as can be obtained in [7]besides offering high speed and removing dead time issue. Itdiffers from Figure 1 with respect to the switching transistorsSM1,SM2 which avoids dynamic power consumption andthe control transistor CM1,CM2 which provides a extramechanism to keep either of the outputs in the differentialpair charged up to VDD. The two cross coupled controltransistors CM1 and CM2 are used which at the beginningof the reset phase (clk=0) are turned OFF since pMOStransistors M4 and M5 pre-charge the output node to VDD.During the evaluation phase (clk=1) the tail transistor nMOSM1 turns ON and the output nodes start to drop at differentrates based on the input voltages at transistors M2 and M3.Figure 3 shows a pictorial representation of the comparisonprocess. The higher input voltage transistor will draw morecurrent which drops the voltage at its drain terminal, turningON either of the control transistors high keeping one controltransistor completely OFF. This arrangement will make oneof the output terminal discharge completely to the groundpotential and keeps the other output node at a higher potential.

2015 IEEE Computer Society Annual Symposium on VLSI

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DOI 10.1109/ISVLSI.2015.68

178

Fig. 1. Original latch based comparator[7].

In the conventional approach, the output nodes was just thefunction of input transistor transconductance and input voltagedifference. This created a timing constraint during the nextreset phase due to fact that the output node capacitances wasagain needed to be charged back to VDD. Extra two nMOStransistors SM1 and SM2 acting as switches are also used inthe proposed work to avoid the direct consumption of currentfrom VDD to ground through the tail transistor M1 resultingin saving static power consumption. The design does not useany specific low voltage transistors.

The current flowing through the input transistors M2 andM3 of the differential gain stage can be related from Eq. 1 andEq. 2

VDi−(t) = VDD − ID2

CDi−t (1)

VDi+(t) = VDD − ID3

CDi+t (2)

Therefore the total differential gain can be expressed as afunction of total charge on the output capacitive load given byEq. 3

AV (t) =ΔVDi+(t)

ΔVin(3)

where VD are the voltages across the output capacitive loads,ID are the currents through the transistors M2 and M3, VDD

is the supply voltage, CD is the output capacitive load, AV istotal differential gain.

A. Delay Analysis

The delay analysis for the proposed architecture is givenas:

tdelay = tO + tlatch (4)

Fig. 2. Proposed latch based comparator.

Fig. 3. Pictorial representation of the comparator during evaluation process.

The discharge delay tO is defined as the time taken by the ca-pacitive load to discharge Cload till either of pMOS transistorsM12/M13 turns ON and the tlatch is defined as latching delayof the regenerative circuit. The discharge delay is given as

tO =CLoutVthn

ID1/2(5)

179

here CLout is the output capacitive load, ID1 is the currentthrough the transistor M1. It must be noted that ID1

2 currentflows through the transistor M1. This equation is derived from[8] given by

I

C=

V

t(6)

The other delay tlatch can be formulated as

tlatch = CLout

[1

gm,latch+

1

gm18, gm19

]ln

ΔVout

ΔVO(7)

ΔVout = VDD/2, ΔVO is the output voltage difference, gm,latch

is the effective transconductance of the latch, gm18/gm19 arethe transconductance of transistors M18/M19.

The proposed architecture has a merit of enhanced latchtransconductance i.e in the proposed work the output nodefrom the differential gain stage will charge up to VDD atthe evaluation phase and turn ON one of the intermediatetransistor, thus enhancing the regenerative process.It is the latching delay of two cross coupled inverters whichis assumed to have a voltage swing of VDD/2. The transistorsM18 and M19 create imbalance in the voltage levels duringthe comparison phase which adds up along with effectivetransconductance of the latch.

Figure 4 shows the transient response of the modifiedcomparator (for two inputs in1= 500mV and in2= 525mV).Due to the control transistors and the extra switches eitherof the outputs pull up to VDD or discharge completely tothe ground. This information is then passed on to the latchto hold this value for a certain instant of time and due tothe cross coupled configuration (positive feedback) it willfurthermore regenerate the signal into the correct logic levels.During the reset phase both the outputs (out1 and out2) arecharged up to the supply voltage while during evaluationphase output out1 remains at a higher potential and out2 iscompletely discharged.

Figure 5 shows the transient analysis of a comparator sub-jected to a single-ended sinusoidal input of 100MHz frequencyhaving an amplitude of 650mV. It can be seen that when out2node remains high, out1 node drops down to zero potential andregains to high potential when clk=0. The major advantage ofproposed work is that only one output node has to be chargedup in the reset phase since during the evaluation phase due tothe previous stature of the control transistors one of the outputnode has already been pulled up to VDD. This speeds up theprocess of comparison which adds a merit of fast conversionprocess.

III. LOW POWER 8-BIT ASAR ADC

Figure 6 shows the block representation of the completelow power 8-bit ASAR ADC design using proposed compara-tor to trigger and complete the process of conversion in a fastermode. The comprehensive working can be summarized as thecomparator outputs being connected to a XOR circuitry whichwill be used as a ready pulse (clock) to be used by the SARand in turn claims the design to be asynchronous. By thisapproach we avoid an external clock required by the SAR.As a preset condition the SAR register is set to a mid-value

Fig. 4. Transient response of the proposed comparator.

Fig. 5. Transient response of the proposed comparator.

range based on the resolution (N=no.of bits) of the ADC. TheSAR logic will now trigger and shift to the correct logic levelsbased on the clock signal provided by the XOR circuitry. Oneof the comparator output is connected to the data input of thesequencer logic of SAR register. A 8-bit ADC will require8 ready signals to complete one conversion. The completeworking and description of this can be found from [9] [10].Figure 7 shows the block diagram of 8-bit charge scaling DACwhich is a combination of two 4-bit charge scaling subDACs.It has two sections namely the MSB array and the LSB arrayconnected with a scaling capacitor.

180

Fig. 6. Low power 8-bit Asynchronous SAR ADC design using ChargeScaling DAC.

Fig. 7. Charge Scaling DAC.

A. Simulation results.

Figure 8 presents the simulation result of 8-bit ASARADC with static latch based comparator [9]. The designconsumes 1.2ms for one full cycle conversion. Figure 9 showsthe transient analysis of the entire ASAR ADC using proposeddynamic latch based comparator for an input of 625mV. Asshown in the Figure 9, the proposed design achieves a fasterlevel of conversion process in comparison with Figure 8.Other inputs are not shown for brevity. After 8 ready signalsgenerated by the comparator output, all the individual bits inthe SAR register attain the correct logic levels.

Figure 10 shows the schematic simulation result of DAC foran input of 600mV. The voltage settling around the samerange of the DAC is shown in the y-axis with respect to thetime on the x-axis. Initially the circuit starts up from the resetcondition for which the SAR has been fixed to the mid-valuerange of the resolution (N=8), corresponds to the value of128=100000002. In this case the supply voltage is 1V whichimplies the corresponding mid-range to be 500mV. The DACsettles around the same range of the input applied whichimplies the error is lesser than 0.5 LSB.

Fig. 8. Simulation results showing the complete conversion of ASAR ADCwith static latch based comparator.

Fig. 9. Simulation results showing the complete conversion of ASAR ADCwith improved dynamic latched comparator.

Fig. 10. Simulation results showing the DAC settling for a input of 600mV.

B. Comparison with other works

Below table summarizes comparison of the present designwith other existing architectures.

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Table of comparisonRef[11]

Ref[12]

Ref[13]

Thiswork

Technology(nm) 180 180 180 180Supply Voltage (V) 1.8 1.8 1.8 1Resolution (bits) 12 - 8 8Power Dissipation(uW) 72 2100 225 47.18Sampling Rate(MSPS) 2 1.1 3 13Conversion Time (ns) 500 909 333 75

IV. CONCLUSION

The proposed work presents an improved dynamic latchbased comparator for 8-bit ASAR ADC. The dead timerequired to reset the output nodes was removed by makinguse of the proposed architecture in the input differential gainstage. This results in improved process of comparison and italso accelerated conversion process of the ADC. The staticpower dissipation was saved by using extra switches. Thesimulation results confirm the entire 8-bit conversion processto be completed in 75ns with a total power dissipation of47.18μW.

ACKNOWLEDGEMENT

The authors would like to thank Prof. Somenath Biswas,Director IIIT-A and Dr. Manjunath Bhandary, PresidentSahyadri College of Engineering & Management for lab fa-cilities, moral support and encouragement respectively.

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[10] S. Tabassum, A. Bekal, M. Goswami, “A Low Power PreamplifierLatch based Comparator Using 180nm CMOS Technology,” IEEE AsiaPacific Conference on Postgraduate Research in Microelectronics andElectronics (PrimeAsia),pp. 208-212, Dec. 2013.

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