an integrated approach to power electronics systems

1 INTRODUCTION

The fundamental approach to power conversionhas steadily moved toward »high-frequency synthe-sis«, resulting in important reductions in converterperformance, size, weight and cost. However, in so-me high frequency power conversion technologies,fundamental limits are being reached that will notbe overcome without a radical change in the designand implementation of power electronics systems. Itis well recognized within the industrial sector thatthe performance of power electronics systems weredriven by improvements in semiconductor compo-nents over the last decades. Moving from bipolar toMOSFET technology [1, 2] has resulted in speedincreases that, today, test the limits of packaginginductance and thermal handling. Thus, an order ofmagnitude increase in switching speed, which ispossible with new device technologies, will requiresubstantial reductions in structural capacitances andinductances associated with device and system-levelpackaging.

For a typical power electronics system, individualpower devices are mounted on the heat sink, andthe drivers, sensors, and protection circuits are im-plemented on a printed circuit board and mountednear the power devices. The manufacturing processfor such equipment is labor and cost-intensive.However, some manufacturers have taken a moreaggressive approach in recent years, developing ahigh level of integration where power semiconduc-

tors in the die form are mounted on a commonsubstrate with wire bonding. Although the wirebonding technology has seen many improvements inreliability, this approach still limits the possibilitiesof three-dimensional integration, as well as havingelectromagnetic layout constraints. The thermal ma-nagement in this type of packaging is essentiallylimited to one-dimensional heat flow, while the re-duction of structural inductance associated withbonding wires have limitations.

It is perceived, however, that power electronicsmodules constitute one of the driving forces to-wards modularization and integration of powerelectronics systems. Recent innovations in powermodules have been mostly pushed by semiconduc-tor development with the help of improved layoutand packaging technologies. The development trendsare focused on increasing current and voltage levels,increasing temperature, enhancing reliability andfunctionality, as well as reducing size, weight andcost [4]. New ideas on power modules include thereduction of the number of interfaces to reduce thenumber of solder layers and the risk of solder im-perfections and thermal fatigue. Another conceptthat has been around is the elimination of the baseplate from the power module, first observed at lowpower and now migrating to higher power applica-tions. In terms of reliability improvement, devicesusing low temperature joint (LTJ) technology donot change their thermal resistance after extensive

Fred C. Lee, Jacobus D. van Wyk, Dushan Boroyevich, Thomas Jahns, Robert D. Lorenz, T. Paul Chow, Ron Gutmann, Peter Barbosa

An Integrated Approach to Power Electronics Systems

UDK 621.38.022IFAC IA 4.0.1

Review

Today's power electronics systems are typically manufactured using non-standard parts, resulting in labor-inten-sive manufacturing processes, increased cost and poor reliability. As a possible way to overcome these problems,this paper discusses an integrated approach to design and manufacture power electronics systems to improve per-formance, reliability and cost effectiveness. Addressed in the paper are the technologies being developed for inte-gration of both power supplies and motor drives. These technologies include the planar metalization to eliminatebonding wires, the integration of power passives, the integration of current sensors, the development of power de-vices to facilitate integration as well as to improve performance, and the integration of necessary CAD tools to ad-dress the multidisciplinary aspects of integrated systems. The development of Integrated Power Electronics Mo-dules (IPEMs) is demonstrated for two applications: (1) 1 kW asymmetrical half-bridge DC-DC converter and (2)1–3 kW motor drive for heating, ventilation and air conditioning (HVAC). Electrical and thermal design tradeoffsof IPEMs and related enabling technologies are described in the paper.

Key words: packaging, power integrated circuits, power semiconductor devices, sensors, and integrated design methodology

AUTOMATIKA 44(2003) 1–2, 5–20 5

ISSN 0005–1144ATKAAF 44(1–2), 5–20 (2003)

power cycles (>50 000), as opposed to devices usinglow temperature conventional solder techniques thatachieve the end of useful life after 30 000 power cy-cles [4].

While semiconductor devices are still one of thedominant barriers for future power system develop-ment, devices do not currently pose the fundamen-tal limitation to power conversion technology. It israther packaging, control, thermal management, andsystem integration issues that are the dominanttechnology barriers currently limiting the rapidgrowth of power conversion applications [3]. To ad-dress some of these issues, this paper briefly discus-ses the technology advancements needed to improvethe characteristics of power electronics systems, aswell as the technologies being developed for inte-gration of multi-kilowatt power electronic equip-ment. Among these technologies being developedare the planar metalization device interconnect, thatallows three-dimensional integration of power de-vices, and the integration of power passives to in-crease the power density, mainly for power supplyapplications. The technologies being developed spana wide range of applications from distributed powersystems to motor drives. The development of packa-ging techniques, integration of current sensors andthe development of power semiconductor devices toeither improve performance or to facilitate integra-tion of power electronics systems are addressed he-reafter. This paper also discusses results obtainedfrom the various technologies being developed with-in the research scope of the Center for Power Elec-tronics Systems (CPES), whose mission is to pro-mote an integrated approach to power electronicssystems in the form of highly Integrated PowerElectronics Modules (IPEMs).

2 PACKAGING OF POWER ELECTRONICS

SYSTEMS – THE DPS EXAMPLE

The use of distributed power systems (DPS) forcomputer and telecommunication applications hasopened up the opportunity to develop a standardi-zed modular approach to power processing, whichwill improve the design and manufacturing proces-ses significantly, as well as enhance the electrical sys-tem performance. For this reason, a DPS has beenchosen to demonstrate the advantages of integra-ting power electronics systems.

The structure of a typical DPS is shown in Figure1 (a), while a building block of a front-end conver-ter is illustrated in details in Figure 1(b). A typicalthree-dimensional solid-body model representationfor this type of system is shown in Figure 2(a). Asobserved, the existing approach requires discretecomponents, which makes it difficult to optimizespace usage and to increase power density of the

entire system. The solid-body model shows that thecomponents of the front-end converter are distrib-uted on the printed circuit board, while Cu tracesare routed to distribute power and control signalsto all devices. This type of layout approach presentssevere limitations from the electrical and thermalviewpoints. Figure 2(b) shows the top view of the3-D solid-body model. The major components areidentified in the same figure, as well as the criticalpaths defining which components must be placednext to each other in order to reduce parasitic in-ductance. The inductance formed by the criticalloop will generate voltage overshoot across the PFCand DC-DC switches during turn-off.

Although bringing devices together helps reducethe structural inductances, there is a clear limitationto this packaging approach because the space opti-mization is limited by the form factor of the vari-ous components. Therefore, the structural inductan-ce of the packaging approach shown in Figure 2(a)becomes a limiting factor to increasing switchingfrequency and power level. The only way to overco-me this problem is to minimize the parasitic induc-tance of critical paths by seeking integrated approa-ches for power devices and components. The reali-zation of an integrated power electronics system re-quires advances in technologies, which depend uponfinding solutions to deal with the multi-disciplinaryissues in materials, electromagnetic compatibilityand thermal management.

6 AUTOMATIKA 44(2003) 1–2, 5–20

F. C. Lee et al.An Integrated Approach to Power Electronics Systems

a)

b)

Fig. 1 (a) Distributed power system and (b) front-end PFC and DC-DC converters

Although the end objective is to integrate functi-ons and components for both the PFC and DC-DCconverters shown in Figure 1(b), the results repor-ted hereafter are related to the integration of thefront-end asymmetric half-bridge DC-DC converter(AHBC) illustrated in Figure 3. In the same figure,two blocks are highlighted as active and passiveIPEMs. The active IPEM represents the integrationof power MOSFETs and gate drivers, while thepassive IPEM represents the electromagnetic inte-gration of the DC blocking capacitor, transformer

and output inductors of the current doubler confi-guration used in the AHBC. The main purposes ofintegration are to reduce parts count, increase po-wer density, develop a modular approach to powerelectronics systems, and reduce the overall numberof interconnections at the system level.

2.1 DPS IPEM Design and Implementation Using theEmbedded Power Technology

In designing an integrated system, several stepsmust be taken towards defining specifications at thesystem level, as well as at the module level. Table 1shows specifications for the DC-DC converter at200 kHz, while Table 2 and Table 3 describe the re-quirements for the active and passive IPEMs.

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F. C. Lee et al. An Integrated Approach to Power Electronics Systems

a)

b)

Fig. 2 Typical component layout for DPS applications: (a) 3-D so-lid-body model and (b) top view and critical paths of a typical DPS

front-end converter

Fig. 3 Asymmetrical half-bridge DC-DC converter (AHBC) with ac-tive and passive IPEMs

Table 1 System-level (DC-DC converter) specifications

Parameter Specification

Input voltage 300 V – 415 V

Output voltage 48 V ± 10 %

Output voltage ripple (pk-pk) 480 mV

Isolation (output to ground) >10 kΩ

Output power 1 kW

Ambient temperature 50 ºC

Air flow at 5000 ft20 CFM at 50 ºC amb

15 CFM at 35 ºC amb

Safety UL 60950

EMI system-level EN55022 Class B


DC bus voltage (500 device) 400 V

Surge of DC Bus voltage 415 V

Power terminal current 25 A

Junction temperature (max.) 150 ºC

Maximum operating junction temperature 125 ºC

Operating case temperature –20 ºC – 100 ºC

Isolation voltage (case-to-terminal

at 60 Hz)>2500 V

Power terminal leakage current < 500 µA

Maximum switching frequency 500 kHz

Table 2 Active IPEM requirements


DC blocking capacitance >2 µF

Leakage inductance 2 µH

(ZVS range 50 % – 100 %)

Magnetizing inductance 45 µH

Safety UL 60950

Table 3 Passive IPEM requirements

Several approaches have already been developedfor integrated packaging of power modules. Previ-ous work reported a MCM-D package for powerapplications [6], where a Si chip with one powertransistor was used as a MCM-D substrate ontowhich the gate driver was mounted using flip-chiptechnology. A high level of integration was accom-

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Fig. 4 (a) Three-dimensional view of the active module using em-bedded power technology and (b) top view after metalization and

assembly of gate driver

a )

b)

Table 4 Design summary for DPS IPEM

Property Gen I Gen II – Preliminary design Gen II – Proposed design

Substrate Area (mm2) 40 × 30 27 × 30 28.5 × 27.3

Inductance (nH) 10 3 3

Common-mode (CM) capacitance (pF) 4 60 20

Cm current at 200 kHz (A) 0.1 1.9 0.6

Temperature rise (ºC) 38 39 39

plished, but the power bus was still interconnectedto the base substrate using bond wires. This also oc-curred in the IPM packaging technology, wherepower chips were mounted and interconnected withbond wires onto a high-density substrate [7], andthe concepts of embedded chips and bump-less bon-ding were investigated for microelectronics packag-ing applications [8]. A planar device metalizationtechnology was also developed in CPES, namelyEmbedded Power [9], which is a 3-D multilayer inte-grated packaging technology that sandwiches powerbus structure and integrated circuitry. The principleof this technology is shown in Figure 4(a), whilethe metalization view of a power module is shown inFigure 4(b). Note that since one of the main structu-ral elements of this planar technology is a ceramicchip carrier, the structure is suitable to mountingpassive devices and advanced control functions in3-D fashion directly on the carrier.

The DPS IPEM was designed to reduce the geo-metric footprint, while maintaining electrical andthermal performance [10]. A set of DPS IPEM mo-dels based on three-dimensional geometry was de-veloped, including both electrical and thermal mo-dels. The electrical models were implemented inMaxwell Q3D for parameter extraction, while thethermal models were implemented in I-DEAS ther-mal.

Figure 5 and Table 4 summarize the results ob-tained from the design optimization. The first de-sign was based on the wire bonding approach, whilethe other two were implemented with the embed-ded power technology. The proposed design achie-ved 35 % reduction of footprint area as comparedto the wire bonding version, and approximately 9 %reduction in comparison to Generation II prelimi-nary design shown in Figure 5(b). The planar inter-connects reduced the structural inductance by a fac-tor of 3 when compared to the wire bonding tech-nology (Table 4 shows the largest structural packag-ing inductance only, but other paths also showed si-milar reduction ratio). However, the common-mode(CM) capacitance is increased by a factor of 5, ascompared to the wire-bonding module. The para-metric thermal study performed on the embeddedpower modules revealed that footprint reduction in-creases the temperature rise, ceramic thickness does

mendation. The proposed design recommendationsbased on cost and performance tradeoffs were 0.6mm-thick Al2O3 ceramic substrate and 3 mm-thickheat spreader to improve thermal management andprovide adequate mechanical stability. The next gene-ration of the DPS IPEM will target at eliminatingthe heat spreader, while still maintaining electrical--thermo-mechanical performances similar to theproposed design shown in Figure 5(c).

2.2 Design and Implementation of Passive IPEMs UsingHybrid Winding Technology

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Fig. 5 (a) Generation I IPEM using wire bonding, (b) generation IIIPEM preliminary design using embedded power and (c) generation

II IPEM proposed design also using embedded power

a)

b)

c)

not greatly affect the module thermal performance,and the heat spreader thickness improves thermalmanagement [10]. An AlN substrate presented aslightly better thermal performance than Al2O3.Since ceramic thickness does not affect temperaturerise largely, it should be chosen to minimize costimpacts as well as common-mode capacitance at themodule level. Although the heat spreader improvesthermal management, it has a detrimental effect ifthe thickness increases beyond the optimal recom-

Fig. 6 Components of the passive IPEM: (a) equivalent circuit, (b) exploded view of the passive IPEM, and (c) 1 kW prototype

a)

b)

c)

For the design of the passive IPEM, constraintsand parameters for all components were obtainedfrom the system requirements and circuit analyses,as illustrated in Table 3. Because of the currentdoubler configuration, the structure of the passiveIPEM has been realized by stacking two transfor-mers, as illustrated in Figure 6(a). The transformersare built with two E-planar cores that share a com-mon I core, as detailed in Figure 6(b). The DCblocking capacitor of the AHBC is implemented intransformer T1 using the hybrid winding technology[11, 12]. This technology is implemented using Cutraces on both sides of the winding and a dielectriclayer placed in the middle to enhance the capacitivecomponent of that winding. The transformer T2 is aconventional planar low-profile transformer. The in-ductances of the current doubler output filter arerealized by the magnetizing inductances of bothtransformers. Figure 6(c) shows a picture of thepassive IPEM implemented for the AHBC.

2.3 Experimental Results Using Active and Passive

IPEMs

The AHBC configuration using the combined ac-tive and passive IPEMs is shown in Figure 7(a). Themodular approach to system integration is clearlyseen in this figure, where sub-assemblies are arran-ged and externally connected via a PCB placed ontop. Figure 7(b) shows the waveforms measured atfull load, in which Vds1 and Vg1 are the waveformsrelated to the upper switch of the AHBC, while anefficiency comparison between the IPEM-based anddiscrete approaches are shown in Figure 7(c).

There are several advantages to integrated powerelectronics systems using the IPEM concept. Firstly,the modular approach can reduce the design andimplementation time cycles, as well as simplify theassembling process. Secondly, the integration offunctions in the form of IPEMs leads to improvedusage of space, which increases power density andreduces profile of power electronics systems. Forthe example under consideration, the power density

is increased by 2.8 times with respect to the dis-crete approach previously presented [13]. Thirdly,the reduction of interconnects at the system leveldue to integration certainly improves the system re-liability, but this improvement has yet to be quanti-fied. Fourthly, the reduction of structural packaginginductances leads to improved electrical perfor-mance. Reducing voltage ringing across the powerswitches allows increasing the switching frequencyto further improve power density, as long as ther-mal de-rating is not implied.

3 TECHNOLOGY DEVELOPMENT FOR MOTOR

DRIVES (MD)

Fans, pumps and compressors used in many in-dustrial, commercial and residential applications, of-fer significant opportunities for energy savings,since they are generally powered by constant-speeddrives rather than by more energy-efficient ad-justable-speed drives. For example, heating, ventila-tion, and air conditioning (HVAC) systems consumemore than 20 % of the total energy in the world,according to an EPRI report [14]. Projections indi-cate that replacing constant-speed drives in currentHVAC systems with adjustable-speed drives could

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Fig. 7 (b) waveforms under test at 1 kW (VG1: 10 V/div, VDS1: 200V/div, VSEC: 100 V/div, IPRIM: 20 A/div, time scale: 1 µs/div), and

(c) efficiency

Fig. 7 (a) View of the IPEM-based prototype

b)

c)

save 35 % of this energy. Although the benefits ofadjustable speed control for many industrial, com-mercial and residential applications have been welldocumented, their success in large-scale productionhas been limited due to their higher purchase costand perceived reliability limitations. However, effec-tive means of integrating motor drives via theIPEM concept can achieve major improvements incost, reliability, and performance. The major tech-nology developments for motor drives are focusedon active gate drivers [15] to control dv/dt anddi/dt, motor drive IPEM implementation to help re-duce cost [16], and the use of double-sided coolingto improve thermal management of the motor driveIPEM [5].

3.1 Active Gate Driver Control of dv/dt and di/dt

Figure 8 shows the equivalent model for the flex-ible dv/dt control topology applied to the gating cir-cuit for an IGBT. A small external capacitor CM isused to sense the switch's collector (C) terminal

voltage derivative dv/dt and to generate currentfeedback to the gate (G) terminal for dv/dt control.The impact of the gate-collector capacitance on re-ducing the dv/dt of three-terminal switching devicesis a well-understood phenomenon known as theMiller effect. This new approach introduces a de-pendent current source at the gate node whose cur-rent is proportional to the value of the capacitorcurrent Im achieving the same effect as changingthe value of the external Miller capacitor CM. Infact, the net effect of the control circuit can be in-terpreted as providing an electronically controlledMiller capacitance. The net current at the gatenode contributed by the external Miller capacitorcombined with the dependent source is +Im(1−A).Adjusting the value of A over a range, includingpositive and negative polarities, makes it possible toelectronically increase or decrease the effective val-ue of the total Miller capacitance [15].

Flexible control of the transistor di/dt duringhard switching can be achieved by applying a dual

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Fig. 8 (a) Equivalent circuit for flexible dv/dt control and (b) ex-perimental test results for turn-off dv/dt control of a 1200 V/70 A

IGBT operated at 300 V/15 A at three different dv/dt settings

a)

b)

Fig. 9 (a) Equivalent circuit for flexible di/dt control and (b) experi-mental test results for turn-on di/dt control of a 1200 V/70 A IGBT

operated at 300 V/15 A at three different di/dt levels

a)

b)

version of the Miller capacitance used to controldv/dt. Figure 9(a) shows the equivalent model forthe flexible di/dt control topology. The small exter-nal inductance Ls connected in series with theswitch emitter is used to sense the di/dt value andgenerate feedback voltage for the control circuit.The value of this inductance can be chosen to besufficiently small that it has negligible effect on thedominant time constant of the gate drive circuit.Using the same conceptual approach as in the dv/dtequivalent circuit shown in Figure 8(a), the mea-sured di/dt is used to control a dependent currentsource that extracts current If from the switch's gatenode. The value of this current is +B ⋅VLs, whereVLs = Ls ⋅di/dt and B is an adjustable gain analogousto A in the dv/dt control circuit. Changing B makesit possible to electronically adjust the value of di/dt,providing the same effect as changing the value ofthe external inductance Ls [15].

3.2 Flip-chip-on-Flex Packaging of Motor Drive IPEM

The flip-chip on flex motor drive IPEM is an ex-tension of the successfully implemented lower-vol-tage (42 V) lower-power (500 watts) prototype unitfor automotive applications [16]. In this previous de-monstration, a single leg half-bridge was implemen-ted with Si MOSFETs and Si PIN diodes. Theseunits were constructed using commercially availableflex (polyimide) substrates that are well accepted inautomotive signal electronics systems for low-powerapplications.

Based upon this demonstration of a half-bridgecircuit and companion evaluation of flex high volta-ge capability, a higher power (1–5 kilowatt), higher-voltage (600–1200 V) power flex circuit has beendesigned and is being implemented for the motordrive IPEM using Si IGBTs and Si PIN diodes. Thefirst prototype of this circuit is shown in Figure 10,which is implemented in non-commercial flexcircuitry. Commercial IGBTs and PIN rectifierswith moderate switching speed have been used(IRG4PC50W and HFA15TB60S, respectively). Theelectrical performance of this prototype indicatesthat full voltage and current can be handled in asmall footprint. The switching waveforms of thishalf-bridge IGBT/PIN rectifier module are shown inFigure 11. They were obtained with a load consis-ting of an inductor of 200 µH connected in serieswith a resistor of 1.60 Ω. A small (<10 %) voltageovershoot can be observed in the turn-off wave-forms shown in Figure 11(a), while significant diodereverse recovery current is apparent in the turn-onwaveforms illustrated in Figure 11(b).

A power flex test vehicle designed using commer-cial flex circuitry for testing several alternativephase-leg and bridge physical layouts is shown in

Figure 12. A full complement of test structures isincluded and is presently under evaluation. How-ever, based upon the flip-chip on flex results todate [16], the low-to-medium power electronics ap-plications can be implemented with low parasiticsand high power density. Thermal design considera-tions will be a factor in medium-to-high power ap-plications.

12 AUTOMATIKA 44(2003) 1–2, 5–20


Fig. 10 Flex-circuit motor drive IPEM generation 1 prototype: (a)flip-chip IGBT die on flex with under-fill, (b) assembled IGBT

IPEM, and (c) IGBT device characteristics

a)

b)

c)

3.3 Double-Sided Cooling of MD IPEM Using MiniatureHeat Pipes

IPEM planar interconnect technologies offer op-portunities for improved thermal management byallowing thermal access to the upper side of thepower devices [5], as illustrated in Figure 13(a).

Double-sided cooling of IPEMs has the potential toallow increased chip power dissipation and/or to im-prove IPEM reliability by lowering the junction op-erating temperature. To evaluate the effectiveness of

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Fig. 11 Flex-circuit Generation 1 prototype electrical performance: (a) high side IGBT switch turn off waveform and (b) high side IGBTmodule switch turn on waveform

a) b)

Fig. 12 Flex circuit Generation 2 test structures (Sheldahl standard Novaflex® technology, with eitherphoto-imaged solder mask or film overlay solder mask. Double-sided 35 µm Cu and 50 µm dielectric

substrate).

Fig. 13 (a) Double-sided cooling of flex packaging using heat pipe and (b) temperature reduction

a) b)

heat pipes for removing heat from the top side ofthe power module, a nominal case was analyzedwith ANSYSTM finite element software in both sin-gle-sided and double-sided configurations. The re-sults are illustrated in Figure 13(b), which showsthat 18 % more dissipation can be tolerated fordouble-sided cooling for the same maximum junc-tion temperature. Alternatively, a 12 ºC reduction inthe maximum temperature is observed with double--sided cooling compared to the single-sided case forthe same power dissipation (100 W). This corre-sponds to a 15 % decrease in the maximum tem-perature rise relative to ambient temperature. Forthis test configuration, twenty-eight percent of theheat is removed from the upper side of the IPEMwith double-sided cooling.

4 INTEGRATION OF CURRENT SENSORS IN IPEMS

Benchmarking studies focusing on reliability andcost of power electronic systems converged on thecurrent sensor as a major opportunity for improve-ment via integration. The baseline technology is theHall effect detector with a flux concentration toro-idal core used in either the simple open loop formor in an active null regulated flux form as shown inFigure 14.

The current sensor integration objectives are to re-duce the interconnections at both signal and powerlevels, reduce the parasitics in the power flow path,and reduce the number of components, while main-taining the accuracy, range, bandwidth and isolationproperties of the baseline technology. To achieve

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Fig. 14 The active null-regulated, Hall effect current sensor with flux concentrating toroid

Fig. 15 Direct sensing (shunt or pilot current) with integrated current observer

this objective, candidate technologies were evaluated,bench test beds were developed to evaluate alterna-tive technologies and develop useful design appro-aches, as discussed in the following subsection.

4.1 Integrated current sensing alternatives

Current sensing can be broken down into two ba-sic approaches: direct and magnetic field-based.The direct approach has two general forms: shuntsand pilot current devices. Shunts generally use anin-line resistive substrate with Kelvin terminal volt-age sensing. This approach lacks galvanic isolationbut is very inexpensive and has the potential to beeasily integrated into IPEM. The lack of galvanic iso-lation can be substantially mitigated by using onlythe lower bus location on each totem pole switch/antiparallel diode pair. Pilot current devices effective-ly channel the current from one of the active devi-ce cells to an active null-regulated (virtual ground)circuit. If the pilot device cell is well matched tothe other cells, then this approach allows a highlyintegrated sensing method, albeit with compromisesin galvanic isolation. In both direct sensing cases, acurrent observer is used to estimate the phase cur-rent. The observer bandwidth is a significant chal-lenge. These approaches are shown conceptually inFigure 15 and are part of the ongoing CPES re-search effort on integrated current sensors.

The magnetic field-based approaches depend onplacing materials, which have physical propertiessensitive to magnetic fields, in magnetic fields pro-

duced by conductors. Such field detecting methodsinherently offer some form of galvanic isolation.The classical Hall effect magnetic flux detector is onesuch device. However, its low sensitivity implies useof flux-concentrating cores, which yields bulky sen-sors not amenable to integrated packaging. By com-parison, giant magnetoresistive (GMR) materials

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Fig. 16 GMR detectors in mean field-sensing configuration with bridge-based temperature decoupling

Fig. 17 Decoupling fields via geometric placement of GMR mean field detectors

have very high sensitivity, which portends the po-tential for direct IPEM integration without corematerial [17]. Magneto-optical materials also offersuch potential, but due to their more modest fieldsensitivity, the relative bulk volume required doesnot easily allow integration in IPEMs. Figure 16shows a »sandwich« GMR detector in a bridge form[18].

The most challenging issue in use of such field de-tectors is the 3-D geometric design to decouple un-wanted fields from the desired field without resor-ting to core materials [19]. Figure 17 shows the ge-neral problem and Figure 18 shows one approachused in CPES bench testing. The sensed load cur-rent result is shown in Figure 19. The major ongo-ing issues in the CPES IPEM current sensor integra-tion effort are focusing on 3-D design of the IPEMwith integrated GMR field detectors [20] and inte-grated shunt (or pilot current) sensors with hard-ware current observers. Both technologies are po-tential solutions to the interconnection and parasi-

tics objectives. Primary performance issues are sig-nal-to-noise ratio (S/N), and resolution-to-range ra-tio (R/R), cross-coupled physical effects, and band-width.

5 DEVELOPMENT OF DEVICES FOR DPS AND MD

APPLICATIONS

The scope of the device development withinCPES is on the demonstration of novel discreteand integratable devices to facilitate IPEM imple-mentation and to relief integrated packaging re-quirements, as well as to enhance performance forDPS and MD applications.

5.1 High-Voltage Si Trench Rectifiers

Poor reverse recovery characteristics of rectifierslimits switching frequency and stress the powerswitches in the power electronics circuits. To over-come this problem, a high-voltage trench sidewalloxide-merged pin/Schottky (TSOX-MPS) rectifier[21, 22], as shown in Figure 20(a), was proposed to

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Fig. 18 IPEM totem pole with integrated GMR mean field detector bridges

Fig. 19 Current measurement performance of IPEM integratedGMR detectors: (1) signal from scope current probe instrumenta-

tion, and (2) signal from GMR field detector summation

Fig. 20 (a) Schematic cross-section of high-voltage TSOX-MPS rectifier and (b) reverse recovery characteristics of 600 V TSOX-MPS rectifi-er and conventional pin junction rectifier

a) b)

reduce both IRP and Qrr. This hybrid rectifier is ac-tually a junction rectifier with adjacent Schottky re-gions separated with sidewall spacers. The oxidespacers not only suppress the reverse leakage cur-rent but also prevent lateral boron diffusion, thusallowing a more precise control of the Schottky re-gion widths. Figure 20(b) shows the reverse recove-ry current waveform for this trench rectifier at roomtemperature. The reverse peak current and the re-verse recovery charge are 30 % and 50 % smaller,respectively, than those from the conventional pinjunction rectifier. The Si trench rectifier discussed inthis section is suitable to improve efficiency forPFC applications.

5.2 Integrated Si DMOSFET/MPS Rectifier

The switching performance of the verticalDMOSFET is related to the reverse recovery char-acteristics of the anti-parallel diode. The anti-paral-lel diode of DMOSFETs has poor reverse recoverycharacteristics because of the high minority carrierlifetime in the drift region, which limits the switch-ing capability of the power DMOSFET [23]. Smal-

ler reverse recovery charge and faster charge re-moval from the diode is necessary for faster switch-ing and reduced power loss. To minimize the prob-lems with the reverse recovery, a new device struc-ture has been developed that integrates an anti-pa-rallel merged PIN Schottky (MPS) rectifier withinthe conventional DMOSFET. The structure of theintegrated DMOSFET/MPS rectifier is shown inFigure 21(a). The metal electrode from the n+-sour-ce region of the DMOSFET is extended to the sur-face n-drift region. The metal selected has the ap-propriate work function so that a Schottky contactis formed with the n-drift region while ohmiccontacts are formed with the p-body and n+-sourceregions, thus resulting in a MPS structure [24].The design and optimization of the 500 V DMOS-FET/MPS was performed in MEDICITM. The newdevice exhibits about 30 % decrease in reverse peakcurrent (IRP) and minority carrier stored charge(Qrr) [25, 26], as shown in Figure 21(b).

5.3 Integrated Si IGBT/MPS Rectifier

IGBTs are extensively used in power electroniccircuits for motor drive applications. The absence ofan integral diode in the IGBT structure requiresthe use of discrete power rectifiers, thus increasingthe parts-count in the circuit and adding cost, aswell as complexity. Furthermore, the interconnecti-on of discrete devices aggravates the overall packa-ge parasitics. To overcome this drawback, researchhas been conducted to explore monolithic integra-tion of the IGBT with the anti-parallel rectifier.Such integration is crucial to facilitate packaging ofdevices for motor drive applications.

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Fig. 21 (a) Cross section of the integrated DMOSFET/MPS powerdevice and (b) Experimental reverse recovery of anti-parallel rectifi-

ers in DMOSFET and DMOSFET/MPS at 100 ºC

a)

Fig. 22 Die outlines of (a) conventional IGBT and (b) monolithicIGBT/MPS rectifier device

In the approach taken, the anti-parallel MPS rec-tifier is monolithically integrated into the IGBT dieby the allocation of a portion of the total siliconarea for the realization of the rectifier. The die-out-lines of the conventional IGBT and the integratedIGBT/MPS device are illustrated in Figure 22. Thesize of the IGBT/MPS die has to be scaled up byabout 30 %, while both the IGBT and the MPS de-vices have to be realized in an area ratio of 3:1.

a) b)

b)

5.4 Integratable, 80 V Si Lateral Trench MOSFETs

Lateral power MOSFETs have been the keycomponents in power ICs used in portable powermanagement products, such as PC peripheral andautomotive applications. It has been shown that atrench quasi-vertical, RESURF MOSFET structurewould be very competitive when compared to theconventional lateral silicon RESURF MOSFETs,particularly in the higher voltages [29].

The structure of the Lateral Trench MOSFETwith an epi RESURF region is shown in Figure 23.The n-epi region on top of the p-substrate consti-tutes the RESURF region that supports the appliedvoltage. Since the channel length of this MOSFETis determined by the vertical diffusion of the p-baseand n+ source, a deep submicron channel lengthcan be achieved without the use of deep submicronphotolithography. Simulation results indicate a lowspecific-on-resistance of about 0.8 mΩ-cm2 for ablocking voltage of 80 V. Besides, a reduction of45 % in the gate charge is possible, which translatesinto an equivalent reduction in the Ron × Qg product,and thus improving the device's figure of merit. other software tools. The user inputs the solid-body

geometry and material data describing the IPEMlayout into the mechanical CAD software such asI-DEAS, which has the capability of exporting the

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Fig. 23 Lateral trench MOSFET – 2002 patent disclosure by T. PChow

6 INTEGRATED DESIGN METHODOLOGY

A multidisciplinary approach to materials opti-mization, electronic packaging techniques and ther-mal management is necessary to realize an integra-ted system. The entire procedure for designing anIPEM, including layout, fabrication and systems ap-plications necessitates integration of CAD tools[29]. An example of integrated analysis used to op-timize the design of the active IPEM can be seenin the flowchart shown in Figure 24. In this exam-ple, a software tool called iSIGHT is used to inte-grate and manage the data exchange between all

Fig. 24 Integrated thermal and electrical analyses

Fig. 25 (a) Partial equivalent circuit of the active IPEM and (b)thermal map of the IPEM

a)

b)

geometry in a number of format files and an op-tional open architectural library that facilitates soft-ware integration. The same geometry and materialdata is shared by both the electromagnetic fieldand thermal analysis software packages. The para-sitic parameters are extracted by Ansoft MaxwellQ3D and transferred as an equivalent circuit, asshown in Figure 25(a), to the circuit simulationsoftware such as Saber to perform transient, EMIand loss analyses. I-DEAS performs the thermalanalysis to produce the temperature map within theIPEM, as shown in Figure 25(c). The interactionbetween Saber and I-DEAS is managed by iSIGHTuntil the temperature and device losses achieveconvergence. This kind of analysis enables the de-signer to evaluate the tradeoffs between the electri-cal and thermal performance at the component andsystem levels. The user can change the relative lay-out, size, and material of the structural parts, oreven select different heat sink sizes or fluid flows,to achieve satisfactory results [31].

7 CONCLUSION

Advancements in semiconductor technologies ha-ve been the major driving force for improving con-verter size, weight, and cost; mostly due to increasein switching frequency. However, for some high fre-quency applications, fundamental limits in packag-ing are being reached. An order of magnitude in-crease in switching frequency will require substan-tial reduction in structural inductances associatedwith device and system-level packaging. Therefore,to provide further improvements in performance,reliability, and cost, it is essential to develop novelintegration and packaging technologies in the formof Integrated Power Electronics Modules (IPEMs),which must enable the integration of all the con-verter functions and not only concentrate on theswitching stage.

These novel integration and packaging technolo-gies, in conjunction with suitable devices, sensorsand integrated design tools used to exploit thephysical properties of available materials have beenthe focus of the CPES research program. The roleof the technologies mentioned above in the IPEMconcept is key to achieving high levels of integra-tion and to enable significant growth of the powerelectronics industry. While technology roadblockshave been found to date, it is evident that furtherinnovations will be necessary as power densitiesincrease. The impacts of systems integration viaIPEMs will enable a rapid growth of power elec-tronics applications with reduced costs and designcycles that can be compared to the impacts in com-puter applications brought up by the VLSI circuittechnology.

ACKNOWLEDGEMENTS

The authors would like to thank Dr. Z. Liang, Dr. J. T.Strydom, Dr. X. Liu, Dr. S. Wen, Mr. L. Zhao, Mr. R.Chen, Dr. F. Canales, Mr. B. Lu, Mr. Z. Chen, Mr. D.Huff, Ms. Y. Pang and Mr. E. Sewall for their contribu-tions to this paper. The ERC Program of the NationalScience Foundation under Award Number EEC-9731677supported this work.

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Integralni pristup sustavima energetske elektronike. Dananji sustavi energetske elektronike se obi~no proizvodeiz nestandardnih dijelova. Posljedica toga je laboratorijska proizvodnja elektroni~kih u~inskih pretvara~a, poveanitrokovi i smanjena pouzdanost. Jedan od moguih na~ina prevladavanja ovih potekoa jest integralni pristup pro-jektiranju i proizvodnji sustava energetske elektronike. Posebice se razmatraju tehnologije razvijene za integracijuu~inskih krugova i motora. Ove tehnologije uklju~uju postupke planarne metalizacije za izbjegavanje i~anih vodo-va, integraciju pasivnih dijelova u~inskih krugova, integraciju strujnih senzora, te razvoj takvih poluvodi~kih kompo-nenata koje olakavaju integraciju i poboljavaju karakteristike ure|aja. Pri projektiranju, zbog multidisciplinarnihaspekata integriranih sustava, treba primijeniti nu`ne CAD alate. Razvoj integriranih modula elektroni~kih u~inskihpretvara~a (engl. integrated power electronics modules, IPEM) ilustriran je na dvije primjene: (1) istosmjerni pretva-ra~ snage 1 kW u asimetri~nom polumosnom spoju i (2) elektromotorni pogon snage 1 . . . 3 kW za grijanje, venti-laciju i klimatizaciju (engl. heating, ventilation and air conditioning, HVAC). Na IPEM-u objanjeni su projektantskii tehnoloki kompromisi elektri~kog i toplinskog projekta.

Klju~ne rije~i: konstrukcija elektroni~kih sklopova, u~inski integrirani krugovi, u~inske poluvodi~ke komponente,senzori, metode integralnog projektiranja

AUTHORS’ ADDRESSES:

Fred. C. Lee, Distinguished ProfessorThe Bradley Department of Electrical and Computer EngineeringVirginia Polytechnic Institute and State UniversityBlacksburg, VA 24061-0179 USA

Jacobus Daniel van Wyk, ProfessorThe Bradley Department of Electrical and Computer EngineeringVirginia Polytechnic Institute and State UniversityBlacksburg, VA 24061-0179 USA

Dushan Boroyevich, ProfessorThe Bradley Department of Electrical and Computer EngineeringVirginia Polytechnic Institute and State UniversityBlacksburg, VA 24061-0179 USA

Thomas Jahns, ProfessorDepartment of Electrical and Computer EngineeringUniversity of WisconsinMadison, WI 53706 USA

Robert D Lorenz, ProfessorDepartment of Electrical and Computer EngineeringUniversity of WisconsinMadison, WI 53706 USA

T. Paul Chow, ProfessorCenter for Integrated Electronics,Rensselaer Polytechnic InstituteTroy, NY, 12180 USA

Ron Gutmann, ProfessorCenter for Integrated Electronics,Rensselaer Polytechnic InstituteTroy, NY, 12180 USA

Peter M. Barbosa, PhDThe Bradley Department of Electrical and Computer EngineeringVirginia Polytechnic Institute and State UniversityBlacksburg, VA 24061-0179 USA

Receved: 2003−10−20

an integrated approach to power electronics systems

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