An Integrated Design Environment to Evaluate Power/Performance Tradeoffs for Sensor Network

Applications

Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna

Dept. of Electrical Engineering - Systems

University of Southern California

Los Angeles, CA

funded by the DARPA Power-aware Computing and Communications program

Project URL: http://milan.usc.edu/

Prasanna: 2HPEC 2002

MILAN: A Model-based Integrated Simulation Framework

A unified environment capable of:– modeling a large class of embedded systems and applications– driving design space exploration tools for rapid evaluation of a large design

space– seamlessly integrating different widely-used simulators into a single

framework for hierarchical simulation– enabling rapid evaluation of different performance metrics such as energy,

latency, and throughput

• Use coarse system models based on key parameters

• Reduce initial design choices• Use low-level simulators to analyze

the reduced design options• Choose one (or more) designs for

implementation

Initial design space

~105-106

Design space pruning

Hierarchical simulation

~100

~10

Prasanna: 3HPEC 2002

Design Flow in MILAN

Application Application (Task Graph)(Task Graph)

Hardware Hardware ResourcesResources

Generic Modeling

Environment (GME 2000)

ApplicationModel

ResourceModel

Constraints

OfflineEstimates

Design Space

Design Space

DesignSpace

Exploration(analytical technique)

InstructionLevel

SimulatorCycle

AccurateSimulatorRT-level

Simulator

Final Design

Ide

ntify

a s

et o

f de

sig

ns

Hierarchical Simulation

Level of abstraction

Accuracy

High-levelPerf.

Estimator

Prasanna: 4HPEC 2002

I. Energy-Efficient Design of Sensor Network Applications

MEMORY

Sensors

RADIO

BUS(DVS)

PROCESSOR

fdSENSOR

fdSENSOR

fdSENSOR

fd

SENSOR

fd

SENSOR

fdSENSOR

fdSENSOR

• A modeling and simulation environment for power-aware design of a multi-node sensor network

• Multi-granularity simulation

• Simulator integration– Results from Wattch simulation are used to

automatically configure ns-2 parameters– Results from Wattch/ns-2 are used to

automatically refine parameters for high-level estimator

Prasanna: 5HPEC 2002

II. Energy-Efficient Design of Kernel Applications for FPGAs

EAT (million nJslicescycles)

Matrix Size

Xilinx Uni-proc.

Linear Array

3 3 0.2 0.1 0.1

6 6 41.2 3.9 3.5

9 9 469.5 39.2 32.5

15 15

10063.3 839.77 580.0

Domain selection

Domain-specific

modeling

Low-level simulation

of candidate designs

Tradeoff analysis and design space

exploration

Kernel applicatio

n

Energy-

efficient design

Low-level simulators(XPower, ModelSim,…)

VHDL code

MILAN

Architecture, parameters

(ranges)

Power estimates

Power function builder(curve fitting …)

Model interpretersComponent specific power

function