an u -l p i n g n s - patpannuto.com · mbus an ultra-low power interconnect for next generation...
TRANSCRIPT
![Page 1: AN U -L P I N G N S - patpannuto.com · MBUS AN ULTRA-LOW POWER INTERCONNECT FOR NEXT GENERATION NANOPOWER SYSTEMS Pat Pannuto, Yoonmung Lee, Ye-Sheng Kuo, ZhiYoong Foo, Benjamin](https://reader034.vdocument.in/reader034/viewer/2022051800/5ac8ae6b7f8b9a5d718ce23d/html5/thumbnails/1.jpg)
MBUS
AN ULTRA-LOW POWER INTERCONNECT FOR
NEXT GENERATION NANOPOWER SYSTEMS
Pat Pannuto, Yoonmung Lee, Ye-Sheng Kuo, ZhiYoong Foo, Benjamin Kempke, Gyouho Kim, Ronald G. Dreslinski, David Blaauw, and Prabal Dutta
University of Michigan
The 42nd International Symposium on Computer Architecture (ISCA’15)
June 13-17, Portland, Oregon, USA
Note: This presentation uses animation in several places. If you are giving this presentation, I highly encourage you to use the powerpoint version, available at http://patpannuto.com/talks
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Siz
e (
mm
3)
Graphic originally from Dennis Sylvester
2
Laptop
1 per Company
1 per Professional
1 per Engineer
1 per Family
1 per Enterprise
1 per person
Corollary:
100x smaller / decade
Bell’s Law:A new computing class every decade
“Smart Dust” should
arrive by ~2017
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Y.-S. Lin ‘08
We have a diverse array of mm-scale components
3
V. Ekanayake ‘04
B. Warneke ‘04
CPUs
CommunicationA. Ricci ‘09
J. Brown ‘13
M. Crepaldi ‘10
P. Chu ‘97
M. Scott ‘03
S. Hanson ‘09
Y.-S. Lin ‘07
ADCs and Sensors
Y. Lee ‘13
Timers
N. Sturcken ‘13
Power Management
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And a few mm-scale systems…
4
B. Warneke ‘07
The 1cc Computer
T. Nakagawa ‘08
Smart Dust
Y. Shapira ‘08
Smart Dew
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But where is the next class of computing?
5
Siz
e (
mm
3)
Graphic originally from Dennis Sylvester
Smartphone
1 per Company
Laptop
1 per Professional
1 per Engineer
1 per Family
1 per Enterprise
1 per person
100 – 1000’s per person
?
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MBus is the missing interconnect that enables the mm-scale computing class
6
• 22.6 pJ / bit / chip, < 10 pW standby / chip
• Single-ended (push-pull) logic
• Low, fixed wire count (4)
• Multi-master
• Power-aware
• Implemented in over a dozen (and growing) mm-scale chips• CPU, Radio
• Flash Memory
• Temperature, Pressure, Imager
• To make half a dozen (and growing) mm-scale systems
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Modularity is key for fast, iterative design, but was previously absent from mm-scale systems
• Phoenix 2008:‒ World’s lowest power computer
‒ Basically a temperature sensor
The Phoenix Processor: A 30pW Platform for Sensor Applications, Mingoo Seok, Scott Hanson, Yu-Shiang Lin, Zhiyoong Foo, Daeyeon Kim, Yoonmyung Lee, Nurrachman Liu, Dennis Sylvester, David Blaauw , VLSI ‘08
A Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor, Gregory
Chen, Hassan Ghaed, Razi-ul Haque, Michael Wieckowski, Yejoong Kim, Gyouho Kim, David
Fick, Daeyeon Kim, Mingoo Seok, Kensall Wise, David Blaauw, Dennis Sylvester, ISSCC ‘11
• Intraocular Pressure 2011:‒ Collaboration for glaucoma health
‒ A pressure sensor
From mm-scale temperature sensor to
mm-scale pressure sensor took 3 years
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MBus enables a modular, composableecosystem of mm-scale components
2 uAhBattery
5 uAhBattery
DecapControl/PMU
TempSensor
Radio+ CDC
MotionDetection/Imager
Pressure Sensing Temp. Sensing
MEMSP. Sensor
Visual Sensing
From temperature
sensor to pressure
sensor:3 months.
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Existing interconnects have served us well for 30 years. What makes mm-scale systems unique?
Node volume is dominated by energy storage
And volume is shrinking cubically
9
Battery“Phone”
Batteries
“Sensor”
Battery
“Sensor”
10’s μW active, 10’s nW sleep, DC 0.1%
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10’s μW active, 10’s nW sleep, DC 0.1%
Existing interconnects have served us well for 30 years. What makes mm-scale systems unique?
Node volume is dominated by energy storage
And volume is shrinking cubically
10
I/O pads begin to account for non-trivial percentage of node surface area
Battery“Phone”
Batteries
“Sensor”
Battery
“Sensor”
1 mm = 1,000 μm
50 μm, minimum viable bond pad
16-20 maximum I/O pins for 3D stacking
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SPI and I2C are like the USB and Firewire of embedded interconnects
• Nearly every microcontroller has both
• Nearly every peripheral has one or the other
• Very few use anything else‒ (except maybe UART)
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What is wrong with how are systems composed today?
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• SPI, invented by Motorola in ~1979
• One master, N slaves
• Shared clock: SCLK
• Shared data bus: MOSI
• Shared data bus: MISO• One Slave Select line per slave
• Key Properties
• One dedicated I/O line per slave• Master controls all communication
SCLK
MOSI
MISOSS
Slave 1
SCLK
MOSI
MISOSS
Slave 2
SCLK
MOSI
MISO
SS0SS1
…
Master
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What is wrong with how are systems composed today?
13
• SPI, invented by Motorola in ~1979
• One master, N slaves
• Shared clock: SCLK
• Shared data bus: MOSI
• Shared data bus: MISO• One Slave Select line per slave
• One interrupt line per slave
• Key Properties
• One Two dedicated I/O lines per slave• Master controls all communication
• Interrupts must be out-of-band
SCLK
MOSI
MISOSS
INT
Slave 1
SCLK
MOSI
MISOSS
INT
Slave 2
SCLK
MOSI
MISO
SS0SS1
…
GPIO0
GPIO1…
Master
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SPI’s I/O overhead and centralized architecturedo not scale to mm-scale systems
14
• SPI, invented by Motorola in ~1979
• One master, N slaves
• Shared clock: SCLK
• Shared data bus: MOSI
• Shared data bus: MISO• One Slave Select line per slave
• One interrupt line per slave
• Key Properties
• One Two dedicated I/O lines per slave• Master controls all communication
• Interrupts must be out-of-band
SCLK
MOSI
MISOSS
INT
Slave 1
SCLK
MOSI
MISOSS
INT
Slave 2
SCK
MOSI
MISO
SS0SS1
…
GPIO0
GPIO1…
Master
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I2C has fixed I/O requirements and a decentralized architecture
15
• I2C, invented by Phillips in 1982‒ Any-to-(m)any on
one shared bus
• Key Properties‒ Fixed wire count (2)
SCL
SDA
Node1
SCL
SDA
Node3
SCL
SDA
Node2
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I2C has fixed I/O requirements and a decentralized architecture
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• I2C, invented by Phillips in 1982‒ Any-to-(m)any on
one shared bus
• Key Properties‒ Fixed wire count (2)
‒ Open-collector• Multi-master
• Flow Control
SCL
SDA
Node1
SCL
SDA
Node3
SCL
SDA
Node2
Open-collector (aka wired-AND)
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The problem is the energy costs of running an open-collector
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Send a “1”: 0 J
VDD = 1.2 V
Send a “0”: 174 pJ
@400 kHz
80% VDD as 1
R = 15.5 kΩ
(“the best”)
No setup, no hold
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The problem is the energy costs of running an open-collector
18
Send a “1”: 0 J
VDD = 1.2 V
R = 15.5 kΩ
(“the best”)
Send a “0”: 174 pJ SCL Alone: 70 μW
@400 kHz
80% VDD as 1
@400 kHz
No setup, no hold
Bigger R?
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The problem is the energy costs of running an open-collector
19
Send a “1”: 0 J
VDD = 1.2 V
Send a “0”: 174 pJ SCL Alone: 70 μW
@400 kHz
80% VDD as 1
@400 kHz
R = 15.5 kΩ
(“the best”)
No setup, no hold
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The energy demands of open-collectors make them unsuitable for mm-scale systems
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SCL Alone: 70 μW
~ 3.1 mm
Two batteries
• Active Energy Budget: 20 μW
• Not an arbitrary number:- Volume Target
- Lifetime Target
@400 kHz
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Can we modify I2C to bring energy costs in line with mm-scale?
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SCL
SDA
Master
SCL
SDA
Slave2
SCL
SDA
Slave1
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Replace the passive pull-up resistor with active circuitry
The Good : Able to achieve 88 pJ / bit (measured)
The Bad : Required clocks running at 5x bus clock on every chip
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A Modular 1 mm3 Die-Stacked Sensing Platform with Low Power I2C
Inter-die Communication and Multi-Modal Energy Harvesting Yoonmyung Lee, Suyoung Bang, Inhee Lee, Yejoong Kim, Gyouho Kim, Mohammed
Hassan Ghaed, Pat Pannuto, Prabal Dutta, Dennis Sylvester, David BlaauwIEEE Journal of Solid-State Circuits
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Replace the passive pull-up resistor with active circuitry
The Good :Able to achieve 88 pJ / bit (measured)
The Bad : Required clocks running at 5x bus clock on every chip
The Bad : “I2C-like” is not I2C – required FPGA to integrate with COTS chips
The Ugly : Hand-tuned, ratioed logic on every chip – Not synthesizable23
Ultra-Constrained Sensor Platform
InterfacingPat Pannuto, Yoonmyung Lee, Benjamin Kempke,
Dennis Sylvester, David Blaauw, and Prabal DuttaIPSN 2012 (Demo)
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“Dark silicon” is more like “dimly lit silicon”
• Clock-gated modules still exhibit static leakage‒ Blows mm-scale power budget
• mm-scale systems perform power-gating‒ This means modules are cold-booting all the time
• Manageable for monolithic designs because something always powered on
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CPU
Sensor Flash
RadioTimer
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Modular mm-scale components introduce novel circuits problems and novel systems problems
CPU
Sensor Flash
RadioTimer
• Clockless cold boot circuits are tricky
• How do you know what’s awake?
• How do you communicate with “pitch black” silicon to wake it up?‒ I2C-variant: custom “wakeup” signal
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The MBus design follows from a careful consideration of all the requirements for modular, mm-scale systems
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MBus
Mediator
MBus
Member
MBus
Member
MBus
Member
MBus
Member
Clock
Data
• Ring Topology
• 2 lines – 4 I/O per node‒ Clock
‒ Data
• “Shoot-Through”
CLK_IN
CLK_OUT
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To be extensible and respect I/O constraints, wire count must be independent of node count
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MBus
Mediator
MBus
Member
MBus
Member
MBus
Member
Clock
DataRecall SPI:
MBus
Member
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Supporting interrupts with a fixed number of single-ended connections requires an arbitration protocol
• Recall: “shoot through”
• C wants to send a message‒ Stop forwarding, drive 0
• The mediator does not forward during arbitration ‒ Also generates the bus clock
28
MBus
Mediator
A
B
D
C
Clock
Data
DATA_IN
DATA_OUT11
11
11
11
1 100
0
0 11
AR
B
I
T
R
A
T
E
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Supporting interrupts with a fixed number of single-ended connections requires an arbitration protocol
• Recall: “shoot through”
• C wants to send a message‒ Stop forwarding, drive 0
• The mediator does not forward during arbitration‒ Also generates the bus clock
29
MBus
Mediator
A
B
D
C
Clock
Data
DATA_IN
DATA_OUT11
11
11
11
1 10
0
0 1100
0
0
0
0
AR
B
I
T
R
A
T
E
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Supporting interrupts with a fixed number of single-ended connections requires an arbitration protocol
• What changes if B tries to send as well as C?‒ B and C drive DATA_OUT to 0
• B’s DATA_IN high, wins
• C’s DATA_IN low, loses
• MBus has topological priority
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MBus
Mediator
A
B
D
C
Clock
Data
11
11
11
11
1 10
0
00 1
100
0
0
0
00
1
AR
B
I
T
R
A
T
E
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Tradeoff between globally unique addresses, address length, and overhead
• Embed addresses in message frames‒ Overhead proportional to number of uniquely addressable device
• I2C uses 7-bit device addresses with design-time LSBs
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• Requires I/O not available
• Makes packaging assumptions‒ mm-scale systems not always PCB
‒ Routing may not be easy• 3D stack
• Flip-chip + TSVs
AR
B
I
T
R
A
T
E
AD
D
R
E
S
S
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Tradeoff between globally unique addresses, address length, and overhead
• 3 Options‒ Short static addresses and allow device conflicts
‒ Long static addresses to avoid device conflicts
‒ Non-static addresses
• MBus does all 3‒ 4-bit: Static short prefixes (device class)
‒ 24-bit: Static long prefixes (unique device ID)
‒ 4-bit: Runtime enumeration protocol (replaces short prefix)
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AR
B
I
T
R
A
T
E
AD
D
R
E
S
S
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Unbounded messages maximize flexibility and minimize overhead
• An MBus message is 0…N bytes of data
• Embed length in message‒ Imposes large overhead for short messages
‒ Forces fragmentation of long messages
• “End-of-message” sentinel byte(s)‒ Imposes large overhead for short messages
‒ Requires escaping if sentinel is in transmitted
‒ Data-dependent behavior, hard to reason about• Worst case 2x overhead!
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AR
B
I
T
R
A
T
E
DA
T
A
AD
D
R
E
S
S
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DA
T
A
MBus “interjections” provide an in-bandend-of-message with minimal overhead
• During normal operation, Data toggles slower than Clock
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AR
B
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DA
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D
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Clock
Data
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MBus “interjections” provide an in-bandend-of-message with minimal overhead
• During normal operation, Data toggles slower than Clock
35
Clock
Data
AR
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MBus “interjections” provide an in-bandend-of-message with minimal overhead
• During normal operation, Data toggles slower than Clock
36
Clock
Data
ACK
Idle
AR
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IN
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Transaction-level ACKs minimize common-case overhead while interjections preserve flow control
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9 bytes
Arbitration
+
Address
+Interjection
AR
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• Clockless cold boot circuits are tricky
• How do you communicate with “pitch black” silicon to wake it up?‒ How do you know what’s awake?
• A power-gated node cannot send‒ Use arbitration edges to drive the
cold-boot circuitry• (Minimal frontend: 35 gates, 4 regs)
‒ Nodes awaken before addressing
• Nodes appear to be “always on”‒ No need to know or track power states
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MBus
Mediator
MBus
Member
MBus
Member
MBus
Member
Clock
Data
The modularity enabled by MBus created a circuits problem and a systems problem
CPU
Sensor Flash
RadioTimer
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These primitives enable an architectural shift in system design
• CPU acts as configurator instead of overseer‒ Preprogram temperature sensor to send radio packets
‒ Not unlike modern SOCs (sleepwalking, μDMA), but distributed
39
Sensor
Radio
CPU
Sensor
Radio
CPU
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Seamless and transparent interaction between power-aware and power-oblivious chips
• Facilitates integration with COTS chips
40*No current COTS chip support MBus, these integrations leverage more traditional buses still
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The majority of interconnect research is focused on performance at the expense of power and area
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RS232
Serial
Parallel
(EPP)
Parallel
(ECP)
USB 1.1 USB 2.0 USB 3.0
5 Gb/s
115 b/s
43.5 million
times faster
ISA PCI Serial
ATA 1.0
AGP 2.0
(4x)
Sata 3.2 PCIx 4.0
x16
22.8 MB/s
31.5 GB/s
1,381
times faster
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Specification and Verilog at http://mbus.io
42
2 uAhBattery
5 uAhBattery
DecapControl/PMU
TempSensor
Radio+ CDC
MotionDetection/Imager
Pressure Sensing Temp. Sensing
MEMSP. Sensor
Visual Sensing
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MBus-based smart dust now on display at the computer history museum
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Protocol Overhead and message length
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Energy per bit of goodput (useful data)
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Power Draw Comparison
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Goodput of parallel MBus
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Saturating Transaction Rate
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Adding additional nodes does not have significant impact on MBus latency
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MBus
Mediator
MBus
Member
MBus
Member
MBus
Member
Clock
Data
MBus
Member
• Recall: “shoot through”
DATA_IN
DATA_OUT
11
10 ns~7 MHz
10 ns
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Some low-hanging fruit…
• Full Duplex is trivial
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• “Selectively parallel”
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Arbitration Detail
Bus Clk
Data In
Data Out
Data In
Data Out
Data In
Data Out
Data In
Data Out
1
2
3
Med
Arbi-
tration
Priority
Drive
Priority
Latch
Reserved
Reserved
Drive
Bit0
Latch
Bit0
Drive
Bit1. ..
←Drive Bus Request
←Does Not Forward
←Drive Bus Request
Wins Arbitration b/c DATAIN = 1 →
Loses Arbitrationb/c DATAIN = 0 →
Does NotForward
Drive Priority Request→
Begin Forwarding→
←Priority Requested, Back Off
←Wins Priority Arbitration
Begin Forwarding→
Drive Bit 0→
Mediator Wakeup0 1 2 3 4 5 6 7 8
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Interjection Detail
CLK In
CLK Out
Data In
Data Out
Data 1 Data 0 Data 1 Data 1 Data 1 Interjection Switch Role Ctl Bit 0 ACK=True Idle . . .
CLK In
CLK Out
Data In
Data Out
Data 1 Data 0 Data 1 Requesuestt Interjection Interjection Switch Role EoM=True Ctl Bit 1 Idle . . .
CLK In
CLK Out
Data In
Data Out
Data 1 Data 0 Data 1 Interjection Switch Role Ctl Bit 0 Ctl Bit 1 Idle . . .
CLK In
CLK Out
Data In
Data Out
Internal Clk
Data 1 Data 0 Data 1 Enter Interjection Interjection Switch Role Ctl Bit 0 Ctl Bit 1 Idle . . .
X X
X X
1
2
3
4
4
4
4
5
6
7
1 (RX)
2 (TX)
3 (FWD)
Med
Latch
Bit6
Latch
Bit7
Latch
|Req
Bit8|Int
Detect
IntReq
Begin
Interjection
Interjection
Asserted
Begin
Control
Latch
Ctl
Bit0
Latch
Ctl
Bit1
Begin
Idle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
End of Data Request Interjection Interjection Control Idle 52
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Tertiary node power-on request
Clock
Data
Sleep Ctl→Bus Ctl
Relea
sePowe
r Gate
Relea
seClock
Relea
seIso
Relea
seRe
set
Relea
sePowe
r Gate
Relea
seClock
Relea
seIso
Relea
seRe
set Bus Ctl→Layer Ctl
←Req Bus ←Resume Forwarding
“General Error”
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Mediator Wakeup Arbitration Mediator-Initiated Interjection Control Idle
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Hierarchical Power Domains
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Implementation
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