an3075 - interfacing with single-wire serial...

AN3075Interfacing with Single-Wire Serial EEPROMs

INTRODUCTION

The AT21CS Series is a family of Serial ElectricallyErasable and Programmable Read-Only Memory(EEPROM) that utilizes the Single-Wire Interface(SWI) protocol.

The family software addressing scheme allows up toeight devices to share a common single-wire bus. Thedevice is optimized for use in many industrial andcommercial applications where low-power andlow-voltage operation are essential. Some applicationsexamples include analog sensor calibration datastorage, ink and toner printer cartridge identification,and management of after-market consumables. Thefamily is available in space-saving package optionsand operates with an external pull-up voltage on the

SI/O line.

HARDWARE

The hardware used in conjunction with the firmware isshared with the Serial Memory Single-Wire EvaluationKit (DM160232). For additional information about thehardware, refer to the DM160232 User Guide found athttp://www.microchip.com. Figure 1 illustrates thehardware used with the source code.

FIGURE 1: USB BASE BOARD AND SWI SOCKET BOARD

Figure 2 is the hardware schematic that depicts theinterface between the Microchip AT21CS Series ofdevices and the USB Base Board microcontroller,AT90USB1287. The schematic shows the necessaryconnections between the microcontroller and the serialEEPROM as tested. The software was writtenassuming these connections. The single I/Oconnection between the microcontroller and the serial

EEPROM includes a recommended pull-up resistor.

FIGURE 2: HARDWARE CIRCUIT

Note: To power the hardware, the USB Base Board should be plugged into a 5V USB port.

Author: Erik FasnachtMicrochip Technology Inc.

Bus Master:AT90USB1287Microcontroller

AT21CS SeriesEEPROM

GND

VCC

GND

PD1

RPUP

VPUP

SI/O

330Ω

2019 Microchip Technology Inc. DS00003075A-page 1

http://www.microchip.com/DM160232

AN3075

FIRMWARE

The purpose of the firmware is to show how to generatespecific single-wire bus transaction using a generic I/Opin on the microcontroller. The focus is to provide theuser with a strong understanding of communicationwith the AT21CS Series devices, thus allowing for morecomplex programs to be written in the future.

The firmware was written in C using Atmel Studio 7.0and shares code with the Serial Memory Single-WireEvaluation Kit (DM160232) firmware. Most of thecomplex tasks have been done in the firmware and theuser is not expected to write any low-level subroutines.

Oscilloscope screen shots of the firmware andhardware are shown in this application note to assist inbetter understanding single-wire bus transactions.

Initialization

In order to use the firmware with the hardware, thefirmware needs to be programmed to the DM160232USB Base Board. The user should use the hex file(seeprom.hex) found in the “default” folder andprogram the firmware to the USB Base Board using theFLIP Software Utility.

Once the firmware is programmed to the USB BaseBoard, the transactions can be monitored using anoscilloscope and the supplied test points.

Overview

The firmware uses the USB Base Board HWB button tostart sending single-wire bus transactions. The RESETbutton is used to reset the microcontroller. Figure 3highlights the location of the HWB and RESET buttons.

FIGURE 3: USB BASE BOARD BUTTONS

After the HWB button is pressed, an approximate twosecond delay is initiated. After the delay, single-wirebus transactions will be transmitted. Once all bustransactions are complete, three red LEDs located onthe USB Base Board will illuminate. Figure 4 is aflowchart representing the bus transactions.

The firmware includes permanent operations to theAT21CS Series device that once completed, cannot beundone. Therefore, the firmware expects the HWB but-ton to be held down after the initial press to ensurethese operations should be performed. Below are theadditional permanent operations:

• Lock Security Register

• Write-Protect ROMZone0 - ROMZone3

• Freeze ROM Zone State

Note: In order to program the firmware to the USB Base Board, the user must use the USB Base Board Firmware Upgrade Procedure in the DM160232 User Guide found at http://www.microchip.com.

Note: In order to restore the initial DM160232 firmware, the Firmware Upgrade Procedure should be performed again using the initial firmware. This initial firmware location is specified in the DM160232 User Guide found at http://www.microchip.com.

HWB Button

RESET Button

DS00003075A-page 2 2019 Microchip Technology Inc.






AN3075

FIGURE 4: FLOW CHART The hardware supplies the VPUP to the device. Thefirmware is setup to supply 3.3V to the device and thisvalue can be changed by the user.

The firmware also includes a scan for thecorresponding slave address on the installed device.This is accomplished by performing a Reset andDiscovery Response, followed by a device addressbyte. The device address byte will start with slaveaddress 0 (000b) and will check whether the deviceACKs the byte. If the device NACKs, the firmware willincrement the slave address and perform the sequenceagain until the device ACKs. Once an ACK is detected,the firmware will recognize that slave address and thataddress will be used for other operations.

Page Write to Main EEPROM

No

Yes

Read Page from Security Register

Read Serial Number

Check Security Register Lock

Read ROM Zone0 - Zone3

Manufacturer ID Read

Operations Complete

Was HWBButton Pressed?

Is HWBButton Held

Down?

Yes PerformPermanentOperations

No

Approx. Two Second Delay

Read Page from Main EEPROM

Page Write to Security Register

Scan for Slave Address


AN3075

SINGLE-WIRE COMMUNICATION

Types of data transmitted over the SI/O line:

• Reset and Discovery Response

• Data Input

- Logic ‘0’ or Acknowledge (ACK)

- Logic ‘1’ or No Acknowledge (NACK)

• Data Output

- Logic ‘0’ or Acknowledge (ACK)

- Logic ‘1’ or No Acknowledge (NACK)

• Start and Stop Condition

Communication with the device is conducted in timeintervals referred to as a bit frame and lasts tBIT in

duration. Each bit frame contains a single binary datavalue. Input bit frames are used to transmit data fromthe master to the slave device and can either be alogic ‘0’ or a logic ‘1’. An output bit frame carries data

from the slave device to the master. In all input andoutput cases, the master initiates the bit frame bydriving the SI/O line low. Once the slave devicedetects the SI/O being driven below the VIL level, itsinternal timing circuits begin to run.

The duration of each bit frame is allowed to vary frombit to bit as long as the variation does not cause thetBIT length to exceed the specified minimum and

maximum values.

Reset and Discovery Response

A Reset and Discovery Response sequence is usedby the master to reset the slave device as well as toperform a general bus call to determine if any devicesare present on the bus.

To begin the reset portion of the sequence, the mastermust drive SI/O low for a minimum time. If the slavedevice is not currently busy with other operations, themaster can drive SI/O low for a time of tRESET. The

length of tRESET differs for Standard Speed mode and

for High-Speed mode. Figure 5, shown below,illustrates the Reset and Discovery Response.

FIGURE 5: RESET AND DISCOVERY RESPONSE WAVEFORM

Note: The Reset and Discovery Response is notconsidered to be part of the data stream tothe device, whereas the remaining trans-actions are all required in order to senddata to and receive data from the device.The difference between the different typesof data stream transactions is the durationthat SI/O is driven low within the bit frame.

tRRT

tDACK

tRESET / tDSCHG

tDRR


AN3075

Data Input

A data input bit frame can be used by the master totransmit either a logic ‘0’ or logic ‘1’ data bit to theslave device. The input bit frame is initiated when themaster drives the SI/O line low. The length of time thatthe SI/O line is held low will dictate whether the masteris transmitting a logic ‘0’ or a logic ‘1’ for that bit frame.For a logic ‘0’ input, the length of time that the SI/Oline must be held low is defined as tLOW0. Similarly, for

a logic ‘1’ input, the length of time that the SI/O linemust be held low is defined as tLOW1.

The slave device will sample the state of the SI/O lineafter the maximum tLOW1 but prior to the minimum

tLOW0 after SI/O was driven below the VIL threshold to

determine if the data input is a logic ‘0’ or a logic ‘1’. Ifthe master is still driving the line low at the sampletime, the slave device will decode that bit frame as alogic ‘0’ as SI/O will be at a voltage less than VIL. If the

master has already released the SI/O line, the slavedevice will see a voltage level greater than or equal toVIH because of the external pull-up resistor, and that

bit frame will be decoded as a logic ‘1’.

LOGIC ‘0’

A logic ‘0’ condition has multiple uses in the I2Cemulation sequences. It is used to signify a ‘0’ data bit,and it also is used for an Acknowledge (ACK)response. Figure 6 depicts the logic ‘0’ input bit frame.

FIGURE 6: DATA INPUT LOGIC ‘0’

tBIT

tLOW0


AN3075

LOGIC ‘1’

A logic ‘1’ condition has multiple uses in the I2Cemulation sequences. It is used to signify a ‘1’ data bit,and it also is used for an No Acknowledge (NACK)response. Figure 7 depicts the logic ‘1’ input bit frame.

FIGURE 7: DATA INPUT LOGIC ‘1’

tLOW1

tBIT


AN3075

Data Output

A data output bit frame is used when the master is toreceive communication back from the slave device.Data output bit frames are used when reading anydata out as well as any ACK or NACK responses fromthe slave device. Just as in the input bit frame, themaster initiates the sequence by driving the SI/O linebelow the VIL threshold which engages the device

internal timing generation circuit.

Within the output bit frame is the critical timingparameter tRD, which is defined as the amount of time

the master must continue to drive the SI/O line lowafter crossing the below VIL threshold to request a

data bit back from the device. Once the tRD duration

has expired, the master must release the SI/O line.

LOGIC ‘0’

If the slave device is responding with a logic ‘0’ (foreither a ‘0’ data bit or an ACK response), it will begin topull the SI/O line low concurrently during the tRDwindow and continue to hold it low for a duration oftHLD0, after which it will release the line to be pulledback up to VPUP (see Figure 8). Thus, when the mastersamples SI/O within the tMRS window, it will see avoltage less than VIL and decode this event as a logic‘0’. By definition, the tHLD0 time is longer than tMRS timeand therefore, the master is ensured to sample whilethe slave device is still driving the SI/O line low.

FIGURE 8: DATA OUTPUT LOGIC ‘0’

tBIT

tHLD0

tMRS

tRD


AN3075

LOGIC ‘1’

If the slave device intends to respond with a logic ‘1’

(for either a ‘1’ data bit or a NACK response), it will not

drive the SI/O line low at all. Once the master releasesthe SI/O line after the maximum tRD has elapsed, the

line will be pulled up to VPUP. Thus, when the master

samples the SI/O line within the tMRS window, it will

detect a voltage greater than VIH and decode this

event as a logic ‘1’. Figure 9 depicts the logic ‘1’ output

bit frame.

FIGURE 9: DATA OUTPUT LOGIC ‘1’

tBIT

tMRS

tRD


AN3075

Start and Stop Conditions

All transactions to the slave device begin with a Startcondition; therefore, a Start can only be transmitted bythe master to the slave. Likewise, all transactions areterminated with a Stop condition and thus a Stopcondition can only be transmitted by the master to theslave.

The Start and Stop conditions require identical biasingof the SI/O line. The Start/Stop condition is created byholding the SI/O line at a voltage of VPUP for a duration

of tHTSS. Figure 10 depicts the Start and Stop

conditions.

FIGURE 10: START OR STOP CONDITION

tHTSS


AN3075

AT21CS SERIES OPERATIONS

Device Addressing

Accessing the device requires a Start conditionfollowed by an 8-bit device address word.

The device protocol sequence emulates what wouldbe required for an I2C Serial EEPROM, with theexception that the beginning four bits of the deviceaddress are used as an opcode for the differentcommands and actions that the device can perform.

Since multiple slave devices can reside on the bus,each slave device must have its own unique addressso tha t the mas te r can access each dev iceindependently. After the 4-bit opcode, the followingthree bits of the device address byte are comprised of

the slave address bits. The three slave address bitsare pre-programmed prior to shipment and areread-only. Obtaining devices with different slaveaddress bit values is done by purchasing a specificordering code.

Following the three slave address bits is a Read/Writeselect bit where a logic ‘1’ indicates a read and a logic‘0’ indicates a write. Upon the successful comparisonof the device address, the EEPROM will return anACK (logic ‘0’). If the 4-bit opcode is invalid or thethree bits of slave address do not match what ispreprogrammed in the device, the device will notrespond on the SI/O line and will return to a Standbystate. Refer to Figure 11 for an example waveform ofthe device address byte.

AVAILABLE OPCODES

Table 2 outlines available opcodes for the device.

TABLE 1: DEVICE ADDRESS BYTE

4-bit Opcode Pre-Programmed Slave Address Bits Read/Write

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Refer to Table 2 A2 A1 A0 R/W

TABLE 2: OPCODES USED BY THE DEVICE

Command 4-bit Opcode Brief Description of Functionality

EEPROM Access 1010 (Ah) Read/Write the contents of the main memory array.

Security Register Access 1011 (Bh) Read/Write the contents of the Security register.

Lock Security Register 0010 (2h) Permanently lock the contents of the Security register.

ROM Zone Register Access 0111 (7h) Inhibit further modification to a zone of the EEPROM array.

Freeze ROM Zone State 0001 (1h) Permanently lock the current state of the ROM Zone registers.

Manufacturer ID Read 1100 (Ch) Query manufacturer and density of device.

Standard Speed Mode 1101 (Dh)Switch to Standard Speed mode operation (AT21CS01 only command, the AT21CS11 will NACK this command).

High-Speed Mode 1110 (Eh)Switch to High-Speed mode operation (device power-on default. The AT21CS11 will ACK this command).


AN3075

FIGURE 11: DEVICE ADDRESS BYTE

Following the device address byte, a memory addressbyte must be transmitted to the device immediately.The memory address byte contains a 7-bit memoryarray address to specify which location in theEEPROM to start reading or writing. Refer to Table 3to review these bit positions.

1 0 1 0 0 0 0 0 AC

K

EEPROM Access Slave 000b R/W

TABLE 3: MEMORY ADDRESS BYTE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Don’t Care A6 A5 A4 A3 A2 A1 A0


AN3075

Write Operations

All write operations to the device begin with the mastersending a Start condition, followed by a deviceaddress byte (opcode Ah for the EEPROM andopcode Bh for the Security register) with the R/W bitset to ‘0’ followed by the memory address byte. Next,

the data value(s) to be written to the device are sent.Data values must be sent in 8-bit increments to thedevice followed by a Stop condition. If a Stop conditionis sent somewhere other than at the byte boundary,the current write operation will be aborted. The deviceallows single byte writes, partial page writes, and fullpage writes.

To ensure that the address and data sent to the devicefor writing are not corrupted while any type of internalwrite operation is in progress, commands sent to thedevice are blocked from being recognized until the

internal operation is completed. If a write interruptionoccurs (SI/O pulsed low) and is small enough to notdeplete the internal power storage, the device willNACK, signaling that the operation is in progress. If aninterruption is longer than tDSCHG then internal write

operation will be terminated and may result in datacorruption. Figure 12 depicts a byte write operation to

the main memory array.

FIGURE 12: BYTE WRITE TO MAIN MEMORY ARRAY

Note: Any attempt to interrupt the internal writecycle by driving the SI/O line low maycause the bytes being programmed to becorrupted. Other memory locations withinthe memory array will not be affected. Ifthe master must interrupt a write opera-tion, the SI/O line must be driven low fortDSCHG.

Device AddressByte (0xA0h)

Memory AddressByte (0x55h)

Data Byte(0xAAh)



Data Byte(0xAAh)


AN3075

Read Operations

Read operations are initiated in a similar way as writeoperations with the exception that the Read/Writeselect bit in the device address byte must be set to alogic ‘1’. There are multiple read operations supported

by the device:

• Current Address Read within the EEPROM

• Random Read within the EEPROM

• Sequential Read within the EEPROM

• Read from the Security Register

• Manufacturer ID Read

The device contains a single, shared-memory AddressPointer that maintains the address of the next byte inthe EEPROM or Security register to be accessed. Forexample, if the last byte read or written was memorylocation 0Dh of the EEPROM, then the Address Pointerwill be pointing to memory location 0Eh of the

EEPROM. As such, when changing from a read in oneregion to the other, the first read operation in the newregion should begin with a random read instead of acurrent address read to ensure the Address Pointer isset to a known value within the desired region.

If the end of the EEPROM or the Security register isreached, then the Address Pointer will “rollover” to thebeginning (address 00h) of that region. The AddressPointer retains its value between operations as long asthe pull-up voltage on the SI/O pin is maintained or thedevice has not been reset. Figure 13 depicts a random

read operation within the main memory array.

FIGURE 13: RANDOM READ WITHIN THE EEPROM

Note: If the last operation to the device accessedthe Security register, then a random readshould be performed to ensure that theAddress Pointer is set to a known memorylocation within the EEPROM.




Data Byte(0xAAh)

Restart condition(tHTSS)


AN3075

CONCLUSION

This application note offers designers a set of firmwareroutines to access the AT21CS Series SerialEEPROMs using a generic I/O pin on themicrocontroller. All routines were written in C usingAtmel Studio 7.0. The hardware used in thisapplication note is the Serial Memory Single-WireEvaluation Kit (DM160232). Details related to single-wire protocol and device operation can be found in theappropriate device data sheet found atwww.microchip.com.


http://www.microchip.com

AN3075

APPENDIX A: REVISION HISTORY

Revision A (05/2019)

Initial release of this document.


AN3075

NOTES:


Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2019 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTSYSTEMCERTIFIEDBYDNV

== ISO/TS16949==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2019, Microchip Technology Incorporated, All Rights Reserved.

ISBN: 978-1-5224-4549-4

DS00003075A-page 17


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com

AtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Austin, TXTel: 512-257-3370

BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088

ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075

DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924

DetroitNovi, MI Tel: 248-848-4000

Houston, TX Tel: 281-894-5983

IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453Tel: 317-536-2380

Los AngelesMission Viejo, CA Tel: 949-462-9523Fax: 949-462-9608Tel: 951-273-7800

Raleigh, NC Tel: 919-844-7510

New York, NY Tel: 631-435-6000

San Jose, CA Tel: 408-735-9110Tel: 408-436-4270

Canada - TorontoTel: 905-695-1980 Fax: 905-695-2078

ASIA/PACIFICAustralia - SydneyTel: 61-2-9868-6733

China - BeijingTel: 86-10-8569-7000

China - ChengduTel: 86-28-8665-5511

China - ChongqingTel: 86-23-8980-9588

China - DongguanTel: 86-769-8702-9880

China - GuangzhouTel: 86-20-8755-8029

China - HangzhouTel: 86-571-8792-8115

China - Hong Kong SARTel: 852-2943-5100

China - NanjingTel: 86-25-8473-2460

China - QingdaoTel: 86-532-8502-7355

China - ShanghaiTel: 86-21-3326-8000

China - ShenyangTel: 86-24-2334-2829

China - ShenzhenTel: 86-755-8864-2200

China - SuzhouTel: 86-186-6233-1526

China - WuhanTel: 86-27-5980-5300

China - XianTel: 86-29-8833-7252

China - XiamenTel: 86-592-2388138

China - ZhuhaiTel: 86-756-3210040

ASIA/PACIFICIndia - BangaloreTel: 91-80-3090-4444

India - New DelhiTel: 91-11-4160-8631

India - PuneTel: 91-20-4121-0141

Japan - OsakaTel: 81-6-6152-7160

Japan - TokyoTel: 81-3-6880- 3770

Korea - DaeguTel: 82-53-744-4301

Korea - SeoulTel: 82-2-554-7200

Malaysia - Kuala LumpurTel: 60-3-7651-7906

Malaysia - PenangTel: 60-4-227-8870

Philippines - ManilaTel: 63-2-634-9065

SingaporeTel: 65-6334-8870

Taiwan - Hsin ChuTel: 886-3-577-8366

Taiwan - KaohsiungTel: 886-7-213-7830

Taiwan - TaipeiTel: 886-2-2508-8600

Thailand - BangkokTel: 66-2-694-1351

Vietnam - Ho Chi MinhTel: 84-28-5448-2100

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393

Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829

Finland - EspooTel: 358-9-4520-820

France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - GarchingTel: 49-8931-9700

Germany - HaanTel: 49-2129-3766400

Germany - HeilbronnTel: 49-7131-72400

Germany - KarlsruheTel: 49-721-625370

Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44

Germany - RosenheimTel: 49-8031-354-560

Israel - Ra’anana Tel: 972-9-744-7705

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - PadovaTel: 39-049-7625286

Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340

Norway - TrondheimTel: 47-7288-4388

Poland - WarsawTel: 48-22-3325737

Romania - BucharestTel: 40-21-407-87-50

Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91

Sweden - GothenbergTel: 46-31-704-60-40

Sweden - StockholmTel: 46-8-5090-4654

UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

05/14/19

http://support.microchip.com

http://www.microchip.com

an3075 - interfacing with single-wire serial...

Documents