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Texas Instruments Incorporated

High-Performance Analog Products

Analog ApplicationsJournal

Second Quarter, 2007

© Copyright 2007 Texas Instruments


2

Analog Applications JournalHigh-Performance Analog Products www.ti.com/aaj 2Q 2007

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Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:

Products

Amplifiers amplifier.ti.com

Data Converters dataconverter.ti.com

DSP dsp.ti.com

Interface interface.ti.com

Logic logic.ti.com

Power Management power.ti.com

Microcontrollers microcontroller.ti.com

Applications

Audio www.ti.com/audio

Automotive www.ti.com/automotive

Broadband www.ti.com/broadband

Digital control www.ti.com/digitalcontrol

Military www.ti.com/military

Optical Networking www.ti.com/opticalnetwork

Security www.ti.com/security

Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

http://www.ti.com/aaj

http://amplifier.ti.com

http://dataconverter.ti.com

http://dsp.ti.com

http://interface.ti.com

http://logic.ti.com

http://power.ti.com

http://microcontroller.ti.com

http://www.ti.com/audio

http://www.ti.com/automotive

http://www.ti.com/broadband

http://www.ti.com/digitalcontrol

http://www.ti.com/military

http://www.ti.com/opticalnetwork

http://www.ti.com/security

http://www.ti.com/telephony

http://www.ti.com/video

http://www.ti.com/wireless


3

Analog Applications Journal 2Q 2007 www.ti.com/aaj High-Performance Analog Products

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Data AcquisitionConversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Conversion latency can be a problem when working with multiple small-signal, low-frequency sensors ina system. This article compares cycle-latancy behavior of various delta-sigma converters and shows howTI’s zero-latency ADCs are well suited for many multipliexed small-signal applications.

Power ManagementEnhanced-safety, linear Li-ion battery charger with thermal regulation and input overvoltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Using unregulated power sources can easily drive linear Li-ion battery chargers beyond safe thermaloperating limits. The bq2406x chargers offer thermal regulation and input overvoltage protection thatalleviate thermal concerns while maximizing the charge rate and minimizing the charging time.

Current balancing in four-pair, high-power PoE applications . . . . . . . . . . . . . . . . . . . . 11IEEE standards limit the power available to peripherals using two-pair architucture. This articledescribes a current-balancing technique that uses four-pair architecture to achieve up to 50 watts ofinput power to end equipment.

Interface (Data Transmission)Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . 18

USB On-The-Go (OTG) enables connectivity to various USB devices without a PC host. This articleprovides insight to getting the TUSB60xx OTG-capable devices to gluelessly provide a USB interface toTI processors that supports the VLYNQ interface—such as the DaVinci™ family, the DM320, and theOMAP™ family.

Amplifiers: Op AmpsNew zero-drift amplifier has an IQ of 17 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Micropower applications require very small input offset, offset drift, and very low noise. This articleprovides an indepth look at the OPA333—a low-noise, chopper-stabilized, micropower operationalamplifier which operates from a 1.8-V supply with very low quiescent current.

General InterestSpreadsheet modeling tool helps analyze power- and ground-plane voltage drops to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . 29

PCB power- and ground-plane voltage drops can become a real problem when working with very lowcore voltages. This article shows how to use your spreadsheet software to model a PCB layout to predictvoltage drops for various copper thicknesses and temperatures. Using the spreadsheet surface-chartingfunction, a 3D map of the voltage drops can be generated for quick visual analysis.

Index of Articles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

TI Worldwide Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Contents

To view past issues of theAnalog Applications Journal, visit the Web site

www.ti.com/aaj




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Analog Applications Journal is a collection of analog application articlesdesigned to give readers a basic understanding of TI products and to providesimple but practical examples for typical applications. Written not only fordesign engineers but also for engineering managers, technicians, systemdesigners and marketing and sales personnel, the book emphasizes generalapplication concepts over lengthy mathematical analyses.

These applications are not intended as “how-to” instructions for specificcircuits but as examples of how devices could be used to solve specific designrequirements. Readers will find tutorial information as well as practicalengineering solutions on components from the following categories:

• Data Acquisition

• Power Management

• Interface (Data Transmission)

• Amplifiers: Op Amps

• General Interest

Where applicable, readers will also find software routines and programstructures. Finally, Analog Applications Journal includes helpful hints andrules of thumb to guide readers in preparing for their design.

Introduction

Introduction


5

Analog Applications Journal

Texas Instruments Incorporated Data Acquisition

2Q 2007 www.ti.com/aaj High-Performance Analog Products

Conversion latency in delta-sigma converters

Small-signal sensors often generate slow-moving dc signals.For these types of sensors, the delta-sigma (∆Σ) analog-to-digital converter (ADC) eliminates most of the analog inputcircuitry by providing a complete high-resolution, low-noisesolution. Some systems have multiple sensors generatinglow-frequency signals. This situation may require a high-resolution, low-noise ADC with a multiplexer at its input.An example of a multiplexed sensor system is an auto-motive diagnostic application where numerous small-signalsensors monitor temperature, tire pressure, air-bag readi-ness, etc. (see Figure 1). Examples of other sensor-inputmultiplexed systems are found in industrial-control, medical,avionics, and process-control applications. Even though thesensors at the input of the multiplexer in these systemspresent low-frequency (nearly dc) signals, switching fromchannel to channel creates the need for an ADC that iscapable of a high-speed response.

There are two common units of measure that describethe latency of an ADC: cycles and seconds. Cycle latency isthe number of complete data cycles between the conversioninitiation and the availability of the corresponding outputdata. Latency time, measured in seconds, tells the userhow fast fully settled conversions can be performed.

In the system in Figure 1, the multiple-channel ADCmust have high resolution, lownoise, zero-cycle latency, and lowlatency time. (Zero latency or 0-cycle latency is sometimes calledno latency.)

ADC cycle latencyFor ADCs, cycle latency is thenumber of complete data cyclesbetween the initiation of the input-signal conversion and the availabilityof the corresponding output data(see Figure 2). The unit of measurefor this definition of latency is N-cycle latency, where N is a wholenumber. Figure 2 shows the timingdiagrams for a 0-cycle-latency (orzero-latency) ADC and a 4-cycle-latency ADC. In Figure 2(a), with0-cycle latency, the sampling periodof N+0 is initiated. The output dataof N+0 is acquired before the sam-pling period of N+1 is initiated. InFigure 2(b), with 4-cycle latency,the sampling period of N+0 is

By Bonnie C. Baker (Email: [email protected])Senior Applications Engineer

LoadCell

PressureSensor

10 mΩ

ThermistorDigitalOutput

MultichannelADC

Figure 1. Example multiplexed sensor system

DataInvalid

0-Cycle

Laten

cy

N+1 N+3 N+4 N+5 N+6 N+7N–5 N+0 N+2

Analog IN

Data OUT

N+3N+4

N+5 N+6N+7

N+0 N+1 N+2N+0

Single-CycleConversion

Figure 2. Comparison of cycle-latency behavior of two ∆Σ ADCs

(a) 0-cycle-latency ∆Σ ADC

Analog IN

Data OUT

DataInvalid

N–3 N–1 N+0 N+1 N+2 N+3N–5 N–4 N–2

4-Cycle Latency

N+3N+4

N+5 N+6N+7

N+1 N+2N+0

(b) 4-cycle-latency ∆Σ ADC


initiated. The output data of N+0 is presented afterthe completion of four conversion cycles.

Figure 3 shows zero-latency ADC behavior graph-ically. In Figure 3, the input signal is first acquiredat t0. The ∆Σ converter continues to acquire inputsamples through the sampling period and continuallymodulates the signal into a noise-shaped representa-tion. The digital low-pass/decimation filter accumu-lates the noise-shaped signal and generates the outputcode at the end of the t0 period. A ∆Σ converter haszero latency if data is available before a new samplingperiod is initiated. The output code represents theoversampled, filtered-input signal. At t1 the converterinitiates the next sampling period.

The successive approximation register (SAR) ADCsare capable of zero latency as are many ∆Σ converters.The better choice for the application shown inFigure 1 is a high-resolution, zero-latency ∆Σ ADC.Some data sheets for ∆Σ ADCs claim single-cycleconversions. This is another way of saying that aconverter has zero latency.

Texas Instruments (TI) offers numerous multi-plexed, zero-latency ∆Σ ADCs that provide low-noise,high-resolution solutions (see Figure 4). These ∆Σconverters are capable of masking the filter actionand providing a fully settled signal before the end of onecycle. As an example, TI’s 16-channel, 24-bit ADS1258 hasan internal, fifth-order, sinc digital filter followed by a pro-grammable, first-order averaging filter. When the converteris configured in its auto-scan mode, the cycle latency iszero. In the auto-scan mode, the ADS1258 scans throughthe selected channels automatically, with break-before-make switching.

ADC latency timeLatency time is typically viewed as the time required foran ideal step input to converge, within an error margin, toa final digital output value. This error band can be expressedas a predefined percentage of the total output-voltage step.The latency time of a conversion is the time between thebeginning of the signal acquisition and the time when datais available to download from the converter. In contrast tothe cycle-latency specification, the latency time (or settlingtime) is never equal to zero.

Figure 5 compares the latency-time performance of various multiplexed ∆Σ ADCs. The latency time of a zero-latency ∆Σ ADC varies from device to device, dependingon the system clock and the order of the converter’s digitalfilter. A requirement for larger applications is that the multi-plexed ADC must quickly cycle through the channels. Thelatency time for these types of applications can be critical.

Texas Instruments IncorporatedData Acquisition

6


TI ADS1258

Vendor A

Vendor B

42 µs

85 µs

250 µs

0

Latency Time (µs)

200 25050 100 150

Figure 5. Latency-time comparison of ∆Σ ADCs

MSP12xxADS1216/7/8

ADS1224ADS1226

ADS1232ADS1234

ADS1240ADS1241

ADS1242ADS1243

ADS1256ADS1258

( )()

( )()

( )()

( )()

( )()

0

Cycles of Latency

1 2 3 4 5

( ) Optional Modeof Operation

Figure 4. TI’s multiplexed zero-latency ∆Σ ADCs

–0.5

0

0.5

1

–1

C00000

000000

07FFFF

7FFFFF

800000

Single-CycleConversion

Time (seconds)

Time (seconds)

t0

t0

t1

t1

t2

t2

t3

t3

SamplePeriod

AnalogInputs

OutputDataDigital Low-Pass Filter

Decimation Filter

∆ΣModulator

Noise-Shaped Signal

Dig

ita

lO

utp

ut

(Co

de

)A

na

log

Inp

ut

(No

rma

lize

dV

)

Figure 3. Typical input and output of zero-latency ∆Σ ADC


Texas Instruments Incorporated Data Acquisition

7


SCLK

DIN

DOUT

PWDN

START

RESET

CS

DRDY

ADS1258

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN15

LoadCell

10 mΩ

Thermistor

PressureSensor

GPIO(7:0)

DigitalFilter

Oscillator

SPIInterface

Control

24-Bit

ADC∆Σ

16-InputAnalog

MUX

Figure 6. The ADS1258, a 16-channel, zero-latency, 24-bit ∆Σ ADC

When the ADS1258 (Figure 6) is configured in its auto-scan mode (zero latency), the output data is fully settledat the end of each conversion. The minimum latency timein the ADS1258’s auto-scan mode is 42 µs.

It is possible to reduce the throughput time of a zero-latency ∆Σ ADC if the intermediate or masked digital filterresults are available. In this mode, the digital output resultsare not necessarily fully settled. For these devices thethroughput time is always less than the latency time.Reduction of throughput time best suits sensors thatproduce small voltage changes at a slow rate (such astemperature sensors, pressure sensors, or load cells). With these types of sensors it might be advantageous toacquire several conversions and perform post-processingon the data.

When the ADS1258 is configured in its fixed-channelmode, the intermediate results from the fifth-order digitalfilter are available to the user. In the ADS1258 fixed-channel mode, the converter is no longer automaticallycycling from channel to channel, and the output data may

or may not be fully settled. The minimum throughput timeof the ADS1258 in fixed-channel mode is 8 µs (1⁄5 of thefully settled latency time).

ConclusionThe economy and efficiency of using multiplexed ∆Σ ADCsfor applications with multiple sensors must be weighedagainst possible problems caused by ADC conversionlatency and any latency introduced by external processing.The TI ADS1258 offers 16-channel, 24-bit conversionswith low noise and zero latency. The device’s single-cycle,low-latency-time capability provides fully settled data atthe end of each conversion cycle. In auto-scan mode, theADS1258 can complete a conversion for all 16 channels inunder 700 µs. Cycle latency and the total conversion timemust be evaluated for each ADC considered to be sure thedevice will perform as intended.

Related Web sitesdataconverter.ti.com

www.ti.com/sc/device/ADS1258


http://dataconverter.ti.com

http://www.ti.com/sc/device/ADS1258

8


Enhanced-safety, linear Li-ion batterycharger with thermal regulation and input overvoltage protection

The lithium-ion (Li-ion) battery is widely adopted in por-table devices because of its high energy density on both agravimetric and volumetric basis. Due to their simplicity,low cost, and small size, highly integrated linear batterychargers are widely used to charge single-cell Li-ion bat-teries. However, when unregulated adapters are used topower portable systems, it can be a challenge to remove orminimize the heat generated from the linear chargers andto maintain their operation within a safe thermal range.This article describes a newly developed battery chargerwith thermal regulation. This charger has input overvoltageprotection (OVP), which alleviates thermal concerns whilemaximizing the charge rate and minimizing the chargingtime, allowing use of an unregulated adapter.

Battery-charging requirementsThe charge profile widely used for charging Li-ion batteriesconsists of three charging phases: precharge; fast-chargeconstant current (CC); and constant voltage (CV). In theprecharge phase, the battery is charged at a low rate whenthe cell voltage is below 3.0 V. Typically, when the cellvoltage reaches 3.0 V, the charger enters the CC phase.The faster-charge CC is usually limited to stay below thecell’s 1C rating. The cell cycle life decreases with chargerates above 1C because metallic lithium deposited on the

node easily reacts with the electrolyte and is permanentlylost. Finally, the charger enters the CV phase, where itmaintains the peak cell voltage and then terminates charg-ing when the charge current drops to a predefined level.

The cell capacity is a function of the cell voltage—thehigher the voltage, the higher the capacity. However, highercell voltage results in shorter cycle life. For example, charg-ing a cell at 4.3 V can provide 10% more capacity, but cellcycle life may be 50% shorter. On the other hand, if the cellis undercharged at just 40 mV under the optimum voltage,it can have about 8% lower capacity. Therefore, a veryaccurate battery charge voltage is extremely important.

Thermal-regulated battery charger with input OVPFigure 1 shows a low-cost, stand-alone linear batterycharger circuit with thermal regulation and input OVP.The charger simply drops the adapter’s DC voltage downto the battery voltage. The power dissipation in the linearcharger is given by

There is a large difference between the input and batteryvoltages when the charger transitions from precharge tofast-charge mode, where the power dissipation reachesthe maximum. For example, if a 5-V adapter is used to

P V V ICHGR IN BAT CHG= −( ) × .

Texas Instruments IncorporatedPower Management

By Jinrong QianApplications Manager, Battery Management Applications

AdapterVIN

COUT

1 µF

OUT

5

10

9

6

BAT

ISET

TMR

VSS

2

C : 0.47 µF1

IN

8

3

STAT2

Q1

bq24061

VBAT

ICHG

ICHG

VBAT TJ

VREF

200 Ω

System

R : 1.13 kSET Ω

Pack+1

CIN0.47 µF

STAT1

7

4R : 1.5 k3 Ω

R : 1.5 k2 Ω

R : 1.5 k1 Ω

R : 49.9 kTMR Ω

PG

CE

+ + + –

Figure 1. Application circuit with thermal regulationand input OVP


Texas Instruments Incorporated Power Management

9


charge a 1200-mAh Li-ion battery, it has a maximumpower dissipation of 1.8 W with a 1-A charge current anda 3.2-V battery voltage. This power dissipation results inan 85°C temperature rise for a 3 × 3-mm QFN packagewith 47°C/W thermal impedance. The junction temperatureexceeds the maximum allowed operating temperature of125°C at 45°C ambient temperature. It is hard to maintainthe junction temperature within a safe thermal range atthe beginning of the charging. As the battery voltage risesduring the charging, the power dissipation drops. Aftercharging enters the CV mode, the power dissipation dropsfurther as the charge current starts to taper down.

How do we improve the design to keep the chargeroperating in a safe thermal range? The more advancedbattery chargers such as bq2406x and bq2403x have intro-duced a thermal regulation loop to prevent overheating ofthe charger. When the internal chip temperature reaches apredefined temperature threshold—for example, 110°C—any further increase of the IC temperature results inreduction of the charge current. This limits the power dissipation and provides thermal protection to the charger.The maximum power dissipation causing the IC junctiontemperature to reach thermal regulation depends upon thePCB layout, the number of thermal vias, and the ambienttemperature. Figure 2 shows that after 1.2 seconds thethermal loop reduces the effective charging current from1.2 A to 600 mA within 2 seconds.

Thermal regulation usually happens at the early stage ofthe fast charge, but if it is active during the CV mode, thecharging current could prematurely reach the charge termi-nation threshold. To prevent this false charge termination,the battery charge-termination function is disabled when-ever the thermal regulation loop is active. In addition, theeffective charge current is reduced, which increases thebattery charging time and which, if the charge safety timerhad a fixed setting, could terminate charging early. Thebq2406x employs a dynamic safety-timer control circuitthat effectively extends the safety time during thermalregulation and minimizes the chance of a safety-timerfault. Figure 3 shows that the safety-timer response isinversely proportional to the effective charge current inthermal-regulation mode.

When the battery-charging function is enabled, theinternal circuit generates a current proportional to thereal charging current set by the ISET pin. The voltagegenerated across resistor RSET reflects the charge current. This voltage can be monitored by the host forcharge-current information.

There are several types of adapters used to charge Li-ionbatteries. Less expensive adapters may not have wellregulated output and have higher output voltages underno load than at the normal load. In addition, during thebattery hot plug-in, the input voltage to the charger couldreach as high as two times that of the adapter voltage dueto resonance between the cable inductance and the input

0

1

2

3

4

5

6

7

0 0.50 1 1.50 2 2.50 3

Time, t (s)

Vo

ltag

e( V

)

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

Batt

ery

Cu

rren

t( A

)

VISET

IBAT

VIN

Figure 2. Charge-current waveform underthermal regulation

00

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0.5 1 1.5 2 2.5 3

Time, t (s)

Batt

ery

Cu

rren

t( A

)

0

2

4

6

8

10

12

Safe

tyT

imer,

t(h

)C

HG

IBAT

Safety Timer

Figure 3. Dynamic safety timer inthermal regulation

capacitor of the battery charger. To increase safety whenthe input voltage is above the predefined threshold, theinput OVP implemented in bq2406x chargers does notallow charging.

The LDO mode (with the TMR pin open) disables thecharge-termination circuit and the battery-detection routineand holds the safety-timer clock in reset. This mode isoften used for operation without a battery or in produc-tion testing.



10


Adapter VIN

COUT

1 µF

OUT

5

10

9

6

BAT

ISET

TS

VSS

C1

0.47 µF

IN

I =750 mATempRange: 0˚ to 45˚CSafetyTimer:5 hours

CHG

2

3

STAT2

Q1

bq24060

VBAT

ICHG

200 Ω

System

5

VIN

10

R

15 k4

Ω C10 nF

2

9

6

8

Pack+1

CIN : 0.47 µF

STAT1

7

4R : 1.5 k3 Ω

R : 1.5 k2 Ω

R : 1.5 k1 Ω

R49.9 k

TMR

Ω

PG

TMR

Controller

RT2

33.2 kΩRSET

1.13 kΩ

RT1

10 kΩ

Figure 4. Power-path-management battery charger

Many applications require powering the system whilecharging the battery simultaneously. When the system isdirectly connected to the battery-charge output as shownin Figure 1, interaction between the system and chargermay result in a false charge termination caused by thesafety timer. Figure 4 shows a typical application circuitthat eliminates such issues. There are two independentpower paths, one to charge the battery and one to powerthe system. When the AC adapter is not available, the battery discharge MOSFET is turned on after a time delayset by R4 and C2 so that the battery will provide power tothe system.

SummaryThe linear battery charger with thermal regulation can significantly improve the thermal design and safety. Withinput OVP, it allows only authorized adapters to chargethe battery, improving system safety.

Related Web sitespower.ti.com

www.ti.com/sc/device/bq24060

www.ti.com/sc/device/bq24061


http://power.ti.com

http://www.ti.com/sc/device/bq24060

http://www.ti.com/sc/device/bq24061

Review of PoE two-pair/four-pair architecturesAn end-to-end PoE solution typically comprises a powersource, referred to as “power sourcing equipment” (PSE),and end equipment, referred to as the “powered device”(PD). The PSE may be standalone or embedded in arouter or switch. Most Ethernet cable used today isCategory 5E (CAT5E) cable composed of four unshieldedtwisted pairs of copper.

Figure 1 shows the possible architectures that can beused to deliver power over CAT5E cable. The architecturein Figure 1a delivers power to the PD from the PSE in asingle loop over two pairs of the CAT5E cable. The IEEE

11


Current balancing in four-pair, high-powerPoE applications

IntroductionPower-over-Ethernet (PoE) parameters are specified byIEEE 802.3-2005 clause 33, which defines both the allow-able architectures and the maximum deliverable power fora PoE system.1 The present standard mandates a two-pairarchitecture allowing a maximum of 12.95 W at the end ofthe cable. As end equipment becomes more complex, itrequires more power and architectures more flexible thanthe IEEE standard allows. This article describes a uniquecurrent-balancing technique that uses a four-pair architec-ture to deliver up to 50-W to the end equipment.


By Steven R. TomSystems Engineer, Power Interface Products


48 V

PSE

Switch or Hub

RJ45 RJ45

PD

DC/DCConverter

<100 m ofCAT5E Cable

+–

11

22

33

66

44

55

77

88

Figure 1. Two possible architectures for power delivery to the PD

48 V

PSE

Switch or Hub

RJ45 RJ45

PD

DC/DCConverter

<100 m ofCAT5E Cable

+–

11

22

33

66

44

55

77

88

PD

(a) Two-pair architecture

(b) Four-pair architecture



12


standard specifies that power may be delivered in a singleloop over either of the two pairs but not over all four pairssimultaneously. Using two current loops over all four pairs,the architecture in Figure 1b increases the available powerdelivered to the input of the PD. The main advantage ofthe four-pair architecture is the increased number of con-ductors which decreases power loss and increases totalpower to the end equipment. The main disadvantages arethe added cost and the increased complexity needed toensure that the current is balanced between the twocurrent loops.

In the four-pair architecture, both current loops feed asingle DC/DC converter. If the impedances of each loopwere identical, current balancing would be unnecessaryand each loop would provide half of the needed input cur-rent to the DC/DC converter. However, mismatches in thewires, connectors, and components will naturally causeone loop to carry more current than the other. To ensure

reliability, the series components in each current loopmust be designed to handle the worst-case imbalance whilemaintaining data transmission. A larger imbalance impliesan oversized (and thus more costly) design. Maximumpower delivery can be obtained by balancing the currentbetween the line pairs so that each path operates justbelow its current limit. The following design example andanalysis show how the worst-case imbalance can be deter-mined and minimized.

Design example with current-booster circuitIn a four-pair architecture, the detection and classificationfunctions of the PD must be performed on each two-paircurrent loop, which necessitates the need for two PD controllers. In the design example that follows, twoTPS2376-H controllers are used as the PD input source tothe DC/DC power supply2 (see Figure 2). The DC/DCpower supply uses a UCC3809-2 in a single-switch flyback

Lines FromEthernet

Transformers

PD Interface 1

1

8

5

2

2

7

9

3

3+

6

4

4 5

D2

Q2 R152.2 Ω

R192.0 Ω

Q1

Path 1

Total ReturnCurrent

AC

AC

D6

D5

C170.1 µF

C747 µF

R48

909 kΩ

R11

25.5 kΩ

R13

357 kΩR14

4.42 kΩ

R49

61.9 kΩ

+

–

UVL01

UVL01

VOUT

U1TPS2376DDA-H

ILIM VDD

UVLO

PG

RTN

CLASS

DET

VSS

PwPd

U3DC/DC Converter

VCC VOUT

5 V, 8 A

PGNDGND

1 8

2 7

9

3 6

4 5

D9

Q9 R322.2 Ω

R332.0 Ω

Q8

Path 3

Path 4

Path 2

AC

AC

D13

D12

C240.1 µF

R50

909 kΩ

R25

25.5 kΩ

R30

357 kΩR31

4.42 kΩ

R51

61.9 kΩ

+

–

UVL02

UVL02

U2TPS2376DDA-H

ILIM VDD

UVLO

PG

RTN

CLASS

DET

VSS

PwPd

CAT5E_Wires_1_2

CAT5E_Wires_3_6

CAT5E_Wires_7_8

CAT5E_Wires_4_5

Figure 2. Design example of four-pair architecture with current-booster circuit



13


topology to provide an isolated 5 V at 8 A to the load.Table 1 shows the predetermined design specifications

used for this design example. It is assumed that an avail-able PSE will supply a regulated voltage between 51 and57 V that is capable of sourcing up to 800 mA for eachcurrent loop consisting of two pairs of the CAT5E cable. Areasonable assumption for the loop impedance of each two-pair loop (maximum length of 100 m) is 12.5 Ω. TheCAT5E cable will connect to the PD interface and input tothe DC/DC converter that will provide an isolated 5 V at 8A to the load. For simplicity and emphasis on the PDinterface, the DC/DC power supply is shown in Figure 2 asa simple black box.

Assuming that the DC/DC converter is ~85% efficient,approximately 47 W of input power is needed. Dependingon the CAT5E cable length and the PSE voltage, an inputcurrent between 0.825 and 1.2 A is required to meet theinput-power specification.

The current limit of the TPS2376-H is listed in Table 1because it is imperative that the current in either of thetwo current loops not exceed this value during operation toavoid unwanted shutdown. Because the minimum currentlimit of the TPS2376-H is 625 mA, the current-booster circuitry in Figure 3 was introduced to gain the full poten-tial of the allowable 800 mA of input current per two-pairloop. In reality, the current is not boosted—it is merelyshunted around the TPS2376-H. Figure 3 shows how thecurrent-booster circuit works for one of the current loops.As the return current into pin 5 (RTN) on the TPS2376-Hincreases, the voltage drop across R15 increases, loweringthe voltage between base and emitter sufficiently to turn ontransistor Q1. Current through R15 will turn on Q1 whenVR15 > 0.7 V. This allows Q1 to conduct and shunt a portionof the return current around the TPS2376-H. Q2 providesprotection for Q1 during short-circuit and transient condi-tions by clamping the base of Q1 to its collector and forcingit off. Q2 will turn on when VR19 > 0.7 V, shunting some ofthe Q1 base current and eventually turning it off if thecurrent continues to increase. For a more detailed expla-nation of this circuit, please see Reference 3.

MIN TYP MAXPSE Voltage (V) 51 — 57

Impedance per Two Pairs (Ω) — 12.5 —

Input Current per Two Pairs (A) — — 0.800

VOUT (V) 4.95 5 5.05

IOUT (A) — — 8.0

DC/DC Output Power to Load (W) — — 40

DC/DC Input Power (W) — — 47

DC/DC Efficiency (%) — 85 —

DC/DC Input Current (A) 0.825 — 1.200

Current Limit (A) (TPS2376-H) 0.625 0.765 0.900

1 8

2 7

9

3 6

4 5

D2

Q2 R152.2 Ω

R192.0 Ω

Q1

Path 1

Path 2

UVL01

U1TPS2376DDA-H

ILIM VDD

UVLO

PG

RTN

CLASS

DET

VSS

PwPd

Figure 3. Current-booster circuit for onecurrent loop

Table 1. Design specifications



14


Modeling the four-pair architecture within PSPICETo ensure that the design will current share appropriately,it is necessary to model the four-pair architecture within asimulation tool such as PSPICE. The key elements that needto be modeled are the sources of impedance in series witheach current loop; i.e., the diode bridge, the CAT5E cableresistance, and the series resistances of the TPS2376-Hpass FETs and booster circuitry. Table 2 correlates theactual schematic in Figure 2 with the PSPICE simulationschematic in Figure 4.

The simulation models the PSE as an ideal DC voltagesource, the DC/DC power supply as an ideal DC currentsource, and the CAT5E cable and PD interface as the fourcurrent paths. The color-coded paths in Figure 4 correspondto those shown in Figure 2. Modeling the PSE as an idealvoltage source and the DC/DC power supply as an ideal DCcurrent source are reasonable assumptions that simplifythe simulation significantly and allow the analysis to focuson the current balancing of the CAT5E and PD circuitry.

As stated earlier, in an ideal circuit the current would beequal in each current path because each path contains thesame components. However, imbalances do arise becauseof variations in diode forward voltage drops, cable resist-ance, and pass FET on resistances. PSPICE allows forexamination of the ideal case where matched componentsare used and the current in each current loop is balanced.The simulation is made by sweeping the current in the DCcurrent source, I_DCDC, and recording the current in

each of the two current loops and the power delivered tothe DC current source. The power delivered to the DCcurrent source represents the input power to the DC/DCconverter. (If the efficiency of the DC/DC power supply isknown, it can be multiplied by the input power to calcu-late the actual power to the load.) Within each currentloop, it is important to make sure that the current throughthe pass FET of each TPS2376-H device is less than the625-mA current-limit threshold and that the total currentin either current loop does not exceed 800 mA.

A second variable that must be considered is the lengthof the CAT5E cable. The IEEE standard allows for a

D6_V1

0.65 V

D2_R

0.25 Ω

D9_R

0.25 Ω

D6_R1

0.3 Ω+ +– –

0 V

Vpse

51 V

+

–

R12

6.25 Ω

D9_V

0.4 V

D2_V

0.4 V

I_DCDC1.1 A

6.25 Ω

D13_V1

0.65 V

D13_R1

0.3 Ω+ +– –

R45

6.25 Ω

D6_V2

0.65 V

D6_R2

0.3 Ω+–

R36

D13_V2

0.65 V

D13_R2

0.3 Ω+–

R78

6.25 Ω

0.58 Ω 2.2 Ω

2.0 ΩQ1

Q2

R15U1_RDSon

R19

0.58 Ω 2.2 Ω

2.0 ΩQ8

Q9

R32U2_RDSon

R33

+

–

TotalReturnCurrent

DC/DCConverter

PD Interface

Path 2

Path 3

Path 4

Path 1

Figure 4. Balanced PSPICE circuit for load-share simulation

ACTUAL SCHEMATIC PSPICE SIMULATION (Figure 2) SCHEMATIC (Figure 4)

U1 U1_RDSon (pass FET on resistance)

U2 U2_RDSon (pass FET on resistance)

D6 D6_V1, D6_V2, D6_R1, D6_R2D13 D13_V1, D13_V2, D13_R1, D13_R2D2 D2_V, D2_RD9 D9_V, D9_R

CAT5E cable resistance R12, R45, R36, R78PSE input voltage Vpse

DC/DC power supply I_DCDCQ1, Q2, Q8, Q9, R15, R19, R32, R33 Q1, Q2, Q8, Q9, R15, R19, R32, R33

Table 2. Modeling of four-pair architecture



15


maximum of 100 m of Ethernet cable between the PD andPSE.1 Figure 5 shows the simulation results for the cornerareas of 100 m and 1 m of cable length when the modelcable resistances (R12, R45, R36, R78) are modified. Allsimulations are done at the minimum PSE voltage of 51 Vbecause input current is highest at this condition.

The simulation results confirm that when matched, thecurrent loops will load share identically as Path 1 overlapsPath 3 and Path 2 overlaps Path 4. As input power increasesabove 25 W, the current-booster circuitry begins turning onand a portion of the current in each current loop is shuntedaround the TPS2376-H. The largest current handled byeither TPS2376-H device is ~465 mA when the inputpower to the DC/DC power supply is 48 W and 100 m ofcable connects the PD to the PSE. The largest current ineither of the two-pair current loops is 599 mA (465 mA +134 mA). This simulation result is acceptable because themaximum TPS2376-H current is less than the 625-mA current limit and the maximum current in either of thetwo-pair current loops is less than 800 mA.

Understanding sources of loop-impedancemismatchTo ensure reliable performance, it is important to under-stand the sources of loop-impedance mismatch so thatworst-case imbalances can be entered into the simulationand analyzed. The simulation circuit in Figure 6 takes intoaccount maximum variations in diode forward voltage, 1%resistor tolerances, and maximum pass FET on-resistancetolerances. Also, the maximum cable length resistance tolerance of 3% was used in accordance with the IEEEstandard.

0

100

200

300

400

500

600

Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V

Load-Sharing Current

Distribution: Balanced

Cable Length: 100 meters Paths 1 and 3

Paths 2 and 4

0 5 10 15 20 25 30 35 40 45 50Input Power to DC/DC Converter (W)

Figure 5. PSPICE simulation of balancedcurrent sharing

(a) With 100-m cable

0

100

200

300

400

500

600

Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V



Cable Length: 1 meter

Paths 1 and 3

Paths 2 and 4

Input Power to DC/DC Converter (W)

0 5 10 15 20 25 30 35 40 45 50

D6_V1

0.65 V

D2_R

0.2 Ω

D9_R

0.25 Ω

D6_R1

0.3 Ω+ +– –

0 V

Vpse

51 V

+

–

R12

6.25 Ω

D9_V

0.4 V

D2_V

0.25 V

I_DCDC1.1 A

6.25 Ω

D13_V1

1.0 V

D13_R1

0.3 Ω+ +– –

R45

6.44 Ω

D6_V2

0.65 V

D6_R2

0.3 Ω+–

R36

D13_V2

1.0 V

D13_R2

0.3 Ω+–

R78

6.44 Ω

0.58 Ω 2.178 Ω

1.98 ΩQ1

Q2

R15U1_RDSon

R19

1.0 Ω 2.222 Ω

2.02 ΩQ8

Q9

R32U2_RDSon

R33

+

–

TotalReturnCurrent

DC/DCConverter

PD Interface

Path 2

Path 3

Path 4

Path 1

Figure 6. Unbalanced PSPICE circuit for load-share simulation

(b) With 1-m cable



16


The values were adjusted so that all impedance mis-matches were in one current loop, allowing for the largestimbalance. The four-pair architecture simulation previouslydiscussed was run a second time to determine the extentof current imbalance in each current pair.

Figure 7 shows that the largest current through either ofthe TPS2376-H devices is 488 mA with a 100-m cable and498 mA with a 1-m cable. The largest current available (inthis example, Path 1 plus Path 2) is 640 mA with a 100-mcable and 660 mA with a 1-m cable. Because the worst-case current imbalance exceeds neither 625 mA throughthe TPS2376-H nor 800 mA in one current loop, thedesign remains within the original design specification.

Board-level resultsTo verify that the simulations are accurate, an evaluationboard was built and tested. Figure 8 shows the current ineach of the current loops when measured in an ideal labsetting at 25°C ambient temperature. These board-levelresults demonstrate a current imbalance through eachTPS2376-H of only 10 mA (2.1%) with a 100-m cable and1 mA (0.2%) with a 1-m cable.

To emulate worst-case conditions, the evaluation boardwas retested with a diode and resistor in series with thereturn path of the R78 current loop (Paths 3 and 4). Theforward voltage drop of the diode (0.7 V) and an additional0.5-Ω resistance were added to compensate for worst-case

0

100

200

300

400

500

600

Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V


Distribution: Unbalanced

Cable Length: 100 meters


0 5 10 15 20 25 30 35 40 45 50

Figure 7. PSPICE simulation of unbalancedcurrent sharing


0

100

200

300

400

500

600


Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V




0 10 20 30 40 50 60

(b) With 1-m cable

0

100

200

300

400

500

Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V





0 5 10 15 20 25 30 35 40 45 50

Figure 8. Board-level test results of balancedcurrent sharing


0

100

200

300

400

500

600


Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V




0 5 10 15 20 25 30 35 40 45 50

(b) With 1-m cable



17


diode forward voltage variations and system resistance tolerances. This permitted a reasonable board-level test tobe conducted to measure actual current-loop imbalances.

Figure 9 shows that the largest current through either ofthe TPS2376-H devices is 488 mA with a 100-m cable and484 mA with a 1-m cable. The largest current available (inthis example, Path 1 plus Path 2) is 648 mA with a 100-mcable and 640 mA with a 1-m cable. Because the worst-case current imbalance exceeds neither 625 mA throughthe TPS2376-H nor 800 mA in one current loop, thedesign remains within the original design specification.

ConclusionOverall, both simulation and board-level results confirmthat the current-booster circuit will meet the initial designrequirements for current balancing by keeping the returncurrent through each TPS2376-H under its minimum current limit and under the maximum current allowable inthe CAT5E Ethernet cable. The addition of the current-booster circuit improves the current balancing betweenthe two current loops so that the wire, connector, andcomponent tolerances do not cause the design to fall outof the design specifications.

ReferencesFor more information related to this article, you can down-load an Acrobat Reader file at www-s.ti.com/sc/techlit/litnumber and replace “litnumber” with the TI Lit. # forthe materials listed below.

Document Title TI Lit. #

1. IEEE 802.3 standard,http://standards.ieee.org/getieee802/802.3.html —

2. “IEEE 802.3af PoE High Power PD Controller,”TPS2376-H Datasheet . . . . . . . . . . . . . . . . . . . . .slvs646

3. Martin Patoka, “High-Power PoE PD UsingTPS2375/77-1,” Application Report . . . . . . . . . .slva225

Related Web sitespower.ti.com

www.ti.com/sc/device/TPS2376-H

www.ti.com/sc/device/UCC3809-2

0

100

200

300

400

500

600

Cu

rren

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V





0 5 10 15 20 25 30 35 40 45 50

Figure 9. Board-level test results of unbalancedcurrent sharing


0

100

200

300

400

500

600C

urr

en

tD

istr

ibu

tio

n(m

A)

Path 1

Path 3

Path 2

Path 4

PSE Voltage: 51 V





0 5 10 15 20 25 30 35 40 45 50

(b) With 1-m cable


http://power.ti.com

http://www.ti.com/sc/device/TPS2376-H

http://www.ti.com/sc/device/UCC3809-2

18


Enabling high-speed USB OTG functionality on TI DSPs

High-speed USB On-The-Go (OTG) enables connectivitybetween portable consumer electronic devices over theindustry’s most popular peripheral interface, USB. Currently,USB devices require a PC host—laptop or desktop—totransfer data. High-speed USB OTG removes the need tofind a bulky PC host to transfer pictures, music, and datato/from a cell phone, digital camera, MP3 player, memorystick, etc. Power is not much of an issue with today’s PChost-centric USB, but is of increasing concern as portabledevices take on more functionality and the demand forlonger battery life increases. The problem of USB directconnection and power-management complexities is solvedwith the new USB 2.0 high-speed OTG controllers andpower-management devices from Texas Instruments (TI).These devices allow developers to add full high-speedOTG capability to their platforms in small-form-factor, low-power designs. TI’s OTG devices are available with amuxed NOR-flash or VLYNQ host interface for easy con-nectivity to TI’s OMAP processors and many other DSPs.

What is USB OTG?The terms USB 1.1, USB 2.0, USB OTG, WUSB, and OTGare all in common use today. In many cases they have created confusion among engineers and end users. Theoriginal USB 1.0 specification was released in January1996. It defined two speeds for devices, low speed (LS) at1.5 Mbps and full speed (FS) at 12 Mbps. The specificationwas revised in July 1998 and released as USB 1.1 with majorclarifications/updates. In April 2000, the specificationunderwent a major revision and was released as USB 2.0,the current version that fully superseded USB 1.1. Thebeauty of USB 2.0 is that it maintains full backwards com-patibility with USB 1.1 devices. However, it adds a muchneeded third speed node, high speed at 480 Mbps, whilekeeping support for both low speed and full speed. In July2003, the USB OTG addendum was released, defining anew class of devices for portable, battery-powered prod-ucts with limited host capabilities. Finally, in May 2005,the Wireless USB (WUSB) specification was released.

USB OTG is an addendum to the USB 2.0 specificationthat defines a new class of devices that extends the func-tionality of a peripheral product to include limited hostcapabilities. As the name implies, the original target of thespecification was consumer portable devices with whichend users may have wanted to share data when a computerwas not available. Usage examples included sharing contactinformation between two PDAs or cell phones, sharing pictures from one digital still camera or camera phone withanother, or printing directly from a digital still camera or

PDA. Like standard USB, OTG is a point-to-point, host-centric bus and is not intended as a peer-to-peer network-ing connection. An OTG product must act as a standardperipheral when connected to a standard USB host suchas a PC. The OTG addendum mainly addresses how adevice must act when it is in host mode.

Just like a standard USB host port, an OTG host mustsupply power; but the required supply current is limited to8 mA. Unlike a standard USB host in a PC, an OTG devicemay not have a simple way to add drivers for “unrecognized”devices. Therefore, an OTG device must supply what iscalled a Targeted Peripheral List (TPL), which allowsdevice manufacturers to specify exactly what peripheralsthey will support. The specification also mandates messag-ing that will communicate to the end user that an unsup-ported device has been plugged in and will not work. Thismessaging can be as simple as an LED or as complex as atext display.

Since the target end products were primarily smallportable consumer electronics, a standard USB connectorwas too large. Therefore the USB Implementers Forumintroduced new mini and micro connectors. The mini-Bconnector has been in common use as a small-form-factorreceptacle on many USB peripherals. The micro-AB recep-tacle is what a dual-role OTG device must use. This con-nector accepts either a micro-A plug or a micro-B plug.The orientation of the cable determines which device in anOTG connection acts as the host (A side) and which actsas the peripheral (B side), as shown in Figure 1. The newconnector has an additional pin (ID) that is left open onthe micro-B plug and is grounded in the micro-A plug todetermine initial roles.

Although cable orientation determines which role, hostor peripheral, each OTG device will initially assume atconnection, the roles can be reversed via a dynamicswitching method called Host Negotiation Protocol (HNP).

Texas Instruments IncorporatedInterface (Data Transmission)

By Dan HarmonProduct Line Marketing Manager, Digital Interface Products

D+

D–

GND

IDIDX

VBus

Micro-AB Micro-AB

B Device A Device

Micro-B Micro-A

Figure 1. Cable orientation determinesinitial state


Texas Instruments Incorporated Interface (Data Transmission)

19


Why switch roles? The need for this can be understood ifwe look at Figure 2 and consider that every OTG devicemust include a TPL. The device on the left has the printeron its TPL, but it is not on the printer’s TPL. If the userplugs in the cable backwards as shown in Figure 2, thencommunication between the two devices will not be possi-ble without reversing the roles. HNP allows the roles to bereversed silently and automatically, thus enabling the com-munication and enhancing the end-user experience byeliminating the need to disconnect the cable and reverse it.

Session Request Protocol (SRP) is a method for turningbus power off/on at the discretion of the host device tosave power when communication is not needed. Many ofthe target devices for OTG are battery-powered. Extendingbattery life is of utmost importance to both the manufac-turer and the end user. With this in mind, the A device (asindicated by cable orientation) in an OTG connection can

power off the bus and go into a sleep mode, extendingbattery life. This also allows the B device to go to sleep ifit so desires. However, if the end user desires the commu-nication to start up again and initiates this request on theB device, SRP allows the B device to request the A deviceto turn on VBus power and start a session. An OTG sessionis defined as the time during which the A device is furnish-ing VBus power. To wake up the A device, the B devicepulses first the D+ wire and then the VBus wire. The ADevice, which can respond to either pulsing, detects thepulse, causing it to switch on VBus and start a session.

SRP is more complex than this simple illustration. The Bdevice, for example, must first measure VBus to ensurethat a session is not in progress. It must also be able to differentiate between a classic PC or an OTG device at theother end of the cable. It does this by delivering measuredamounts of current to the VBus wire and noting theresulting voltage.

TUSB60xx: The family of high-speed, OTG-interface-solution devicesThis family of devices enables application processors(DSPs, OMAP™, and MCUs) that do not have integratedUSB cores to function as either a USB 2.0 high-speed periph-eral, an embedded USB 2.0 high-speed host controller, or afull USB 2.0 high-speed OTG device. The TUSB60xxdevices serve as bridges between a USB 2.0 high-speedbus and a local processor host interface. Figure 3 shows atypical system implementation. The TUSB60xx family is

Printer

Micro-AB Micro-B Micro-A Micro-AB

PrinterDriver

Figure 2. HNP example

USBConnector

VBus 1.5 V

RSTn

SLEEP

3.3V_SWEN

ExtInt/GPIO

ApplicationProcessor

Main SystemPower Management

VLYNQ/NOR

System Wakeup

1.5V_SWEN

CP EN_

3.3 V VBus IDD+D–

VCC

VCC

EN3 CLKINEN2 CLKIN GPIO

VbatSysRefClk

1.8 V 1.8 V

PGOOD

TPS65030 TUSB60xxSLEEP(USB OTG Power

Management) SW_EN2

SW_EN1 INT

EN1

VOUT2 VOUT3

ExternalMemory/Devices

Figure 3. TUSB60xx typical system implementation


Texas Instruments IncorporatedInterface (Data Transmission)

20


fully compliant with high-speed USB OTG. These devicescome in a space-saving 5 × 5-mm MicroStar Junior™ BGApackage and support an ultralow-power idle mode thatconsumes less than 100 µA. Both of these features arecritical to small portable consumer devices that featureUSB OTG. An application processor is required to supportsoftware needs. These include the operating system forhost mode, the drivers for the TPL devices when they arein OTG host mode, and the application functionality whenthe TPL devices are in peripheral mode. A summary of theTUSB60xx family’s features and benefits is given in Table 1.

The TPS65030 is a companion power-management deviceto the TUSB60xx devices. In addition to providing all ofthe power requirements of the TUSB60xx, it can provide 5 V at 100 mA on the VBus line when a TUSB60xx deviceis in OTG host mode.

The first two members of the TUSB60xx family are theTUSB6010B and the TUSB6020. The only differencebetween the two devices is the external processor interface.

The TUSB6010B (Figure 4) features a 16-bit muxedNOR-flash interface that supports both synchronous andasynchronous transfers. The TUSB6010B supports singleand burst read/write access with a programmable burst sizeof up to 16 half words. It can also support 6 external direct-memory-access (DMA) requests. The TUSB6010B willgluelessly interface to the OMAP1710 and the OMAP2420processors. When the device is used with the OMAP2420with the GPMC running at 55 MHz, the throughput mea-sures a sustained 250-Mbps bulk input and bulk outputwith DMA. When the TUSB6010B is connected to theOMAP1710 with the external memory interface running at55 MHz, the throughput measures a sustained 250-Mbps

Features Benefits

• USB 2.0 high-speed, OTG-compliant device • Certified compliance and interoperability

• Multiple external processor interface options • Flexible architectures to interface to multiple processors

• Ultralow-power (<100-µA) idle mode; small • Designed to meet the critical demands of portable, form factor = 5 x 5-mm MicroStar Junior™ BGA battery-powered target devices

Table 1. TUSB60xx family

VBUSPMaster and Slave

32/16 Bitsat sys_clk

8 Bitsat 60MHz

CentralResource

Switch

InterruptController

DMAController

3.3 V 1.5 V

clk60

sys_clk

Digital CorePower

Distribution

I/O PowerDistribution

Power/Reset/ClockManagement

(PRCM)

GPIO

3.3 V 1.5 V

USB 2.0PHY Macro

OTG Analog PLL UT

MI+

Le

ve

l3

VBUSPSlave

32 Bits atsys_clk

VBUSP2VBUSSlave Bridge

USB 2.0 Dual-Role OTG

Controller IP Core

USB EP Buffer RAM(16K x 8)

INT

CLK

ADVn

SCSn

QEn

ACSn

WEn

AddData [15:0]

RDY

DMAReg[5:0]

NOR/FlashInterface(Ext HostInterface)

1.8 V

1.5 V

GPIO

5-V VBus

ID

DPVDM

XI/CLKIN

RSTn

SLEEP

32 Bits at sys_clk

DFT andDebug

I/OController

VBUSPMaster 32 Bits

at sys_clk

clk120

Figure 4. TUSB6010B block diagram


Texas Instruments Incorporated Interface (Data Transmission)

21


bulk output with synchronous DMA and a sustained 100-Mbps bulk input with asynchronous DMA.

The TUSB6020 (Figure 5) features a VLYNQ interface,which is a high-speed, low-pin-count, point-to-point serialspecification developed by TI. The TUSB6020 features a10-pin interface supporting 4 receive lines and 4 transmitlines that run at 150 MHz. It works as a memory-mappedmaster/slave interface with a multichannel DMA controller.The integrated list processor is capable of parsing CPPI3.0-compliant buffer descriptors. The TUSB6020 will glue-lessly interface to any TI processor that supports a VLYNQinterface. These processors include (but are not limited to)

the DaVinci™ family, the DM320, and the OMAP5912.Utilizing an 8-pin VLYNQ interface running at 125 MHz,the TUSB6020 will enable a sustained 267-Mbps bulkinput and bulk output.

Related Web sitesinterface.ti.com

www.ti.com/davinci

www.ti.com/sc/device/partnumber

Replace partnumber with OMAP5912, TUSB6020, orTPS65030

VBUSFMaster and Slave

32/16 Bitsat sys_clk

8 Bitsat 60MHz

CentralResource

Switch

InterruptController

3.3 V 1.5 V

clk60

sys_clk

Digital CorePower

Distribution

I/O PowerDistribution

Power/Reset/ClockManagement

(PRCM)

GPIO

3.3 V 1.5 V

USB 2.0PHY Macro

OTG Analog PLL UT

MI+

Le

ve

l3

VBUSPSlave

32 Bits atsys_clk

VBUSP2VBUSSlave Bridge

VBUSMaster and Slave

32 Bits atsys_clkUSB 2.0 Dual-

Role OTGController IP Core

USB EP BufferRAM (16K x 8)

INT

VLYNQ_CLK

VLYNQ_CRUN

VLYNQ_TX [3:0]

VLYNQ_RXD[3:0]

VLYNQInterface(Ext HostInterface)

1.8 V

1.5 V

GPIO

5-V VBus

ID

DPVDM

XI/CLKIN

RSTn

SLEEP

32 Bits at sys_clk

DFT andDebug

I/OController

Figure 5. TUSB6020 block diagram


http://interface.ti.com

http://www.ti.com/davinci

http://www.ti.com/sc/device/OMAP5912

http://www.ti.com/sc/device/TUSB6020

http://www.ti.com/sc/device/TPS65030

22


New zero-drift amplifier has an IQ of 17 µA

Micropower applications require not only a verysmall offset and offset drift but also very lownoise. Such applications include instrumentationfront ends in biomedical electronics, condition-ing stages in CO2 detectors, and electronic sen-sor interfaces in precision metrology equipment.A front-end, low-noise amplifier combined withsignal-conditioning circuits and a sensor forms amicrosystem that often has to either be portableor stand alone and is therefore battery-powered.Hence, the power consumption has to be small.It is therefore crucial to eliminate the 1/f (flicker)noise and to reduce the overall noise down tothe fundamental thermal noise, which is mainlydetermined by the allowable current consump-tion of the input stage.

While an auto-zero amplifier (AZA) removesits offset and 1/f noise at the cost of a raisedwhite-noise level in the baseband, a chopper-stabilized amplifier reduces its baseband noiseto the initial white-noise level but generateslarge output ripple instead. Because the input-stage noise is inversely proportional to its quies-cent current, e2

n ≈ 1/IQ, an AZA often requires asignificant increase in IQ to achieve the desirednoise levels after noise folding. Since thisincrease counteracts the requirements of a micro-power amplifier, it is desirable to use a chopper-stabilized amplifier in micropower applicationsand to find some way to filter the output ripple.

This article describes a new, micropower, low-noise, chopper-stabilized operational amplifier,the OPA333, which operates from a 1.8-V sup-ply, requiring a quiescent current of only 17 µA.

OverviewThe OPA333 consists of a high-precision path(gm1, gm2, and gm3) in parallel with a widebandpath (gm4 and gm3) (see Figure 1). The preci-sion path ensures a high open-loop gain, AOL, of130 dB, while the wideband path provides a350-kHz gain bandwidth at a phase margin of60° (Figure 2). An internal, patent-pendingnotch filter removes chopper noise by a factorof more than 500, yielding a voltage-noise spec-tral density of 55 nV/√Hz

–––across a 20-kHz band-

width (Figure 3).

Texas Instruments IncorporatedAmplifiers: Op Amps

By Thomas KugelstadtSenior Systems Engineer, Industrial Systems

10

120

100

80

60

40

20

0

–20

Ph

as

e(°

)

250

200

150

100

50

0

–50

–100100 k10 k1 k100

Frequency (Hz)

Op

en

-Lo

op

Ga

in,A

( dB

)O

L

1 M

Phase

Gain

Figure 2. Open-loop gain and phase versus frequency

VIN

C2

C1Notch Filter

Chopped Input Stage

VOUT–g

m3

+gm2

+gm4

+gm1

OSC

Figure 1. Internal block diagram

Current Noise

Voltage Noise

Continues withno 1/f noise

1

1000

100

10

1000

100

1010 k1 k10010

Frequency (Hz)

Vo

lta

ge

No

ise

(nV

/H

z)

Cu

rre

nt

No

ise

( f/

Hz)

A

Figure 3. Noise densities versus frequency


Texas Instruments Incorporated Amplifiers: Op Amps

23


With typical values for offset and drift of VOS = 2 µV anddVOS/dT = 20 nV/°C, respectively, the OPA333 also gener-ates only 1.1 µVpp of instantaneous noise in the 0.01- to10-Hz band. The device offers rail-to-rail input and outputand is available in SC70 and SOT23 packaging. Operationis specified from –40°C to 125°C.

OPA333 design rationaleThe remainder of this article explains the underlying principles of the OPA333 design, describing the functionalblocks and their individual contributions to the overallperformance of this remarkable amplifier.

Offset cancellation of a wideband amplifier in generalReducing the input offset voltage of a wideband amplifier,AW, typically requires the support of an additional stabiliz-ing or nulling amplifier, AN, which is connected in parallelto the main amplifier (Figure 4). The stabilizing amplifiermust be able to cancel its own offset, thus resembling anideal amplifier. In addition, its open-loop gain has to besignificantly larger than AN >> AW. This is usually achievedby using a multistage amplifier whose input gain is identicalto AW and whose output gain is G, with G >> 1. Note thatthe nulling amplifier can use chopping or auto-zeroing tonull its own offset.

The output voltage of the circuit in Figure 4 is given by

Assuming G >> 1 and substituting AWG with AN yields theeffective open-loop gain and input offset for the amplifiermodel in Figure 5:

V AV V

GOUT NIN OSW= ×

+.

V V V A GV V

GOUT W N WIN OSW= + = × + ×

++

( ) .11

VIN VOUT

VN

VW

VOSW

A = AN W

G

AW

AN

+

–

+

–

Figure 4. Offset cancellation principle

VIN VOUTAN

VOSW

G

+

–

Figure 5. Effective amplifier model

C = C AIN C1

CC1

VIN VOUT–A

Figure 6. Miller effect: CIN = CC1(A + 1).For A >> 1: CIN ≈ CC1A.

Thus, the DC gain has increased by factor G, from AW toAN, while the input offset of the wideband amplifier isreduced by G (typically 60 dB).

Multistage stabilizing amplifierLarge capacitance values are required to achieve low dom-inant pole frequencies. We recall that Miller compensationis used in op amp design to reduce these large valuesdown to a size feasible for on-chip integration. Miller com-pensation relies on the effect that the input capacitance ofan amplifier, CIN, appears to be A times larger than theactual capacitance in the feedback loop, CC1, with A beingthe amplifier gain (see Figure 6).

Because the precision path requires significantly highergain than the wideband path, a three-stage cascade struc-ture is used to provide that gain while allowing operationfrom very low supply voltages. If we neglect the choppermechanism and the notch filter in Figure 1, the stabilizing



24


amplifier that remains is a three-stage, nestedMiller-compensated (NMC) cascade amplifier asshown in Figure 7.

Miller compensation provides the additionalvaluable feature of frequency-response shapingthrough a process known as pole-splitting.Figure 8 shows the frequency response of anuncompensated three-stage amplifier with itspole frequencies fp1, fp2, and fp3. Through care-ful design of the gm stages and appropriateselection of the Miller compensation capaci-tances, it is possible to shift fp1 down to a verylow frequency, fp1′, making it the dominantpole of the precision path. At the same time,fp2 is pushed to higher frequencies, fp2′,expanding the 20-dB/dec slope and thus therange of stable operation.

In the case of a stand-alone amplifier, fp2is usually located beyond the unity-gain fre-quency, allowing a three-stage NMC structureto achieve high bandwidth beyond 10 MHzwhile maintaining phase margins of up to 70°.

In the OPA333 design, however, the NMCamplifier operates in parallel with the widebandstages, gm4 and gm3. Because this widebandforward path is responsible for providing thenecessary bandwidth and phase margin of theoverall amplifier, the stability requirements ofthe NMC amplifier are relaxed, allowing its second pole, fp2, to occur before the unity-gain crossover.

Where do we apply the actual offset cancellation?To answer this question we can, for conve-nience, replace the gm stages with actual opamps, where the precision path comprising A1to A3 is in parallel with thewideband path comprising A4and A3 (Figure 9). For furthersimplification, the switchingnetwork and the notch filterhave been left out, and theamplifier circuit is shown in afeedback configuration.

CC2

CC1

RO1 RO2

CL

VIN VOUT+g

m1+g

m2–g

mL

Figure 7. Three-stage NMC cascade amplifier

Am

pli

fie

rG

ain

,A

( dB

)

fp2 fp2'fp1fp1' = fpd

Normal Three-Stage Amp

fp3

Frequency, f (Hz)

Three-Stage Nested Miller (NMC) Amp

Figure 8. Pole splitting of the three-stage NMC amplifier

RFRG

VIN

VOUT

VOS4

A4

VOS3

A3

VOS2

A2

VOS3

A3

VOS1

A1

+

+

+–

–

–

+

–

+

–

Figure 9. Deriving VOUT as a function of individual offset voltages, VOSi



25


Providing each amplifier with its individual input offsetvoltage and setting VIN to zero yields an output of

where

Separating the VOUT terms and solving for VOUT gives

Assuming that the DC gains of A4 and A1 are matched,

We see that, except for VOS1, all offsets are strongly sup-pressed by the open-loop gains of at least one, if not two,preceding amplifiers. The nonattenuated VOS1, however,requires active cancellation through either chopping orauto-zeroing.

Auto-zeroing versus choppingFigures 10 and 11 show the simplified principles of bothoffset cancellation methods. Auto-zeroing consists of twophases, a nulling phase with switches in position 1 and anamplification phase with switches in position 2. In thenulling phase, the amplifier measures its own offset andstores it on capacitor C1. In the amplification phase, theamplifier measures the input voltage plus the offset andsubtracts the previously stored offset from the contami-nated input. The resulting, offset-free output signal isstored on C2 and operates as correcting voltage for themain amplifier.

The function of sampling and holding the offset voltagemakes the AZA a data-sampling system prone to aliasingand folding effects. For DC and low frequencies, the noise

VV

A A

V

A

V

AVOUT

OS OS OSOS= + + +

⎛⎝⎜

⎞⎠⎟

1 2 3

1 2

2

1

4

21β

.

VV V A V A V A A

A A AOUTOS OS OS OS=

+ + ++

⎛⎝⎜

⎞⎠⎟

1 2 3 2 2 4 4 1 1 2

1 2 4β.

β =+

R

R RF

F G.

V A V A V A V V

A V A V V

OUT OS OS OS OUT

OS OS OUT

= + + −( )⎡⎣ ⎤⎦ + + −

3 3 2 2 1 1

3 3 4 4

β

ββ( )⎡⎣ ⎤⎦ ,

properties in the time domain change slowly, and the sub-traction of two consecutive noise samples results in a truecancellation. At higher frequencies this correlation dimin-ishes, and subtraction errors translate into wideband fold-over components in the baseband, where they make upthe lion’s share of baseband noise.

Figure 12 shows that the AZA removes offset and 1/fnoise, but at the cost of a significantly raised noise floor inthe baseband.

Because the noise power density of an amplifier’s inputstage is inversely proportional to its transconductance

VIN

+2

2

C1 C2

11

–

VA Z

VOSN

+

–

AN

–BN

OSC

Figure 10. Auto-zero principle

VIN 2

21

VCH

VOSN

+

–

AN

1

OSC

Figure 11. Chopper principle

0.1

1.0

10

100

1 10 100 10 k 100 k1 k

1/f

No

rma

lize

dS

pe

ctr

al

De

ns

ity

Frequency, f (Hz)

e en nw

Auto-Zero

Chopper

Figure 12. Auto-zeroing and chopping effects on baseband noise



26


(e2n = 2/3 × 4KT/gm), and gm is proportional to the stage

quiescent current (gm ≈ IQ), the power density is inverselyproportional to the quiescent current (e2

n ≈ 1/IQ). There-fore, to reduce the baseband noise of an AZA to the desiredlevel, the initial input noise must be lowered through a significant increase in quiescent current, which counteractsthe intrinsic requirements of a micropower amplifier.

In strong contrast to the AZA, the chopper amplifierdoes not introduce aliasing fold-over components. Asshown in Figure 11, a chopper simply modulates its offsetand low-frequency noise to higher frequencies. Here thenoise is neither sampled nor held, just periodically invertedwithout changing the general properties of the noise in thetime domain. Although the power density of the chopperoutput noise results from a summation in the choppermodulation, as is the case for the sample-and-hold processin the AZA, the replicas (odd harmonics only) vary rapidlyvia a 1/n2 function, making their contribution to the base-band negligible.

10

0

–10

–20

–30

–40

–50

–60

–70

–80101 100 k10 k1 k100

Frequency, f (Hz)

Am

pli

fie

rG

ain

,A

( dB

)

1 M

–20 dB perdecade

Figure 13. Filter transfer function

V = 148 µpp V with Notch Filter

V = 75 mpp V without Notch Filter40

30

20

10

–10

–20

–30

–40

0

250 260

Ou

tpu

tV

olt

ag

e,

V( m

V)

270 280

Time, t (µs)290 300

Figure 14. Output ripple with and without filter

As shown in Figure 12, for chopper frequencies largerthan the noise-corner frequencies, the baseband whitenoise in the output is only slightly larger than the initialwhite-noise floor, which eliminates increases in quiescentcurrent and makes the chopper amplifier suitable formicropower applications.

Output noise filterWhile the chopper does not introduce wideband foldingcomponents into the baseband, the process of choppingdoes modulate the offset, or DC noise, into the higher fre-quency range where no noise existed before, thus creatinglarge output ripples. The OPA333 therefore possesses aswitched-capacitor (SC), low-pass notch filter in the offsetcancellation path with filter notches at the chopper fre-quency and its harmonics. The filter’s transfer function,shown in Figure 13, reduces the output ripple by a factorof more than 500. Figure 14 shows the difference in outputripple with and without the notch filter.



27


The final amplifier systemFigure 15 shows the actual implementation of the chopper-stabilized amplifier, revealing a differential signal-pathstructure for gm1 and the SC notch filter. Note that, forsignal symmetry, the implementation of a third capacitor,C3, is required.

During phases 1 and 2, the input signal is modulated.During phases 3 and 4, the capacitors C5 and C6 work intandem. While C5 is charged with gm1’s output current, the charge of C6 is transferred to the integrator, gm2, andvice versa.

Note that the input signal is modulated twice, once bythe input switches of gm1 and a second time by the outputswitches. Relative to VIN, the polarity or direction of gm1’soutput current remains the same during phases 1 and 2.However, the offset voltage, or offset current, is modulatedonly once by the output switches. Its polarity changesfrom phase 1 to phase 2.

During the first half of phase 3 (that is, tCK/2 of theclock period), the phase 1 switches are active and C5 ischarged with gm1’s output current, ISIG + IOS. During the

second half of phase 3, the phase 2 switches are active,the direction of the offset current changes, and C5 ischarged with ISIG – IOS.

The capacitor charge is given by Q = IC × t, with t = tCK/2,IC1 = ISIG + IOS, and IC2 = ISIG – IOS. Thus, after phase 3 iscompleted, C5 has the charge of QC5 = (ISIG + IOS) × tCK/2+ (ISIG – IOS) × tCK/2 = ISIG × tCK. The offset-free charge isthen transferred to the next stage during phase 4, wherethe same procedure is applied to C6.

While the large attenuation of the notch filter removesthe output ripple, it may also filter the signal to some degree.A signal delay is created by the integrate-and-transferaction, which affects the circuit differently depending onhow the compensation capacitors are connected.

Notice that C2 and C3 have been split into “a” and “b”portions (Figure 15). The “b” portion returns most of thecompensation to the filter input, C2b = 6 pF, maintaininggood continuous-time characteristics for the signal path.The smaller “a” portion, C2a = 1 pF, connects to the filteroutput, providing sufficient local-loop stability. The complexcompensation scheme is responsible for a slight rise in the

gm1

Phase 3

Phase 3

Phase 4

Phase 4

Phase 3

Phase 4

Phase 4

Phase 3

C16 pF

4

C8 pF

5

C8 pF

6

SC Notch Filter withSynchronous Integration

VIN

VOUT

gm2

C6 pF

2b

C1 pF

2a

C7 pF

1

C1 pF

3aC

6 pF3b

gm3

gm4

5.00

0.00

5.00

0.00

5.00

0.00

5.00

0.00

5.00

0.00

Phase 1

Phase 2

Closed

Closed

Closed

Closed

Open

Open

Open

Open

Phase 3

Phase 4

InternalClock

0.00 6.00 12.00

Time, t (µs)

Phase 2

Phase 1

Phase 2

Phase 1

Phase 2

Phase 1

Phase 2

Phase 1

Figure 15. Internal block diagram and timing sequence



28


TI COMPETITOR

(1) (2) (3) (4) (5)DEVICE OPA333 AD8628 ICL7650 LTC2054 OPA335 AD8551

Year 2006 2005 2005 2004 2002 2002

fCH (kHz) 125 15 — — — —

fAZ (kHz) — 15 0.25 1 10 4

VOS (µV) 2 1 1 3 1 1

IB (pA) 70 30 5 1 70 10

GBW (kHz) 350 2500 2000 500 2000 1500

en (nV/√Hz–––

) 55 22 25 85 55 42

IQ (µA) 15 1100 2000 150 285 975

e2n × IQ (nV2 × µA)* 45 532 1250 1084 862 1720

GBW/IQ (kHz/µA)* 23 2 1 3 7 2

Table 1. Comparison of the OPA333 versus previous zero-drift amplifiers

*Figure of merit

noise floor beyond 20 kHz, which is visible inFigure 16.

SummaryThis article elaborates on the technicalimplementations of the OPA333, the industry’ssuperior, zero-drift micropower amplifier.Chopper stabilization ensures low basebandnoise at very low supply currents. An inte-grated, patent-pending notch filter removesthe output ripple created by the choppermodulation of the input offset.

Because an amplifier’s noise power densityis inversely proportional to its quiescent current, the product (e2

n × IQ) represents afigure of merit, revealing how much addi-tional tail current was necessary to reducethe remaining baseband noise to the desiredlevel after the process of offset cancellation.A more familiar figure is the ratio of gainbandwidth to quiescent current, GBW/IQ,disclosing how much bandwidth per micro-ampere was achieved. In both figures of merit,the OPA333 demonstrates far superior per-formance versus even its closest competitor(see Table 1).

Related Web sitesamplifier.ti.com

www.ti.com/sc/device/OPA333

LinearVertical

Scale

LinearVertical

Scale

Frequency, f (kHz)

Frequency, f (kHz)

0

0

10

100

20

200

Slight Riseto 50 kHz

Op Amp Gain G = 10

Low Level ofChopping FrequencyVisible at 125 kHz

Op Amp Gain G = 10

ne = 55 nV/ Hzfrom DC to 20 kHz

Figure 16. DC to 20-kHz and 200-kHz noise spectra


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http://www.ti.com/sc/device/OPA333

29


Spreadsheet modeling tool helps analyzepower- and ground-plane voltage drops tokeep core voltages within tolerance

IntroductionThe trend toward smaller geometries in processor coresdrives requirements for lower-voltage power supplies. Forexample, DSPs from Texas Instruments (TI) such as theTMS320TCI648x series require a 1-V core. As processor-corevoltages drop, clock frequencies are typically increased tomatch the thermal capabilities of the packaging and of theoverall cooling systems. That means higher currents in thepower structures of printed circuit boards (PCBs). It is notuncommon to see 50- to 100-A current requirements for a1-V rail when multiple processors are distributed on a singlePCB. This article addresses the impact of these higher cur-rents on the power- and ground-plane design and on thecore-voltage-tolerance budget and describes a spreadsheetmodel that may be used to calculate voltage gradients.

Requirements for processor-core voltageThe typical voltage-tolerance budget for the processor coreis 3% for a 1-V rail, which equates to 30 mV for the totalstatic and dynamic response of the power supply. TI’s newpower devices such as the PTH TurboTrans™ series (T2)modules, and new synchronous buck controllers such asthe TPS40140, have been designed with internal refer-ences that allow for 1.5% tolerance under static line, load,and temperature conditions. The current guidanceallocates the remaining 1.5% tolerance for the transientresponse of the supply. This, in combination with thebandwidth of the switching power supply, determines theamount of capacitance required to meet the core-voltagerequirements. Local bypassing counteracts the inductivenature of large ground planes. Little attention is typicallypaid to the DC voltage drop in the power planes. Ascurrents continue to increase and core voltages decrease,power- and ground-plane DC voltage drops will become amore significant portion of the total tolerance budget.

Power- and ground-plane voltage-dropconsiderationsPower- and ground-plane copper thickness is the primaryattribute that impacts the voltage drop. Another major factor is the placement of the processor loads relative tothe power-supply output pins. Power converters such asthe PTH series allow for remote sensing to mitigate boardvoltage drops, but there are few tools to aid the designerin the placement of these remote sensing lines. Mostdesigners use an ohms-per-square figure for different

copper thicknesses to calculate an equivalent resistanceand to determine the required copper weight. This tech-nique works well for simple configurations; but whenmultiple processors or significant plane discontinuities arepresent (due to vias or other features), the simple ohms-per-square method may not be adequate to model thevoltage drop in the power and ground planes.

Commercial softwareCommercial software for finite-element analysis may beused to compute the plane voltage drops for arbitrarygeometries, but the software is expensive and requires adeveloped expertise. There is no simple tool to generate aPCB model and quickly assess the plane voltage drops.

SPICE modelingA model of the PCB may be constructed with an equiva-lent sheet resistance model (see Figure 1), with sourcesand loads connected to the appropriate nodes. The PCB

Texas Instruments Incorporated General Interest

By Steve WidenerAnalog Field Applications Engineer


2,22,1

1,1 1,2

RR

R

R

3,23,1

RR

R

4,24,1

RR

R

5,25,1

RR

R

2,3

1,3

R

R

R

3,3

4,3R

5,3

R

R

2,4

1,4

R

R

R

3,4

R

4,4

R

R

5,4

R

R

2,5

1,5

R

R

R

3,5

R

R

4,5

R

R

5,5

R

R

RB

RD

IA

ID

ID

IB

RA RC

Figure 1. Resistor sheet


Texas Instruments IncorporatedGeneral Interest

30


model can then be solved with a SPICE-based simulator.The difficulty in the SPICE method is that the schematicis unwieldy and the results are difficult to visualize.

A spreadsheet-based modelThis article details a method that uses Microsoft® Excel®

spreadsheet software to determine plane voltage distribu-tion on a PCB with arbitrary geometry and source/loadplacement. A little-used feature of Excel, circular refer-ences and iteration, is used to solve the network matrix.The method may also be used with other mathematicalsoftware. This article also develops the necessary equa-tions and provides step-by-step instructions to calculatepower/ground-plane voltage drop for arbitrary source andload conditions.

Node equations for sheet resistanceFigure 1 is a schematic model of PCB node voltages inter-connected by equivalent sheet resistances, R, with nodesexpressed as row, column. This model divides the PCBinto 25 nodes. Increasing the number of squares will pro-vide more resolution. This array is sufficient to illustratethe general node equations applicable to larger models.The voltage at any node is determined by using Kirkoff’scurrent law, which states that the sum of all currents intoa node must equal zero. One of three equations is requiredto determine node voltage, which depends on the nodelocation—central, edge, or corner.

Central-node equationsFor central node 3,3 in Figure 1, the current equation is

(1)

Using Ohm’s law yields

(2)

Solving Equation 2 for V3,3 yields

(3)

Equation 3 is the general form of the equation for a central node with arbitrary sheet resistance. This equationaccommodates variations in square resistance that are dueto localized heating or other nonuniformities. In the caseof uniform sheet resistance, Equation 3 simplifies to

(4)VV V V V

3 33 2 2 3 3 4 4 3

4,, , , , .=

+ + +

VR R R V R R R V R R R V R R R V

R R R R RB C D A C D A B D A B C

B C D A3 3

3 2 2 3 3 4 4 3,

, , , ,=+ + +

+ CC D A B D A B CR R R R R R R+ +.

V V

R

V V

R

V V

R

V V

RA B C D

3 2 3 3 2 3 3 3 3 4 3 3 4 3 3 3 0, , , , , , , , .−

+−

+−

+−

=

I I I IA B C D+ + + = 0.


(6)

Solving for V3,1 yields

(7)

Equation 7 is the general form of the equation for an edgenode with arbitrary sheet resistance. In the case of uniformsheet resistance, Equation 7 simplifies to

(8)

Corner-node equationsFor corner node 5,1, Figure 3 depicts the currents flowingfrom the two adjacent nodes. The current equation for acorner node is

(9)I IA B+ = 0.

VV V V

3 14 1 2 1 3 2

3,, , , .=

+ +

VR R V R R V R R V

R R R R R RB C A C A B

B C A C A B3 1

4 1 2 1 3 2,

, , , .=+ +

+ +

V V

R

V V

R

V V

RA B C

4 1 3 1 2 1 3 1 3 2 3 1 0, , , , , , .−

+−

+−

=

2,1

3,1

4,1

2,2R

3,2

R

4,2

R

R

RB

RA

IA

IC

IB

RC

Figure 2. Edge node

4,1

5,1

4,2R

5,2

RRB

RA

IA

IB

Figure 3. Corner node

Edge-node equationsFor edge node 3,1, Figure 2 depicts the currents flowingfrom the three adjacent nodes. The current equation foran edge node is

(5)I I IA B C+ + = 0.



31



(10)

Solving for V5,1 yields

(11)

Equation 11 is the general form of the equation for a cornernode with arbitrary sheet resistance. In the case of uniformsheet resistance, Equation 11 simplifies to

(12)

Source nodesThe outputs of power supplies are modeled as fixed values(voltages) at the geometrically relevant nodes. Many powersupplies utilize differential remote sensing. In the model,the fixed-voltage nodes may represent the local sensepoints, and the power-supply output is varied to set thedesired voltage at those remote sensing points.

The remaining equations solve for node voltages wherea load is present at the node.

Load equationsCentral-node equationsIn the case of a central node with a load (Figure 4), thecurrent equation is

(13)I I I I IA B C D Load+ + + = .

VV V

5 15 2 4 1

2,, , .=

+

VR V R V

R RB A

B A5 1

5 2 4 1,

, , .=++

V V

R

V V

RA B

5 2 5 1 4 1 5 1 0, , , , .−

+−

=

Equation 15 is the general form of the equation for a central node with arbitrary sheet resistance and a loadcurrent. In the case of uniform sheet resistance, Equation15 simplifies to

(16)

Edge-node equationsFor the case where load current is sourced from an edgenode (node 3,1 in Figure 2), the node voltage equation is

(17)

For uniform sheet resistance, Equation 17 simplifies to

(18)

Corner-node equationsFor the case where load current is sourced from a cornernode (node 5,1 in Figure 3), the node voltage equation is

(19)

For uniform sheet resistance, Equation 19 simplifies to

(20)

The previous equations may be used to model thepower- or ground-plane voltage map of a PCB with arbitrary source, resistance, and load arrangements.

Example problemPCB voltage-drop modeling presents two challenges. Thefirst is to build the representative model with a number ofvoltage sources, path resistances, and loads distributedacross the PCB; the second is to solve the simultaneousequations. Excel spreadsheet software provides a conve-nient means to quickly build a model and solve the nodalequations. Following is a simple example that illustratesthis. A PCB power plane with uniform sheet resistance ismodeled and the voltage at every node is calculated for agiven set of load conditions.

For this example, a 10 × 15-cm copper board with a 1-V/1-oz power plane and a 1-oz ground return plane is assumed.A single power supply with 1 output pin provides the volt-age source, and distributed across the PCB are 10 loadsdrawing 5 A each. The goal is to determine the steady-state voltage at each load with a 65°C board temperature.

VV V RILoad

5 15 2 4 1

2,, , .=

+ −

VR V R V R R I

R RB A A B Load

B A5 1

5 2 4 1,

, , .=+ −

+

VV V V RILoad

3 14 1 2 1 3 2

3,, , , .=

+ + −

VR R V R R V R R V R R R I

R R R R R RB C A C A B A B C Load

B C A C A B3 1

4 1 2 1 3 2,

, , , .=+ + −

+ +

VV V V V RILoad

3 33 2 2 3 3 4 4 3

4,, , , , .=

+ + + −

2,2

3,2

RILoad

4,2

R

2,3R

3,3

4,3R

2,4R

3,4

R

4,4

R

R

RB

RD

IA

ID

IC

IB

RA RC

Figure 4. Central load node


(14)

Solving Equation 14 for V3,3 yields

(15)VR R R V R R R V R R R V R R R V R R R R IB C D A C D A B D A B C A B C D

3 33 2 2 3 3 4 4 3

,, , , ,=

+ + + − LLoad

B C D A C D A B D A B CR R R R R R R R R R R R+ + +.

V V

R

V V

R

V V

R

V V

RI

A B C DLoad

3 2 3 3 2 3 3 3 3 4 3 3 4 3 3 3, , , , , , , , .−

+−

+−

+−

=


Worksheet model construction step-by-stepTo model the PCB, a worksheet is used where a range ofcells is assigned to represent the node voltages on the PCB.Each cell corresponds to a square of copper on the PCB.The size of each square is chosen for a desired geometricresolution. For instance, if 1-mm geometries (such as slotsor via holes) are desired, then 100 × 150 squares (cells)would be required to model a 10 × 15-cm PCB. For thissimple example, 5-mm squares are selected to model a 10 × 7.5-cm PCB, so an array of 20 × 15 cells is used in thespreadsheet (see Figure 5). The300 cells are highlighted greento identify the PCB outline.

Circular referencesTo build this model, a few non-intuitive steps must be followed,because circular references arerequired to solve the nodalequations. “Circular reference”refers to the condition wherethe value of a cell is a functionof its own value in some way.This situation may be resolvedby allowing Excel to iterate thevalue in the cell (by increasingor decreasing the value) untilsome tolerance level is met andthe interrelated equations con-verge. There are instances whenExcel will not be able to resolvecircular references—particularly


32


Figure 5. Model of 10 x 7.5-cm PCB with 5-mm squares

evident when the model is being built or is undergoingmajor changes. For this reason, manual calculation is usedin the spreadsheet model.

InitializationTo build the model, it is first assumed that the voltage dis-tribution is ideal; that is, there is 1 V in every cell. A “1” isentered in each cell to start (see Figure 6). Note that it isconvenient to label the boundaries of the PCB model withan index grid to aid in placing the sources and loads.

Figure 6. Model of ideal voltage distribution

Simple model is 15 cells (columns) by 20 cells (rows).



33


The next step is to disable automatic calculation bychecking the Manual “radio button” in the Tools >Options > Calculation menu (Figure 7). When a changeis made, the F9 key recalculates the worksheet. While thismenu is open, the Iteration box should be checked, and theparameters Maximum Iterations and Maximum Change

should be set to 20000 and 0.000001, respectively. Thissets the parameters for the solution engine so that iterationsoccur up to 20,000 times or until the solution converges towithin 1 µV. These preliminary settings are required toenable iterative calculations and to avoid convergenceerrors while the PCB model is being built and modified.

A simplifying assumptionFor this example, the sheet resistance is assumed to beuniform in the power and ground planes so that a simplify-ing assumption can be made. The ground- and power-plane resistances are combined, and the “return” path isassumed to have zero resistance. That assumption makesthe voltage at each cell representative of the differentialvoltage (plane to ground) at every location on the PCB.The resistance of the power plane is simply doubled toaccount for the return path.

Copper-sheet resistanceThe sheet resistance of copper is given as

(21)

where ρ is the sheet resistance of copper in ohms per squareρ20 is the resistivity of copper at 20°C equal to

17.241 mΩ/µm†; α is the temperature coefficient of resistance for copper equal to 0.393%/°C†; T is the PCB

( / );Ω

ρρ α

=+ −( )⎡⎣ ⎤⎦20 1 20T

h,

†CRC Handbook of Chemistry and Physics, 58th edition (CRC Press, Inc.,1977), Section E-84.

Figure 7. PCB model settings entered in Calculation menu

Figure 8. Implementation of Equation 21 in Excel

temperature in degrees Celsius at the square of interest;and h is the thickness of the copper plane in micrometers(1 oz ~ 35.6 µm ±10%). Equation 21 is implemented withthe following Excel equation inserted into cell E2 (seeFigure 8):

=(0.017241*(1+0.00393*($D$8-20)))/(17.8*(IF($B$3,1,IF($B$4,2,IF($B$5,4,IF($B$6,6,0))))))

The temperature is located in cell D8, and one of thecopper thicknesses in cells B3 through B6 (½, 1, 2, or 3 oz)is exclusively selected with a “TRUE.” The resulting sheetresistance value in ohms per square is in cell E2. The valuefor twice this resistance (accounting for the combinedpower- and ground-plane resistances), located in cell E5,is used for the simplifying assumption.



34


Adding radio buttons to select copper thicknessThe copper thicknesses of ½, 1, 2, and 3 oz are arranged asshown in Figure 8 to allow for the convenient use of radiobuttons to select them. To place a radio button, turn on theControl Toolbox toolbar (View > Toolbars > Control

Toolbox) and select Design Mode and Option Button

(Figure 9a). In this mode, use the cursor to draw a box overcells B3 and C3 as shown in Figure 9b. Right-clicking in thenew OptionButton1 area and selecting Properties makesthe dialog box in Figure 9c appear. Change the Caption

field from “OptionButton1” to “1/2 oz” and enter “B3” into

Figure 9. Adding radio buttons to select copper thickness

(b) (c)

the LinkedCell field, then close the dialog box. The radiobutton now appears as shown in Figure 9d. With these set-tings, cell B3 will be true when this radio button is selected.

Repeat the process for 1, 2, and 3 oz, linking their radiobuttons to cells B4, B5, and B6, respectively. The resultsappear as shown in Figure 9e.

Because the GroupName field (Sheet1) is common toall the radio buttons, only one thickness may be selectedat a time. The radio buttons will not work until the designmode is exited, but there is one more task to completebefore exiting.

(a)

(d) (e)

Design Mode Option Button



35


Adding a command button for recalculationWhile design mode is still active, it is advantageous to create a reminder button to initiate recalculation. Selectthe Command Button on the Control Toolbox toolbar(see Figure 10a), then click on some empty cells and dragto create a CommandButton1 box as shown in Figure 10b.Right-clicking on the CommandButton1 box and selectingProperties makes the dialog box in Figure 10c appear.Change the Caption field from “CommandButton1” to“Recalculate” and close the dialog box. Now a Recalculate

button is displayed as shown in Figure 10d. Exit design

mode the same way you entered, by clicking the Design

Mode button on the Control Toolbox toolbar (Figure 10e).To cause the Recalculate button to force a recalculation,

a simple macro must be assigned to the button. SelectTools > Macro > Visual Basic Editor to open VisualBasic, then select View > Code to open a window similarto the one shown in Figure 10f. Type in the code shown inFigure 10g and close the window. Now, as the copperthickness and temperature are changed, clicking theRecalculate button will update the ohms-per-square valuesappropriately (see Figure 10h).

Figure 10. Adding a command button for recalculation

(b) (c)

(a)

(d)

(e) (f)

(g) (h)

Command Button

Design Mode “Off”



36


Building the node-voltage modelTo build the node-voltage model, an equation for eachnode must be entered into the appropriate cell in Excel.Note that for each node, “adjoining cells” refers to thosefound either above, below, left, or right—not at a diagonal.

Corner nodes: Enter the Excel expression for Equation 12,“=(Sum of the 2 adjoining cells)/2”.

Example: For cell B13, enter “=(B14+C13)/2”.

Edge nodes: Enter the Excel expression for Equation 8,“=(Sum of the 3 adjoining cells)/3”.

Example: For cell F32, enter “=(F31+E32+G32)/3”.

Central nodes: Enter the Excel expression for Equation 4,“=(Sum of the 4 adjoining cells)/4”.

Example: For cell K23, enter “=(K24+J23+K22+L23)/4”.

Fill in all cells with the equations as described and clickthe Recalculate macro button. All voltages remain at 1 V,as there are no sources or loads. It is advisable to save thespreadsheet at this point and to create a backup. New formfactors may easily be constructed at this stage by recopyingthe equations in the desired resolution and form factor.

Adding sources to the modelSources represent the output of the power supply at thepoint of regulation. Positioning a source is easily done byplacing a fixed numeric value in the cell that corresponds(geometrically) to the location of the actual power-supplyoutput on the PCB. It is convenient to give the cell a con-trasting color for ease of identification. Figure 11 shows a

1-V source that was placed in cell D30 by simply entering“1” in place of the equation.

Adding loads to the modelLoads represent current sinks geometrically located onthe PCB. Enter a location for a load current in cell H5 and enter “10” in that cell (see Figure 12). Then type theExcel expression for Equation 16 into cell M17 as“=(M18+L17+M16+N17-$E$5*$H$5)/4”.

“$E$5” and “$H$5” are absolute (versus relative) refer-ences to the copper resistance and load current, respec-tively, and will not change as this equation is copied intoother cells. The remaining factors should change as theload equation is copied into other cells.

Figure 11. Model with 1-V source entered in cell D30

Figure 12. Model with load current of 10added in cell H5



37


Putting it all togetherFor the load equation just described, the sheet resistance(actually two times the sheet resistance to account for thereturn path) is in cell E5, and the load current is in cellH5. Set the temperature to 25°C and select 3-oz copper,then click the Recalculate button. When the iterations arecomplete, the screen appears as shown in Figure 13. Eachcell now contains the calculated voltage on the PCB (differ-ential voltage to ground at the load point) for the givencopper thickness, source voltage, temperature, and loadcurrent. The cells model voltages at the correspondinggeometric locations on the PCB.

For a visual representation of voltage distribution usinglightweight copper, change the copper thickness to ½ ozand the temperature to 65°C and click Recalculate.Selecting the voltage results and applying a surface chartcreates the voltage map shown in Figure 14.

Figure 13. Voltage distribution calculations using 3-oz copperat 25°C with 1 source and 1 load

12345678

910111213141516

17181920

0.930 –

No

de

Vo

lta

ge

(V)

Board Model Rows BoardM

odel Colum

ns

0.935 –

0.940 –

0.945 –

0.950 –

0.955 –

0.960 –

0.965 –

0.970 –

0.975 –

0.980 –

0.985 –

0.990 –

0.995 –

1.000 –

12

34

56

78

910

1112

13

1514

Figure 14. Voltage map of recalculated datawith ½-oz copper at 65°C


To see an example with multiple loads, reset the copperthickness to 1 oz, the load current to 5 A, and the ambienttemperature to 65°C. Then copy the load equation in cellM17 into 9 additional locations on the PCB and clickRecalculate. The results are shown in Figure 15a. Figure15b shows the new voltage gradient.


38


Figure 15. Calculated voltage distribution with 1 source and 10 loads

(a) With 1-oz copper

(b) With 1-oz copper (c) With 3-oz copper

0.960 –

0.965 –

0.970 –

0.975 –

0.980 –

0.985 –

0.990 –

0.995 –

1.000 –

12345678

910111213141516

17181920

No

de

Vo

lta

ge

(V)


odel Colum

ns

12

34

56

78

910

1112

13

1514

The 50-A total load with 1-oz copper planes causes aworst-case droop of 136 mV—much more than the typicalrequirement of ±30 mV—and that doesn’t include transientresponse. Obviously, thicker copper planes are required,so the copper thickness should be adjusted back to 3 oz(Figure 15c). In this case, the maximum droop is 23.4 mV—a much better situation.

12345678

910111213141516

17181920

0.790 –

0.800 –

0.810 –

0.820 –

0.830 –

0.840 –

0.850 –

0.860 –

0.870 –

0.880 –

0.890 –

0.900 –

0.910 –

0.920 –

0.930 –

0.940 –

0.950 –

0.960 –

0.970 –

0.980 –

0.990 –

1.000 –

No

de

Vo

lta

ge

(V)


odel Colum

ns

12

34

56

78

910

1112

13

1514



39


The voltage-gradient information provided by the modelis very helpful in determining the optimal placement ofthe remote sense lines relative to the power supply orpower module.

Adding slots or viasSlots or rows of vias may be modeled by inserting edgeand corner nodes into the appropriate locations in theworksheet and placing a “0” in the cells that represent the

slots (Figure 16a). With the slots included in the calcula-tion, the voltage plot looks as shown in Figure 16b. Theslot changes the worst-case voltage droop to 30.3 mV.

Many situations may be modeled with this simple exam-ple. Additional accuracy is expected as more cells are usedto model the sheet resistance. The maximum number ofcolumns in Excel is limited to 256, which sets the limita-tion for the minimum resolution (for one dimension of thePCB). Note that the three-dimensional graphing capability

Figure 16. Model with slots added

(a)

(b)

12345678

910111213141516

17181920

0.970 –

0.975 –

0.980 –

0.985 –

0.990 –

0.995 –

1.000 –

No

de

Vo

lta

ge

(V)


odel Colum

ns

12

34

56

78

910

1112

13

1514



40


of Excel is limited to about 25 cells, so graphs are notavailable for higher resolutions. However, this is not a serious limitation, since the cell values are displayed in thetable. Simple conditional formatting may be used to color-code the results directly on the spreadsheet without theneed for a separate graph.

Further applicationsThe technique described may be used to construct morecomplicated geometries. In general, plane thicknesses arenot always the same, as ground planes are typically thickerthan power planes. Further, power planes may be splitrather than uniform, or the “power plane” may be simply avery wide trace on a signal layer. With the described tech-nique, a model for each plane may be constructed and a“difference” sheet created to examine the voltage differ-ence at different load points. Separate temperature andresistance sheets can also aid in constructing more com-plicated geometries.

One common concern is the voltage drop that occursdue to the “Swiss-cheese” effect of having many vias located in and around high-density ICs. This problem may be addressed by inclusion of the nonuniform resistiveeffects described in Equations 3, 7, 11, and 15 in thespreadsheet model. Model the resistance of the square bytaking the ratio of the copper area to the “empty” area(where vias occur) and increasing the resistance for thatsquare by the ratio.

Including local temperature effectsThe copper resistance is a function of temperature, asnoted previously. Localized heating due to FPGAs or DSPswill increase the temperature and thus the resistance ofthe copper around the load points. This variable may beincluded in models by creating an expected temperaturemap of the PCB and adjusting the effective resistance foreach square according to the local temperature on theboard. Again, this requires the inclusion of the nonuniformresistance equations.

ConclusionThe voltage drop of PCB power and ground planes can be a significant contributor to the total voltage-tolerancebudget for processor cores. Excel and other spreadsheetsoftware with circular reference /iteration capabilities maybe used to construct a model of the PCB that can greatlyassist the designer in selecting copper thickness and remotesensing locations, proportioning the voltage-tolerance bud-get, and optimizing the bypass capacitance necessary tomeet transient requirements. The spreadsheet results alsoprovide guidance for power-supply and processor placement.

Related Web sitesdsp.ti.com

www.ti.com/sc/device/TPS40140

A copy of the finished spreadsheet is available for down-load at: www.ti.com/lit/zip/slyt274


http://www.ti.com/sc/device/TPS40140

http://www.ti.com/lit/zip/slyt274

41


Texas Instruments Incorporated Index of Articles


Title Issue Page Lit. No.

Data AcquisitionAspects of data acquisition system design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .1 SLYT191Low-power data acquisition sub-system using the TI TLV1572 . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . . .4 SLYT192Evaluating operational amplifiers as input amplifiers for A-to-D converters . . . . . . . . . . . . . . . . .August 1999 . . . . . . .7 SLYT193Precision voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .1 SLYT183Techniques for sampling high-speed graphics with lower-speed A/D converters . . . . . . . . . . . . .November 1999 . . . .5 SLYT184A methodology of interfacing serial A-to-D converters to DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . . .1 SLYT175The operation of the SAR-ADC based on charge redistribution . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .10 SLYT176The design and performance of a precision voltage reference circuit for 14-bit and

16-bit A-to-D and D-to-A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .1 SLYT168Introduction to phase-locked loop system modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . . .5 SLYT169New DSP development environment includes data converter plug-ins . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .1 SLYT158Higher data throughput for DSP analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . . .5 SLYT159Efficiently interfacing serial data converters to high-speed DSPs . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .10 SLYT160Smallest DSP-compatible ADC provides simplest DSP interface . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .1 SLYT148Hardware auto-identification and software auto-configuration for the

TLV320AIC10 DSP Codec — a “plug-and-play” algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . . .8 SLYT149Using quad and octal ADCs in SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .15 SLYT150Building a simple data acquisition system using the TMS320C31 DSP . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .1 SLYT136Using SPI synchronous communication with data converters — interfacing the

MSP430F149 and TLV5616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . . .7 SLYT137A/D and D/A conversion of PC graphics and component video signals, Part 1: Hardware . . . . .February 2001 . . . .11 SLYT138A/D and D/A conversion of PC graphics and component video signals, Part 2: Software

and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .5 SLYT129Intelligent sensor system maximizes battery life: Interfacing the MSP430F123

Flash MCU, ADS7822, and TPS60311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . . .5 SLYT123SHDSL AFE1230 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . . .5 SLYT114Synchronizing non-FIFO variations of the THS1206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .12 SLYT115Adjusting the A/D voltage reference to provide gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .5 SLYT109MSC1210 debugging strategies for high-precision smart sensors . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . . .7 SLYT110Using direct data transfer to maximize data acquisition throughput . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .14 SLYT111Interfacing op amps and analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . . .5 SLYT104ADS82x ADC with non-uniform sampling clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . . .5 SLYT089Calculating noise figure and third-order intercept in ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .11 SLYT090Evaluation criteria for ADSL analog front end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .16 SLYT091Two-channel, 500-kSPS operation of the ADS8361 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .5 SLYT082ADS809 analog-to-digital converter with large input pulse signal . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . . .8 SLYT083Streamlining the mixed-signal path with the signal-chain-on-chip MSP430F169 . . . . . . . . . . . . .3Q, 2004 . . . . . . . . . .5 SLYT078Supply voltage measurement and ADC PSRR improvement in MSC12xx devices . . . . . . . . . . . .1Q, 2005 . . . . . . . . . .5 SLYT07314-bit, 125-MSPS ADS5500 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .13 SLYT074Clocking high-speed data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .20 SLYT075Implementation of 12-bit delta-sigma DAC with MSC12xx controller . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .27 SLYT076Using resistive touch screens for human/machine interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . . .5 SLYT209ASimple DSP interface for ADS784x/834x ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .10 SLYT210Operating multiple oversampling data converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . . .5 SLYT222Low-power, high-intercept interface to the ADS5424 14-bit, 105-MSPS converter for

undersampling applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .10 SLYT223Understanding and comparing datasheets for high-speed ADCs . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . .5 SLYT231Matching the noise performance of the operational amplifier to the ADC . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . . .5 SLYT237Using the ADS8361 with the MSP430 USI port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . .5 SLYT244Clamp function of high-speed ADC THS1041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . . .5 SLYT253Conversion latency in delta-sigma converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . .5 SLYT264

Index of Articles


http://www-s.ti.com/sc/techlit/SLYT191













































Texas Instruments IncorporatedIndex of Articles

42



Power ManagementStability analysis of low-dropout linear regulators with a PMOS pass element . . . . . . . . . . . . . . .August 1999 . . . . . .10 SLYT194Extended output voltage adjustment (0 V to 3.5 V) using the TI TPS5210 . . . . . . . . . . . . . . . . . .August 1999 . . . . . .13 SLYT195Migrating from the TI TL770x to the TI TLC770x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .14 SLYT196TI TPS5602 for powering TI’s DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . . .8 SLYT185Synchronous buck regulator design using the TI TPS5211 high-frequency

hysteretic controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .10 SLYT186Understanding the stable range of equivalent series resistance of an LDO regulator . . . . . . . . . .November 1999 . . .14 SLYT187Power supply solutions for TI DSPs using synchronous buck converters . . . . . . . . . . . . . . . . . . .February 2000 . . . .12 SLYT177Powering Celeron-type microprocessors using TI’s TPS5210 and TPS5211 controllers . . . . . . . .February 2000 . . . .20 SLYT178Simple design of an ultra-low-ripple DC/DC boost converter with TPS60100 charge pump . . . .May 2000 . . . . . . . .11 SLYT170Low-cost, minimum-size solution for powering future-generation CeleronTM-type

processors with peak currents up to 26 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .14 SLYT171Advantages of using PMOS-type low-dropout linear regulators in battery applications . . . . . . .August 2000 . . . . . .16 SLYT161Optimal output filter design for microprocessor or DSP power supply . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .22 SLYT162Understanding the load-transient response of LDOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .19 SLYT151Comparison of different power supplies for portable DSP solutions

working from a single-cell battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .24 SLYT152Optimal design for an interleaved synchronous buck converter under high-slew-rate,

load-current transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .15 SLYT139–48-V/+48-V hot-swap applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .20 SLYT140Power supply solution for DDR bus termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . . .9 SLYT130Runtime power control for DSPs using the TPS62000 buck converter . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .15 SLYT131Power control design key to realizing InfiniBandSM benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .10 SLYT124Comparing magnetic and piezoelectric transformer approaches in CCFL applications . . . . . . . .1Q, 2002 . . . . . . . . .12 SLYT125Why use a wall adapter for ac input power? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .18 SLYT126SWIFTTM Designer power supply design program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .15 SLYT116Optimizing the switching frequency of ADSL power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .23 SLYT117Powering electronics from the USB port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .28 SLYT118Using the UCC3580-1 controller for highly efficient 3.3-V/100-W isolated supply design . . . . . . .4Q, 2002 . . . . . . . . . .8 SLYT105Power conservation options with dynamic voltage scaling in portable DSP designs . . . . . . . . . . .4Q, 2002 . . . . . . . . .12 SLYT106Understanding piezoelectric transformers in CCFL backlight applications . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .18 SLYT107Load-sharing techniques: Paralleling power modules with overcurrent protection . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .5 SLYT100Using the TPS61042 white-light LED driver as a boost converter . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .7 SLYT101Auto-TrackTM voltage sequencing simplifies simultaneous power-up and power-down . . . . . . . . .3Q, 2003 . . . . . . . . . .5 SLYT095Soft-start circuits for LDO linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .10 SLYT096UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 1 . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .13 SLYT097UCC28517 100-W PFC power converter with 12-V, 8-W bias supply, Part 2 . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .21 SLYT092LED-driver considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .14 SLYT084Tips for successful power-up of today’s high-performance FPGAs . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .11 SLYT079A better bootstrap/bias supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2005 . . . . . . . . .33 SLYT077Understanding noise in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .5 SLYT201Understanding power supply ripple rejection in linear regulators . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . . .8 SLYT202Miniature solutions for voltage isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .13 SLYT211New power modules improve surface-mount manufacturability . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .18 SLYT212Li-ion switching charger integrates power FETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .19 SLYT224TLC5940 dot correction compensates for variations in LED brightness . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .21 SLYT225Powering today’s multi-rail FPGAs and DSPs, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . . .9 SLYT232TPS79918 RF LDO supports migration to StrataFlash® Embedded Memory (P30) . . . . . . . . . . .1Q, 2006 . . . . . . . . .14 SLYT233Practical considerations when designing a power supply with the TPS6211x . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . .17 SLYT234TLC5940 PWM dimming provides superior color quality in LED video displays . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .10 SLYT238Wide-input dc/dc modules offer maximum design flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .13 SLYT239Powering today’s multi-rail FPGAs and DSPs, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .18 SLYT240TPS61059 powers white-light LED as photoflash or movie light . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . . .8 SLYT245TPS65552A powers portable photoflash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .10 SLYT246Single-chip bq2403x power-path manager charges battery while powering system . . . . . . . . . . . .3Q, 2006 . . . . . . . . .12 SLYT247Complete battery-pack design for one- or two-cell portable applications . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .14 SLYT248A 3-A, 1.2-VOUT linear regulator with 80% efficiency and PLOST < 1 W . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . .10 SLYT254























































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Power Management (Continued)bq25012 single-chip, Li-ion charger and dc/dc converter for Bluetooth® headsets . . . . . . . . . . . .4Q, 2006 . . . . . . . . .13 SLYT255Fully integrated TPS6300x buck-boost converter extends Li-ion battery life . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . .15 SLYT256Selecting the correct IC for power-supply applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . .5 SLYT259LDO white-LED driver TPS7510x provides incredibly small solution size . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . . .9 SLYT260Power management for processor core voltage requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . .11 SLYT261Enhanced-safety, linear Li-ion battery charger with thermal regulation and

input overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . . .8 SLYT269Current balancing in four-pair, high-power PoE applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .11 SLYT270

Interface (Data Transmission)TIA/EIA-568A Category 5 cables in low-voltage differential signaling (LVDS) . . . . . . . . . . . . . . .August 1999 . . . . . .16 SLYT197Keep an eye on the LVDS input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .17 SLYT188Skew definition and jitter analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .29 SLYT179LVDS receivers solve problems in non-LVDS applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .33 SLYT180LVDS: The ribbon cable connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .19 SLYT172Performance of LVDS with different cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .30 SLYT163A statistical survey of common-mode noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .30 SLYT153The Active Fail-Safe feature of the SN65LVDS32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .35 SLYT154The SN65LVDS33/34 as an ECL-to-LVTTL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .19 SLYT132Power consumption of LVPECL and LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .23 SLYT127Estimating available application power for Power-over-Ethernet applications . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .18 SLYT085The RS-485 unit load and maximum number of bus connections . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .21 SLYT086Failsafe in RS-485 data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .16 SLYT080Maximizing signal integrity with M-LVDS backplanes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .11 SLYT203Device spacing on RS-485 buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .25 SLYT241Improved CAN network security with TI’s SN65HVD1050 transceiver . . . . . . . . . . . . . . . . . . . . . .3Q, 2006 . . . . . . . . .17 SLYT249Detection of RS-485 signal loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2006 . . . . . . . . .18 SLYT257Enabling high-speed USB OTG functionality on TI DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .18 SLYT271

Amplifiers: AudioReducing the output filter of a Class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 1999 . . . . . .19 SLYT198Power supply decoupling and audio signal filtering for the Class-D audio power amplifier . . . . .August 1999 . . . . . .24 SLYT199PCB layout for the TPA005D1x and TPA032D0x Class-D APAs . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .39 SLYT182An audio circuit collection, Part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .39 SLYT1551.6- to 3.6-volt BTL speaker driver reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .23 SLYT141Notebook computer upgrade path for audio power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .27 SLYT142An audio circuit collection, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .41 SLYT145An audio circuit collection, Part 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .34 SLYT134Audio power amplifier measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .40 SLYT135Audio power amplifier measurements, Part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2002 . . . . . . . . .26 SLYT128

Amplifiers: Op AmpsSingle-supply op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .20 SLYT189Reducing crosstalk of an op amp on a PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 1999 . . .23 SLYT190Matching operational amplifier bandwidth with applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2000 . . . .36 SLYT181Sensor to ADC — analog interface design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .22 SLYT173Using a decompensated op amp for improved performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .May 2000 . . . . . . . .26 SLYT174Design of op amp sine wave oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .33 SLYT164Fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .38 SLYT165The PCB is a component of op amp design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .42 SLYT166Reducing PCB design costs: From schematic capture to PCB layout . . . . . . . . . . . . . . . . . . . . . .August 2000 . . . . . .48 SLYT167Thermistor temperature transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .44 SLYT156Analysis of fully differential amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .November 2000 . . .48 SLYT157Fully differential amplifiers applications: Line termination, driving high-speed ADCs,

and differential transmission lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .32 SLYT143Pressure transducer-to-ADC application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .38 SLYT144Frequency response errors in voltage feedback op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .48 SLYT146Designing for low distortion with high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .July 2001 . . . . . . . .25 SLYT133




















































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Amplifiers: Op Amps (Continued)Fully differential amplifier design in high-speed data acquisition systems . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .35 SLYT119Worst-case design of op amp circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .42 SLYT120Using high-speed op amps for high-performance RF design, Part 1 . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .46 SLYT121Using high-speed op amps for high-performance RF design, Part 2 . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .21 SLYT112FilterProTM low-pass design tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2002 . . . . . . . . .24 SLYT113Active output impedance for ADSL line drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2002 . . . . . . . . .24 SLYT108RF and IF amplifiers with op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . . .9 SLYT102Analyzing feedback loops containing secondary amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2003 . . . . . . . . .14 SLYT103Video switcher using high-speed op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .20 SLYT098Expanding the usability of current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2003 . . . . . . . . .23 SLYT099Calculating noise figure in op amps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2003 . . . . . . . . .31 SLYT094Op amp stability and input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .24 SLYT087Integrated logarithmic amplifiers for industrial applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2004 . . . . . . . . .28 SLYT088Active filters using current-feedback amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Q, 2004 . . . . . . . . .21 SLYT081Auto-zero amplifiers ease the design of high-precision circuits . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2005 . . . . . . . . .19 SLYT204So many amplifiers to choose from: Matching amplifiers to applications . . . . . . . . . . . . . . . . . . . .3Q, 2005 . . . . . . . . .24 SLYT213Instrumentation amplifiers find your needle in the haystack . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Q, 2005 . . . . . . . . .25 SLYT226High-speed notch filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2006 . . . . . . . . .19 SLYT235Low-cost current-shunt monitor IC revives moving-coil meter design . . . . . . . . . . . . . . . . . . . . . .2Q, 2006 . . . . . . . . .27 SLYT242Accurately measuring ADC driving-circuit settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Q, 2007 . . . . . . . . .14 SLYT262New zero-drift amplifier has an IQ of 17 µA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .22 SLYT272

General InterestSynthesis and characterization of nickel manganite from different carboxylate

precursors for thermistor sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .February 2001 . . . .52 SLYT147Analog design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2002 . . . . . . . . .50 SLYT122Spreadsheet modeling tool helps analyze power- and ground-plane voltage drops

to keep core voltages within tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Q, 2007 . . . . . . . . .29 SLYT273


























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