analog integrated circuits fundamental building · pdf fileanalog integrated circuits...

Analog Integrated CircuitsFundamental Building Blocks

Faculty of Electronics Telecommunications and Information Technology

Fundamental Building BlocksElementary amplifier stages

Information Technology

Gabor CsipkesBases of Electronics Department

Outline

basic one stage amplifier configurations

common source amplifiers – principles of operation, parameters

output voltage range output voltage range low frequency gain bandwidth, unity-gain bandwidth frequency response

the one transistor common source amplifier with resistive load

the one transistor common source amplifier with diode load

high gain common source amplfiers

Analog Integrated Circuits – Fundamental building blocks – Elementary Amplifiers 2

high gain common source amplfiers

current source load

cascode and symmetrical cascode

folded cascode

Basic one stage amplifier configurations

configurations and their specific usage depend on transistor connections

typically use a single input transistor

CS CD CG

common source → voltage or transconductance amplifier → always inverting, typically drives capacitive loads, the only configuration providing gain

CS CD CG


typically drives capacitive loads, the only configuration providing gain

common drain → voltage follower, power (current) amplifier → non-inverting, used to drive loads with low resistive component

common gate → current buffer and impedance adapter

Common source amplifiers - principles

input transistor → voltage to current conversion → Gm

load circuit → current to voltage conversion → Rout

the general small signal model is always the same, only Rout may be different

0out

m outin

VA G RV


parameters: output voltage range, low frequency gain, output resistance, frequency response, bandwidth, unity-gain bandwidth, pole-zero configuration

Common source amplifiers – resistive load

most simple form → passive resistance as load, NMOS and PMOS inputs possible

operating point found by matching the current through M and R → intersection of the transistor output characteristic with the load line

the transistor needs appropriate bias (saturation) → DC voltages at the input and the output



the output voltage range defined by the saturation condition of the transistor → → Vout >VGS-VTh

the evolution of Vout is defined by the transfer characteristic of M

2C W 2

2ox

in Th out DDC WI V V V V I R

L

negative quadratic variation



the small signal low frequency model → replace the transistor with its small signal equivalent

calculate the DC gain A0 as the ratio of Vout to Vin

no parasitic capacitances

substrate transconductance gmb neglected for simplicity

0out outm in

DS

V Vg Vr R

KCL at the output node:


DSr R

0 ||1 1m out

out mm DS m out

in G RDS

V gA g r R G RV

r R


the small signal high frequency model → replace the transistor with its small signal equivalent and consider capacitances

calculate the frequency dependent gain A(s) as the ratio of Vout to Vin

consider the non-ideal input source resistance R and the input capacitance C consider the non-ideal input source resistance RS and the input capacitance Cin

KCL at the input and at the output nodes:


1

21

1

in GSin GS GS out

S

out outGS out m GS

out

V V sC V sC V VR

V sR CsC V V g V

R

KCL at the input and at the output nodes:

1

2

in GS

GD

DB L L

C CC CC C C C


1

21 1 1

1( )

1

m outm

out L S m out out S L in

Cg R sg

A ss R C C R g R C s R R C C C

Dominant pole approximation → two poles and one right half plane zero (Miller effect)

0

11

21

12 1

1

2

m out

pout S m L

pL m S

S

A g R

fR R g C C

f C g R CRC C C

Dominant pole approximation → two poles and one right half plane zero (Miller effect)


1

1

0 11

2

2 1

SL in

mzp

mp

S m L

C C Cgf

CgGBW A f

R g C C


the simplified small signal high frequency model → no RS considered

11( )

1

m outm

Cg R sg

A ssR C C

one pole and one right half plane zero (Miller effect)

11 out LsR C C

0

11

2

m out

pout L

m

A g R

fR C

gf


12

2

mzp

m

L

fC

gGBWC

The dominant pole approximation

helps in finding the poles a second order transfer function

22

1 1 1( )11 11 1 1

A ssa s bs s ss

1 2 1 2 1 2

1 1 1p p p p p p

s

assume that ωp1<<ωp2

1 2

1 1

p p 2 2

1 1 2

1 1( )11

p p p

A ss s sa s b


pole frequencies found by identifying coefficients of s

1 21 1;

2 2p paf f

a b where a and b depend on

circuit parameters

The Miller effect

appears when the input and the output of an inverting amplifier are shunted with a capacitance → the shunt capacitance is reflected back to the input and forward to the output

11M in M outaI sC a V sC V

a

1 1;

1in outV VI sC a I sC

1 2

1 1;in outV VI sC I sC


This interpretation of the Miller effect is correct only if no input source resistance RS is present !

1M MI sC a I sC

1

2

11

M M

M M

C C a aCaC C C

a

Common source amplifiers – diode load

the passive load resistance swapped with a MOS transistor in diode connection

the operating point is found by matching the currents through M1 and M2 → intersection of the M1 output characteristic with the M2 transfer characteristic


211

1

222

2

12

| |2

n oxD in Thn out

p oxD DD out Thp

C WI V V VL

C WI V V V

L

output characteristic → I=ID1=f (Vout)

transfer characteristic → I=ID2=f (Vout)


the output voltage range is defined by the voltage drops across M1 and M2

M2 is always saturated (VSG=VSD), the output voltage cannot swing above VDD-VDSat2-|VThp|

M1 requires at least VDSat1 for saturation → Vout>VDSat1

In practice:

small Vin → M1 in subthreshold region → ID1 slowly increases with Vin causing a subthreshold voltage drop on M2 → Voutsuffers a near linear decrease


large Vin → M2 delivers increasing current until velocity saturation → Voutcannot reach VDSat1 because its variation stops


the small signal low frequency model → replace the transistors with their small signal equivalent models


no parasitic capacitances no parasitic capacitances


1 1 2 21 2

0||out

m GS m GSDS DS

Vg V g Vr r



0 1 1 2 12 2

1 1|| ||m

out

outm DS DS m m out

in m mGR

VA g r r g G RV g g

The gain approximately unity if gm1=gm2 → typical voltage buffer !


the small signal high frequency model → replace the transistors with their small signal equivalents and consider capacitances


the input source resistance R is neglected the input source resistance RS is neglected


2

1 1

1

in

out outin out m GS

outV

V sR CsC V V g V

R

KCL at the output node:1 1

2 1 2 2

GD

DB DB GS L

C CC C C C C


the small signal high frequency model

10

1

1 2

11( )

1 1

m outzpmout

in out

sC Ag R sgVA s sV sR C C

one pole and one right half plane zero (Miller effect) 1 2 1in out

p

10

2

21 2

m

m

mp

L

gAggf

C


1

1

2

2

L

mzp

Cgf

C

Common source amplifiers – current source load

the diode load swapped with a simple MOS current source

the operating point is found by matching the currents through M1 and M2 → intersection of the transistor output characteristics


211

1

222 2

2

12

12

n oxD in Thn out

p oxD DD G out

C WI V V VL

C WI V V V

L




the output voltage range is defined by the voltage drops across M1 and M2

both transistors must be biased in saturation

for larger input voltages the relatively high gain may cause clipping (distortion) at the output → both the input and the output voltage ranges are limitedoutput → both the input and the output voltage ranges are limited


min

max

out DSat

out DD DSat

V VV V V






1 1 2 21 2

0||out

m GS m GSDS DS

Vg V g Vr r



0 1 1 2||m out

outm DS DS m out

in G R

VA g r r G RV

High gain, typically larger than 20dB.


the small signal high frequency model → replace the transistors with their small signal equivalents and consider capacitances


the input source resistance R is neglected the input source resistance RS is neglected


2

1 1

1

in

out outin out m GS

outV

V sR CsC V V g V

R

KCL at the output node:1 1

2 1 2 2

GD

DB DB GS L

C CC C C C C


the small signal high frequency model

10

1

1 2

11( )

1 1

m outzpmout

in out

sC Ag R sgVA s sV sR C C

one pole and one right half plane zero (Miller effect)

1p

0 1 1 2

1 2

1

||1

2 ||

m DS DS

pDS DS L

m

A g r r

fr r C

gf


1

1

1

2

2

mzp

m

L

gfCgGBW

C

Common source amplifiers – cascode input

the load is still a single MOS transistor current source, but the input stage is cascoded

the operating point is found by matching the currents → intersection of M1-M2 current source with the M3 output characteristics

Recall transistor biasing in the cascode input stage

Recall transistor biasing in the cascode current source and carefully consider voltage budget !



the output voltage range is defined by the voltage drops across M1, M2 and M3

all transistors must be biased in saturation

for larger input voltages the relatively high gain may cause clipping (distortion) at the output → both the input and the output voltage ranges are limitedoutput → both the input and the output voltage ranges are limited

min

max

2out DSat

out DD DSat

V VV V V


maxout DD DSat






22 2

2 3

2 22 2 1 1

2 1

0out S outm GS

DS DS

out S Sm GS m GS

DS DS

V V Vg Vr r

V V Vg V g Vr r


2 1DS DSr r

3 2 2 1

0 13 2 2 1

m

out

DS m DS DSm m out

DS m DS DSGR

r g r rA g G Rr g r r


the small signal high frequency model → replace the transistors with their small signal equivalents, consider capacitances and calculate the frequency dependent gain A(s)as the ratio of Vout to Vin


3 322 2

2 3

2 1 221 2 2 2 1 1

2 1

10

1

out DSout Sm GS

DS DS

S DSout Sin S m GS m GS

DS DS

V sr CV Vg Vr r

V sr CV VsC V V g V g Vr r


101 3

1

2 3 3 1 23 3

2 1 2

11( )

1 1 1

m DSzpm

DSDS

m p p

sC Ag r sg

A sr C C C s ss r C s

g

two poles and one right half plane zero (Miller effect)

use the dominant 1 2p p

0 1 3

13

22

1 2

1 12 2

2

m DS

pds L out L

mp

A g r

fr C R C

gfC C

use the dominant pole approximation


1 2

1

1

1

2

2

2

mzp

m

L

C Cgf

CgGBW

C

Common source amplifiers – symmetrical cascode

a cascode input stage loaded with another cascode current source

the operating point is found by matching the currents → intersection of the two current source output characteristics

Recall transistor biasing in the Recall transistor biasing in the cascode current source and carefully consider voltage budget !



the output voltage range is defined by the lowest allowed voltage drops across the two cascode current sources → all transistors must be biased in saturation

the nearly vertical slope suggests very high gain

even for small input voltages the very high gain may cause clipping (distortion) at the even for small input voltages the very high gain may cause clipping (distortion) at the output → both the input and the output voltage ranges are limited

min 2out DSatV V


max 2out DD DSatV V V




similar calculations as for the cascode input amplifier, but r is replaced with R similar calculations as for the cascode input amplifier, but rDS3 is replaced with Rp

22 2

2

2 22 2 1 1

0out S outm GS

DS p

out S Sm GS m GS

V V Vg Vr R

V V Vg V g Vr r

3 3 4p m DS DSR g r r

R


2 2 1 12 1

m GS m GSDS DS

g V g Vr r

0 1 2 2 1 3 3 4||m out

m m DS DS m DS DS m outG R

A g g r r g r r G R

pR

The gain is typically larger than 60dB due to Rout !




322 2

2

2 1 221 2 2 2 1 1

2 1

10

1

out pout Sm GS

DS p

S DSout Sin S m GS m GS

DS DS

V sR CV Vg Vr R

V sr CV VsC V V g V g Vr r


101

1

2 3 1 23

2 1 2

11( )

1 1 1

m outzpm

outout

m p p

sC Ag R sg

A sR C C C s ss R C s

g


use the dominant pole approximation1 2p p

0 1 2 2 1 3 3 4

1

22

||

12

2

out

m m DS DS m DS DS

R

pout L

mp

A g g r r g r r

fR C

gfC C

pole approximation


1 2

1

1

1

2

2

2

mzp

m

L

C Cgf

CgGBW

C

Common source amplifiers – folded cascode

similar to the classical cascode input configuration but the input stage is folded → useful in low voltage applications

the operating point is found by matching the currents → intersection of the two current source output characteristics

Recall transistor biasing in the cascode current source and carefully consider voltage budget !

folded cascode input stage



the output voltage range is defined by the transistor biasing requirements → all transistors must be biased in saturation

the input and output voltage ranges are similar with the cascode input case

min

max 2out DSat

out DD DSat

V VV V V





M is an auxiliary source → g V also eliminated from the small signal model M4 is an auxiliary source → gm4VGS4 also eliminated from the small signal model

22 2

2 3

2 22 2 1 1

2 1 4

0

||

out S outm GS

DS DS

out S Sm GS m GS

DS DS DS

V V Vg Vr r

V V Vg V g Vr r r


2 1 4||DS DS DSr r r

3 2 2 1 40 1

3 2 2 1 4

||||

m

out

DS m DS DS DSm m out

DS m DS DS DSGR

r g r r rA g G R

r g r r r




3 322 2

2 3

2 1 4 221 2 2 2 1 1

2 1 4

10

1 ||||

out DSout Sm GS

DS DS

S DS DSout Sin S m GS m GS

DS DS DS

V sr CV Vg Vr r

V s r r CV VsC V V g V g Vr r r


101 3

1

2 3 3 1 23 3

2 1 2

11( )

1 1 1

m DSzpm

DSDS

m p p

sC Ag r sg

A sr C C C s ss r C s

g


use the dominant pole approximation1 2p p

0 1 3

13

22

1 2

12

2

m DS

pDS L

mp

A g r

fr C

gfC C

pole approximation


1

1

1

2

2

mzp

m

L

gfCgGBW

C

Bibliography

P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002

B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002

D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996

P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits, Wiley,2009

R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010


analog integrated circuits fundamental building · pdf fileanalog integrated circuits...

Documents