Analysis and Design of Ultra-Wideband Low-NoiseAmplifier With Input/Output Bandwidth

Optimization and Single-Ended/Differential-Input Reconfigurability

Boyu Hu, Student Member, IEEE, Xiao Peng Yu, Member, IEEE,Wei Meng Lim, and Kiat Seng Yeo, Senior Member, IEEE

Abstract—A CMOS low-noise amplifier (LNA) for ultra-wideband universal radio is presented. Based on capacitive cross-coupled dual-gm-enhancement topology, the circuit topologycould be reconfigured as different versions for single-ended ordifferential inputs. One possible input/output resonant scheme isanalyzed and may help the LNA to exhibit input matching, lownoise, and flat gain in an ultra-wide frequency band with relativelylow power consumption. Both a differential-input-differential-output and a single-ended-input-differential-output version arefabricated in 0.18 μm CMOS technology. The differential-inputversion achieves an 11–14 dB S21, ≤ −9 dBS11 within 1.4–11.4 GHz, and a minimum noise figure of 3.9 dB; the single-ended-input version achieves a 5–8 dB S21, ≤ −10 dBS11 among2.4–11.7 GHz, and a minimum noise figure of 6.3 dB.

Index Terms—Low-noise amplifier (LNA), radio frequency in-tegrated circuit (RFIC), ultra-wideband.

I. INTRODUCTION

RADIO FREQUENCY integrated circuits (RFICs) are keycomponents in nowadays industrial applications. Among

all these applications, ultra-wideband transceiver is one of themost challenging parts which offer high-speed and low-powerwireless link [1]–[3]. Many previous subsystem or buildingblocks have been reported in CMOS technology, which offersa high level of integration [4]–[9]. Recently, the bloomingdevelopment of universal radio-on-a-chip solutions, which suitsfor soft-ware-defined radio or cognitive radios system require-ments, calls for very wideband RF front-ends with applicationflexibility [10], [11].

Placed in front of the whole receiver, a high performancewideband low-noise amplifier (LNA) with certain flexibility tothe input signal is very critical. Hence, many high performance

Fig. 1. Reconfigurable wideband front-end in its different versions for single-ended/differential inputs.

low noise amplifiers have been reported in recent years [12]–[29]. In general, differential signal is highly preferred in asystem-on-chip environment due to its larger dynamic rangeand higher common mode rejection ability. However, since thereceived signal from antenna is usually single ended, certainstrategies should be adopted to convert this signal into differ-ential mode. A single-ended LNA can be used together with asingle-to-differential converter to provide differential signal tothe mixer and the remaining receiver chain. A differential LNAcan also be used together with an external on-board balun toconvert the signal into differential before amplifying. However,each of these two strategies has its own pros and cons. Oneeffective solution is to make the LNA flexible to either single-ended or differential-input signals with differential output. Asshown in Fig. 1, if a front-end can be compatible with single-ended/differential inputs by reconfiguring, the received signalfrom antenna can either go directly into the LNA or convert intodifferential signal using an on-board balun before going intothe LNA [12]. By doing so, much flexibility can be providedwhile dealing with different standards. Combining this input re-configurability within ultra-wideband LNA calls for intelligentdesign techniques to maintain both input matching and voltagegain flatness at a reasonable level with either its single-ended ordifferential-input version.

This paper analyzes one ultra-wideband differential-outputLNA topology, the input of which could be either single-ended or differential signals in its different versions. Onesimilar design employing the capacitive-cross-coupled dual-gm-enhancement topology for differential/single-ended-inputcompatibility has been reported for DVB-H tuner front-enddesign, but only covers a limited frequency range from0.15 GHz to 1 GHz due to its applications [12]. One possibleinput/output resonant scheme, which may allow wideband input

Fig. 2. Reconfigurable ultra-wideband low-noise amplifier.

matching and output voltage gain flatness within a single stagefor power efficient design, is analyzed here. In addition, onematlab-based optimization scheme is analyzed, which may helpthe design at the initial stage.

Section II analyzes ultra-wideband LNA design techniquesand possible bandwidth optimization scheme, Section III dis-cusses the experiment results, and Section IV concludes thiswork.

II. ULTRA-WIDEBAND LNA ANALYSIS

A. Ultra-Wideband LNA Design Techniques

Fig. 2 shows the schematic of the LNA topology. CapacitorC1 and C2 connect the source of M1 and M2 to the gateof each other and form the first gm-enhanced pair. Whenconnecting two inductors Ld1 and Ld2 to the source of M1 andM2, this circuit is configured as a gm-enhanced common gatedifferential LNA with a second-order LC-matching network infront [12], [14]. The effective transconductance of both M1 andM2 is doubled without any additional dc power consumptiondue to the capacitive-cross-coupled opposite signal from eachother of the differential-input signal. When connecting only oneinductor Ls1 to the source of M1, leaving the source of M2

short to ground, M1 and M2 work as a common gate input stageand common source input stage, respectively. The LNA is thenconfigured as a single-ended-input differential output Balun-LNA [12]. Ld1,2/Ls1 could be placed on-board to provide fullreconfigurability, or they could be placed on-chip if the targetedinput version has been fixed and a higher integration level is

Fig. 3. Input matching for single-ended/differential inputs [12].

needed. As shown in Fig. 3, without considering the frequencycharacteristic, the input impedance of both single-ended anddifferential mode can be estimated as

Zin ≈(

1

2gm1,2+

1

2gm1,2

)(1)

where gm1,2 is is the transconductance of M1,2. The volt-age gain of both single-ended and differential mode from thesource/gate of input pair to the LNA’s output without consider-ing frequency characteristic can be estimated as

Hout =Zin

Rs + Zin2gm1,2R1,2 (2)

where R1,2 are the resistance loading at the output.It can be seen from (1) and (2) and Fig. 3, due to the

capacitive cross-coupling at the input, the input impedance andvoltage gain of the LNA for both single-ended and differentialmode could be the same.C3 and C4 connect the source of the cascade transistor M3

and M4 to each other’s gate, forming a second gm-enhancedpair that balances both output differential signal and reducesthe noise contribution from M1 −M4[12].

In this paper, an ultra-wideband LNA topology with cer-tain input reconfigurability is targeted. Bandwidth optimizationtechnique needs to be properly chosen in order to broadenthe working frequency range of the existing single-ended/differential-input ccompatible architecture. Using single-resonant tank for bandwidth optimization may not be enough inultra-wideband applications. Past literatures have reported someideas of using multiresonant instead of single-resonant tank.

As shown in Fig. 4(a), [13] proposed a parallel source-degenerated common source transistors to make a dual-resonantinput stage with two peakings at f1 and f2. [15] proposed aT-coil-based output load to make a dual-resonant output stagewith two peakings at f3 and f4 and use one-resonant tank atinput for staggered compensation, as shown in Fig. 4(b). How-ever, both input/output bandwidth optimization may be moreexpected for ultra-wideband LNA design instead of only inputor output bandwidth optimization under certain conditions. Inaddition, bandwidth optimization should be kept within onestage for power-efficiency consideration.

Thus, one possible single stage, input/output bandwidthoptimization scheme is analyzed in this work. The topologyis similar to some of the literature works [12], [22] and itsdifferential-input version topology was first reported in [26].However, in this work, the architecture is explained in detailwith clearer input/output resonant concept and possible opti-mization scheme analysis together with silicon prototypes.

Fig. 4. (a) Dual-resonant input matching proposed in [13]. (b) Dual-resonantoutput loading proposed in [15]. (c) Input/output resonant scheme analyzed inthis work.

As shown in Fig. 2, load Inductor L3 and L4, together withresistor R1 and R2, form the low quality factor 2nd-order shuntpeaking load, which extends the working frequency band of theLNA. Interstage inductors L1 and L2, together with parasiticcapacitance Cp1 at the drain of the input pair M1,2 and Cp2

at the source of the cascade pair M3,4, form a 2nd-order π-type resonant tank. This interstage-peaking technique has beenused in previous ultra-wideband LNA design [22], but the mainpurpose there is to eliminate the noise leakage of the cascadestage at high frequency. Its impact on the LNA’s bandwidthis not fully emphasized. In this paper, its possible usage forbandwidth optimization is analyzed. As shown in Fig. 4(c),this resonant tank has an effect of resonant feedback to theinput and resonant feedforward to the output. Together with theoriginal resonant tank located at input and output, multiresonantat input/output may be expected under certain conditions, whichmay enhance the input matching and gain performance of thewhole LNA within its working bandwidth.

Reconsider the input impedance among wide band fre-quency, it can be derived as

HZ1(s) =

1

sCp1//sLd1 (3)

HZin(s) =

1

g′m1,2

//HZ1(s) =

sLd1

1 + (g′m1,2 + sCp1)sLd1

=kZin

sQZin

ωnZin

sωnZin

2 + sQZin

ωnZin+ 1

(4)

1

g′m1,2

=ro1 +HZL

(s)

1 + gm1,2ro1(5)

ωnZin=

√1

Ld1Cp1QZin

=

√Cp1

Ld1

ro1 +HZL(s)

1 + gm1,2ro1

kZin=

1

g′m1,2

(6)

Fig. 5. Small-signal equivalent model for (a) input resonant network withintrinsic feedback and (b) output resonant network with cascade feedforward.

where ro1 is the intrinsic output resistance of M1, Cp1−Cp3 arethe parasitic capacitance at the source and drain of M1, and alsothe source of M3. ZL is the interstage load at the drain of M1,2.

Generally, without considering ro1’s feedback effect, a com-mon gate input LNA will have one resonant tank Z1, which iscomposed of Ld1, Cp1, and 1/gm1,2. Its expression is shown in(3) and (4). Equations (5) and (6) derive the natural frequencyand quality factor of this 2nd-order system. By properly placingtwo complex poles, this 2nd-order bandpass resonant tank couldkeep its impedance around targeted value within a certainfrequency band to meet the S11 requirement of the LNA. Thisinput-matching scheme is adopted in many of the previouslyreported common-gate wideband LNA designs.

However, the feedback effect of ro1 may not be simplyignored in wideband common-gate LNA design under someconditions, which is mainly due to two reasons. First, as theCMOS technology goes into deep-submicro, the intrinsic out-put impedance of the transistor decreases sharply. Second, theinput transistor of an LNA is usually biased at a relatively highcurrent-density level and configured as multifinger minimumchannel length transistors in parallel for high-performance de-sign, which further brings the output impedance of the inputtransistor down. As shown in Figs. 4(c) and 5(a), ro1 acts asan intrinsic feedback resistor, which effectively couples theimpedance frequency response at the drain of the input stageback to its source, thus affecting the input matching. From (6),it can be seen that while the nature frequency remains the same,this intrinsic feedback introduces a frequency variation termHzL(s) into Qzin. Equation (5) also indicates that this loadingeffect can be modeled as a series combination of 1/gm1,2 andthe interstage LC network with a scale ratio of 1/gm1,2ro1.For conventional cascade common gate input stage, HzL(s) isshown in (7) as H ′

zL(s), which is a purely capacitive single-pole rolling-off system. When being feedback, this capacitiveloading degrades the input bandwidth performance. Unlike the1st-order capacitive load, interstage peaking introduces a 2nd-order π-type resonant tank and it takes place of the capacitiveterm, as expressed in (8). Putting (8) into (4) can get the5th-order expression of the input impedance considering theintrinsic feedback effect, the simplified expression as shownin (9) and (10). As stated previously, the input impedance isnow affected by both Z1 and Z2. If the parameters of thesetwo resonant tanks are properly arranged, e.g., by placing thecenter resonant frequency of Z1 at relatively low frequency

Fig. 6. Simulated input impedance with and without intrinsic-feedback effectbased on LNA’s ideal small-signal equivalent model.

and Z2 at relatively high frequency, a better in-band inputimpedance matching with less variation may be expected undercertain conditions. Fig. 6 shows the simulated input impedancewith and without considering the intrinsic feedback effect ofinterstage resonant tank Z2 based on the LNA topology’s equiv-alent ideal small-signal models for illustration. It is observedthat with this intrinsic feedback, multiresonant at input stagemay appear, and the magnitude of the input impedance maybe kept within a certain range around the targeted value for arelatively wider frequency range comparing that with single-resonant under certain conditions. In other words, the inputimpedance could be considered as being “boosted” at higherfrequency and thus a better matching performance may showup within the targeted frequency range under certain conditions

H ′ZL

(s) =1

s(Cp2 + Cp3)gm3,4(7)

HZL(s)

=s2L1Cp3 + 2sL1gm3,4 + 1

s3L1Cp2Cp3 + s2L1Cp2gm3,4 + s(Cp2 + Cp3) + gm3,4

(8)

HZin(s) =A4s

4 +A3s3 +A2s

2 +A1s

B5s5 +B4s4 +B3s3 +B2s2 +B1s+B0(9)

A4 = Cp2Cp3L1Ld1ro1A3 = Cp3L1Ld1 + Cp2L1Ld1gm3,4ro1

A2 = L1Ld1gm3,4 + (Cp2 + Cp3)Ld1ro1

A1 = Ld1(1 + gm3,4ro1

B5 = Cp1Cp2Cp3L1Ld1ro1B4 = Cp1Cp3L1Ld1 + Cp2Cp3L1Ld1

+ (Cp1Cp2L1Ld1gm3,4ro1

B3 = Cp1L1Ld1gm3,4 + Cp2L1Ld1gm3,4 + Cp2Cp3L1

+ (Cp1 + Cp2 + Cp3)Ld1 + Cp2L1Ld1gm1,2gm3,4ro1B2 = Cp3L1 + (Cp1 + Cp2 + Cp3)Ld1

+ ((Cp2 + Cp3)Ld1gm1,2 + Cp1Ld1gm3,4) ro1

B1 = (L1+Ld1)gm3,4+(Cp2+Cp3)ro1+Ld1gm1,2gm3,4ro1

B0 = gm3,4ro1 + 1. (10)

The gain performance of the LNA is affected by all of thethree resonant tanks within the given single-stage architecture.Equation (11) shows the voltage gain expression of the LNA.The interstage resonant tank Z2 affects the voltage gain in two

Fig. 7. Simulated gain with cascade-resonant effect based on LNA’s idealsmall-signal equivalent model.

folds: it should help to keep the wideband input matching to-gether with the resonant tank Z1 at input by intrinsic feedback;it should also help to broaden the output frequency range byfeedforward cascading with the resonant tank Z3 at output.Equations (12) and (13) present the expression of Z2 and Z3’simpact on the voltage gain of the LNA. Equation (14) statesthe natural frequency and quality factor, as well as the zero ofthis two cascaded 2nd-order systems. As shown in Fig. 7, ifthe natural frequency and quality factor, as well as the zero ofZ2 and Z3, could be properly optimized, such as placing Z3

at relatively low frequency and Z2 at higher frequency whilestill keeping reasonable input-matching condition regarding theplacement of Z1, a wideband output voltage gain with goodflatness could be expected

Hout(s) =

(1

Rs + Zin(s)− Zin(s)

(Rs + Zin(s))Z1(s)

)×Hα(s)HZ3

(s) (11)

Hα(s) =1

s2L1Cp2 +s(Cp2+Cp3)

gm3,4+ 1

=1

sωnα

2 + sQαωnα

+ 1(12)

HZ3(s) =

1

sCp4//(sL3 +R1) =

sL3 +R1

s2L3Cp4 + sR1Cp4 + 1

=k(s+ ωz)

sωnZ3

2 + sQZ3

ωnZ3+ 1

(13)

ωnα =1√

L1Cp2

, Qα =gm3,4

√L1Cp2

Cp2 + Cp3

ωnZ3=

1√L3Cp4

QZ3=

1

R1

√L3

Cp4, ωZ =

R1

L3. (14)

B. Bandwidth Optimization Scheme

Equations (3)–(14) present the essential analytical expres-sions for input matching and voltage gain design of the ultra-wideband LNA based on its ideal small-signal equivalentmodel. Input/output bandwidth optimization calls for iterationsbetween the input and output network parameter tuning. Thus,one possible matlab-based optimization scheme for estimationat initial stage is analyzed here.

Fig. 8. (a) Sweeping proper Ld1,2 for input bandwidth optimization.(b) Sweeping proper L1,2 for input bandwidth optimization. (c) Sweepingproper L3,4 based on a qualified set of L1,2 and Ld1,2 for output gainbandwidth optimization.

In addition to input/output bandwidth, the design of LNAalso requires noise, gain, and linearity considerations. All ofthese considerations are related to the proper sizing and biasingof the transistors, hence affecting the transconductance andparasitic capacitors, which appear as the design parametersin (3)–(14). One possible design scheme is to optimize thetransistor sizing and biasing first, according to the noise, gain,and linearity performance during the initial iteration and then tooptimize the input/output bandwidth by using proper inductorvalues of Ld1,2, L1,2, and L3,4. Finally, verify whether theinitial iteration and the input/output bandwidth optimization fitthe system requirements. Perform a few iterations if the systemspecification is not achieved during first trial.

By this scheme, after fixing the size and biasing conditionof all the transistors and fitting their other parameters such asparasitic capacitance and output resistance by some preliminarytechnology-related Spice simulations, the design parametersin (3)–(14) may be reduced to Ld1,2, L1,2, and L3,4 only.Thus, the input/output bandwidth optimization problem may beconsidered as a linear programming problem stated in

Target‖fmax_out − fmin_out‖ ≥ fbandwidth_out‖fmax_in − fmin_in‖ ≥ fbandwidth_in (15)

Subject toL1,2, L3,4, Ld1,2 ∈ (Lmin, Lmax) (16)‖|HZin

(jf)| − |HZin0‖ |L1,2,Ld1,2

≤ ΔHZin

f ∈ (fmin_in, fmax_in) (17)‖|Hout(jf)| − |Hout0‖ |L1,2,Ld1,2,L3,4

≤ ΔHout

f ∈ (fmin_out, fmax_out). (18)

The target is to find the optimized input/output bandwidth,(fmax_out − fmin_out) and (fmax_in − fmin_in) among allthe available L1,2, Ld1,2, and L3,4 values, as stated in (17)and (18), and also being conceptually demonstrated in Fig. 8.Certain constraints should be put upon this search. First, theinductor value of L1,2, L3,4, and Ld1,2 should be kept withina certain range for realistic on-chip implementation, as pre-sented in (16). Second, as shown in Fig. 9(a) and (b), for a

Fig. 9. (a) Output bandwidth optimization. (b) Input bandwidth optimization.

given ultra-wideband LNA design, the variation of both inputimpedance and voltage gain should be kept within a certainrange around the target specifications, for example Hzin0 + /−ΔHzin and Hout0 + /−ΔHout, in (17) and (18). For a set ofL1,2, Ld1,2, and L3,4 values that satisfy (17) and (18), they maybe selected as the optimum design parameter at the intial stage.

In more detail, the optimization procedure could be dividedinto three basic steps.

Step 1: Do initial parameter estimation. As analyzed in theabove, the sizing and biasing of transistors could be op-timized first according to the requirements of gain, noise,linearity, and power consumption. Input stage transconduc-tance gm1,2 could be set to meet input matching require-ment in (1). Output resistor load R1,2 could then be setfor gain (2) and noise figure (19)–(21) requirements. Then,the bias current density could be optimized for linearity[27] and power consumption considerations. After theseinitial deductions, the design parameters of Cp1,2, Cp3,4,gm1,2, gm3,4, R1,2, and ro1,2 may be fixed as an initial startpoint, leaving L1,2, Ld1,2, and L3,4 as the unknown designparameters.

Step 2: Input/output bandwidth optimization. For an ultra-wideband LNA design, an initial frequency boundary(fmin, fmax) for the input/output should be set as astarting point for the optimization procedure. Then,the targeted input impedance and voltage gain valueshould be set as Hzin0 and Hout0. In addition, thevariation tolerance among the bandwidth should be setas ΔHzin and ΔHout. The value of L1,2, Ld1,2, andL3,4 is chosen within a certain range (Lmin, Lmax). Forinput bandwidth optimization, twofold loop search ofLd1,2 and L1,2 could be implemented, and a group ofqualified Ld1,2 and L1,2 values that satisfy the presetinput-bandwidth target fbandwidth_in could be saved.After the input-bandwidth optimization, for each pair ofthe qualified value of Ld1,2 and L1,2, one loop search ofL3,4 could be implemented to further optimize the outputgain performance. For input bandwidth optimization, dueto its bandpass characteristic, for each pair of Ld1,2 andL1,2, the 1st positive cross of the transfer function overthe boundary of Hzin0 −ΔHzin could be set as fmin_zinand the last negative cross of the transfer function over theboundary of Hzin0 −ΔHzin could be set as fmax_zin.Similarly, for output bandwidth optimization, due toits bandpass characteristic, for each pair of qualifiedLd1,2 and L1,2, which is obtained from input-bandwidthoptimization, L3,4 could be loop searched. And for each

Fig. 10. (a) gm-boosting for differential-input noise reducing. (b) Noisecancelling for single-ended-input noise reducing.

L3,4, the 1st positive cross of the transfer function overthe boundary of Hout0 −ΔHout could be set as fmin_out

and the last negative cross of the transfer function over theboundary of Hout0 −ΔHout could be set as fmax_out.For each pair of (fmin_zin, fmax_zin), if there is nofrequency f in between such that ‖Hzin(f)−Hzin0‖ ≥ΔHzin, (Ld1,2, L1,2, fmin_zin, fmax_zin) could be storedas one cell of qualified_set_input. Based on the Ld1,2,L1,2 in qualified_set_input, gain performance couldbe further optimized by searching proper L3,4. For eachpair of (fmin_out, fmax_out) that satisfies the presetoutput bandwidth fbandwidth_out, if there is no frequencyf in between such that ‖Hout(f)−Hout0‖ ≥ ΔHout,(L1,2,L3,4,Ld1,2, fmin_zin, fmax_zin, fmin_out, fmax_out)could be stored as one cell of qualified_set_total.

Step 3: for each cell in qualified_set_total, calculateinput_bandwidth, output_bandwidth, centre_freq_inand centre_freq_out. Then, to verify whether these meetthe LNA system specifications. If not, an iterative could beadopted starting from the initial parameter estimation.

With appropriate initial parameter estimation, this bandwidthoptimization scheme may provide relatively reasonable rangeestimation of Ld1,2, L1,2, and L3,4 values, which leads to opti-mized input and output bandwidth to the first order. It should benoticed that since simplified inductor/capacitor/transistor mod-els are adopted in the numerical calculation, the matlab-basedinput/output optimized scheme may provide optimistic re-sults comparing with real inductor/capacitor/transistor-includedcircuit-level design in some cases. However, this optimizationprocedure still offers initial estimation, which can be used asa reasonable initial starting point for the transistor-level circuitdesign at the later stage.

C. Noise Analysis

When being reconfigured for either differential input orsingle-ended input, the circuit topology of the LNA changesand thus the noise analysis need to be implemented separately.

For the differential-input version, as shown in Fig. 10(a), theinput stage transistors are capacitive-cross-coupled. Thus, thewell-known gm-boosting technique [14] forms here to reducethe noise and power consumption. Physically remaining thesame value, the effective transconductance when looking intothe source of M1,2 doubles due to the opposite input signal fedto the gate of M1,2.

The noise factor expression for the proposed LNA underinput matching condition in differential-input mode can begiven as (19)

FDiff =1 +4kTγgm1,2

Rs/2Rs/2+1/2gm1,2

2R1

2 + 4kTR1

4kTRs/2

Rs/2Rs/2+1/2gm1,2

2R1

2

=1 +γ

2+

2

gm1,2R1(19)

Vn,M1out=Vn,M1_path1

− Vn,M1_path2

= −√4kTγgm1,2

Rs

1/gm1,2 +RsR1

+√

4kTγgm1,2Rs/gm1,2

1/gm1,2 +RsR1

=0 (20)

FSE =1 +4kTγgm1,2R1

2 + 8kTR1

4kTRsgm1,22R1

2

=1 + γ +2

gm1,2R1. (21)

Due to the gm-boosting of the input differential pair, whichdominates the noise performance of the LNA, the noise contri-bution can be halved in theory, as shown in (19). In reality, thefeedforward gain for boosting may be less than 1, due to thecapacitive dividing effect between the cross-couple capacitorand the parasitic capacitor at the gate of the input transistors.Hence, the effective noise performance improvement should beless than the theoretical estimation.

For the single-ended version, in Fig. 10(b), the gm-boostingof the input stage no longer exists due to the lack of differential-input signal. However, the LNA reconfigures as an active-balunnow. The noise current in M1 will appear at the differentialoutput through two paths. Path1 goes into the source of M1,then go through M3 to Vout+ as Vn_M1_path1. Path2 firstbeing converted to Vnin, then amplified by the common sourcecascade M2 and M3 and appears at Vout− as Vn_M1_path2.As shown in (20), due to the balanced output voltage gain,the differential output noise generated by M1 exhibits thesame magnitude and polarity. Since these two output noiseare correlated, they can be cancelled out at the differentialoutput theoretically, which resembles the noise-cancelling tech-nique [28]. (21) presents the noise factor expression for single-ended version. Though lacking of gm-boosting at the input,the employed noise-cancelling technique still partly reduces thedominant noise contribution from the input stage, thus keepingthe total noise performance at a reasonable level [12].

It should be noticed that in both (19) and (21), the noiseestimation factor is inverse proportional to the voltage gainof the LNA. This should be included in the design parameterinitial estimation of the input/output bandwidth optimizationprocedure.

Fig. 11. Die photo of differential-input version.

Fig. 12. Die photo of single-ended-input version.

III. EXPERIMENT RESULTS

Both the differential-input and single-ended-input version ofthe LNA are fabricated in Tower Jazz 0.18um SiGe technology,of which only CMOS transistors are used for this design.Figs. 11 and 12 show the chip photograph of the LNA inboth differential-input and single-ended-input versions. Outputbuffers are included on-chip to drive the external 50 ohm loadof the measurement equipment. Input inductors are directlyimplemented on-chip and on wafer measurement is performedto characterize the LNA.

Fig. 13 shows the Scattering (S) parameters of bothdifferential-input and single-ended-input versions. The inputreflection coefficient S11 is less than −9 dB and the S21 isamong 11 dB-14 dB from 1.4-11.4 GHz in differential-inputmode; while the input reflection coefficient S11 is less than−10 dB and the S21 is among 5 dB–8 dB from 2.5 to 11.7 GHzin single-ended-input mode.

Fig. 14 shows the noise figure performance of the two LNAs.For the differential-input LNA, external wideband baluns areemployed at both the input and output of the LNA to properlyconnect it with the noise figure measurement equipement. Forthe single-ended-input LNA, only one wideband balun is em-ployed at the output. The insertion loss introduced degradationdue to the balun at LNA’s input has been de-embeded from theresult. In differential-input version, the noise figure is between3.9 dB and 4.5 dB from 3 to 10 GHz; in single-ended version,it is between 6.3 dB and 6.8 dB.

Fig. 13. S21 andS11 performance of both single-ended/differential-input LNAs.

Fig. 14. Noise figure performance of both single-ended/differential-input LNAs.

Fig. 15. P1dB performance of single-ended-input LNA.

TABLE ICOMPARISON WITH LITERATURES

Due to the lack of multiple signal sources, the linearityperformance of the LNA is measured with 1 dB compressionpoint. As shown in Fig. 15, the P1dB performance is −11 dBmin single-ended version, which is measured at 9 GHz. Basedon this, the equivalent IIP3 could be estimated as −1 dBm insingle-ended version.

The performance of the proposed LNA is summarized andcompared with previous works [12]–[25] in Table I.

IV. CONCLUSION

An ultra-wideband LNA topology, which provides cer-tain reconfigurability for differential/single-ended inputs, hasbeen presented. By adopting capacitive-cross-coupled dual-gm-enhancement topology, the circuit topology could either beconfigured as an ultra-wideband differential-input differential-output gm-enhanced LNA or a single-input differential-outputbalun-LNA in its different versions. One possible input/outputresonant scheme by intrinsic feedback and cascade feedfor-ward and its possible usage for the input impedance matchingand output voltage gain range optimization is analyzed. Onepossible matlab-based optimization scheme, which may helpthe design at the initial stage, is also analyzed here. This LNAachieves an 11–14 dB S21, ≤ −9 dBS11 among 1.4–11.4 GHzwith a minimum noise figure of 3.9 dB in its differential-inputversion; a 5–8 dB S21, ≤ −10 dBS11 among 2.5–11.7 GHzwith a minimum noise figure of 6.3 dB in its single-endedversion. The one-stage architecture makes it consume a rela-tively low power of 8 mW (estimated core circuit) excludingthe auxillary bias-circuits and on-chip buffers.

REFERENCES

[1] J. P. Carmo, P. M. Mendes, C. Couto, and J. H. Correia, “A 2.4-GHzCMOS short-range wireless-sensor-network interface for automotive ap-plications,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1764–1771,May 2010.

[2] J. Lee, D. Vo, Q. Huynh, and S. Hong, “A fully integrated HF-band passiveRFID tag IC using 0.18-μm CMOS technology for low-cost securityapplications,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2531–2540,Jun. 2011.

[3] Y. Kim, Y. Choi, M. Seo, S. Yoo, and H. Yoo, “A CMOS transceiver for amultistandard 13.56-MHz RFID reader SoC,” IEEE Trans. Ind. Electron.,vol. 57, no. 5, pp. 1563–1572, May 2010.

[4] J. L. and S. Hasan, “Design and performance analysis of a 866-MHzlow-power optimized CMOS LNA for UHF RFID,” IEEE Trans. Ind.Electron., vol. 60, no. 5, pp. 1840–1849, May 2013.

[5] H. Xie, X. Wang, L. Lin, H. Tang, Q. Fang, H. Zhao, A. Wang, F. Yao,A. Wang, Y. Zhou, and B. Qin, “A 52-mW 3.1-10.6-GHz fully integratedcorrelator for IR-UWB transceivers in 0.18 μm CMOS,” IEEE Trans. Ind.Electron., vol. 57, no. 5, pp. 1546–1554, May 2010.

[6] B. Qin, X. Wang, H. Xie, L. Lin, H. Tang, A. Wang, H. Chen, B. Zhao,L. Yang, and Y. Zhou, “1.8 pJ/pulse programmable Gaussian pulsegenerator for full-band noncarrier impulse-UWB transceivers in 90-nmCMOS,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1555–1562,May 2010.

[7] X. Wang, X. Guan, S. Fan, H. Tang, H. Zhao, L. Lin, Q. Fang, J. Liu,A. Wang, and L. Yang, “ESD-Protected power amplifier design in CMOSfor highly reliable RF ICs,” IEEE Trans. Ind. Electron., vol. 58, no. 7,pp. 2736–2743, Jul. 2011.

[8] Y. Yao, J. Wu, Y. Shi, and D. F. F., “Fully integrated 900-MHz passiveRFID transponder front end with novel zero-threshold RFCDC rectifier,”IEEE Trans. Ind. Electron., vol. 56, no. 7, pp. 2317–2325, Jul. 2009.

[9] R. Rodriguez, J. A. Delgado-Restituto, J. Masuch, A. Rodriguez-Perez,E. Alarcon, and A. Rodriguez-Vazquez, “An ultralow-power mixed-signalback end for passive sensor UHF RFID transponders,” IEEE Trans. Ind.Electron., vol. 59, no. 2, pp. 1310–1322, Feb. 2012.

[10] V. V. Kulkarni, M. Muqsith, K. Niitsu, H. Ishikuro, and T. Kuroda, “A750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB transmitter with em-bedded on-chip antenna,” IEEE J. Solid-State Circuits, vol. 44, no. 2,pp. 394–403, Feb. 2009.

[11] H. J. Kim, J. U. Kim, J. H. Kim, H. Wang, and I. S. Lee, “The designmethod and performance analysis of RF subsampling frontend for SDR/CR receivers,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1518–1525,May 2010.

[12] M. C. Kuo, C. N. Kuo, and T. C. Chueh, “Wideband LNA compatiblefor differential and single-ended inputs,” IEEE Microw. Wireless Compon.Lett., vol. 19, no. 7, pp. 482–484, Jul. 2009.

[13] B. Y. Chi, Z. Chun, and Z. H. Wang, “Bandwidth extension forultra-wideband CMOS low-noise amplifiers,” in Proc. ISCAS, 2008,pp. 968–971.

[14] X. Y. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate LNAand differential Colpitts VCO/QVCO in 0.18 m CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.

[15] S. Sudip, W. Jeffrey, and D. J. Allstot, “Bandwidth extension techniquesfor CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 41, no. 11,pp. 2424–2439, Nov. 2006.

[16] A. Bevilacqua and A. M. Niknejad, “An ultrawideband CMOS low-noiseamplifier for 3.1-10.6 GHz wireless receivers,” IEEE J. Solid-State Cir-cuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004.

[17] C. F. Liao and S. I. Liu, “A broadband noise-cancelling CMO LNA for3.1-10.6 GHz UWB receivers,” IEEE J. Solid-State Circuits, vol. 42, no. 2,pp. 329–339, Feb. 2007.

[18] B. Park, S. Choi, and S. Hong, “A low-noise amplifier with tunableinterference rejection for 3.1-to 10.6 GHz UWB system,” IEEE Microw.Wireless Compon. Lett., vol. 20, no. 1, pp. 40–42, Jan. 2010.

[19] C. Y. Wu, Y. K. Lo, and M. C. Chen, “A 3-10 GHz CMOS UWB low-noiseamplifier with ESD protection circuits,” IEEE Microw. Wireless Compon.Lett, vol. 19, no. 11, pp. 737–739, Nov. 2009.

[20] G. Sapone and G. Palmisano, “A 3-10 GHz low power CMOS low-noise amplifier for ultra-wideband communication,” IEEE Trans. Microw.Theory Techn., vol. 59, no. 3, pp. 678–686, Mar. 2011.

[21] Y. J. Chen and Y. I. Huang, “Development of integrated broad-bandCMOS low-noise amplifiers,” IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 54, no. 10, pp. 2120–2127, Oct. 2007.

[22] H. Zhang, X. Fan, and E. Sinencio, “A low-power, linearized, ultrawide-band LNA design technique,” IEEE J. Solid-State Circuits, vol. 44, no. 2,pp. 320–330, Feb. 2009.

[23] D. Im, I. Nam, H. T. Kim, and K. Lee, “A Wideband CMOS low noiseamplifier employing noise and IM2 distortion cancellation for a digitalTV tuner,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 686–698,Mar. 2009.

[24] C. H. Chen, G. Liu, B. Zdravko, and A. M. Niknejad, “A highly linearbroadband CMOS LNA employing noise and distortion cancellation,”IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1164–1176, May 2008.

[25] M. Reiha and J. Long, “A 1.2 V reactive-feedback 3.1-10.6 GHz lownoiseamplifier in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 5,pp. 1023–1033, May 2007.

[26] B. H. Hu, X. P. Yu, and L. N. He, “0.9-10 GHz low noise amplifier withcapacitive cross coupling,” in Proc. IEEE ICUWB, Sep. 2010, pp. 1–4.

[27] V. Aparin and L. E. Larson, “Modified derivative superposition methodfor linearizing FET low-noise-amplifiers,” IEEE Trans. Microw. TheoryTechn., vol. 53, no. 2, pp. 571–581, Feb. 2005.

[28] F. Bruccoleri, E. Klmperink, and B. Nauta, “Wideband CMOS low-noise-amplifier exploiting thermal noise cancelling,” IEEE J. Solid-State Cir-cuits, vol. 39, no. 2, pp. 275–282, Feb. 2004.

[29] H. Wu, N. Wang, Y. Du, Y.-C. Kuan, F. Hsiao, S.-J. Lee, M.-H. Tsai,C.-P. Jou, and M.-C. F. Chang, “A current-mode mm-wave direct-conversion receiver with 7.5 GHz bandwidth, 3.8 dB minimumnoise-figure and +1 dBm P1dB, out linearity for high data rate Commu-nications,” in Proc. IEEE RFIC Symp., Jun. 2013, pp. 89–92.

Boyu Hu (S’13) received the B.Sc. degree in elec-tronic and information engineering (Hons.) fromChu-Ko-Chen Honors College, Zhejiang University,Hangzhou, China, in 2008, and the M.S. degree incircuits and systems from the Institute of Very LargeScale Integration (VLSI) Design, Zhejiang Univer-sity, Hangzhou, in 2011. Since 2011, he has beenworking toward the Ph.D. degree at the Universityof California, Los Angeles, CA, USA.

Between March and August 2011, he held theposition of RF/Mixed-Signal IC Designer at Marvell,

Shanghai, China, working on low-power wireless transceivers. Since June 2013,he has held the position of Mixed-Signal IC design Intern at Broadcom, Irvine,CA, working on high-precision mixed-signal audio products. His research inter-ests include low-power high-speed data converters, all-digital frequency/clocksynthesizers, mm-wave/sub-mm-wave, and audio/power-management inte-grated circuit and system.

Xiao Peng Yu (M’06) received the B.Eng. degreein optical engineering from Zhejiang University, YuQuan, Hangzhou, China, in 1998, and the Ph.D.degree in radio-frequency integrated circuits designfrom the School of Electrical and Electronic Engi-neering, Nanyang Technological University (NTU),Singapore, in 2006.

Before joining NTU as a Ph.D. candidate in 2002,he was with MOTOROLA Global Telecom SolutionSector, Hangzhou. He joined the College of Electri-cal Engineering, Zhejiang University, Hangzhou, on

September 2006, where he is currently an Associate Professor. Since January2008, he has been with the Eindhoven University of Technology, Eindhoven,The Netherlands, as a Visiting Scholar. Since August 2009, he has been a MarieCurie Fellow (IIF) in TU/e (Co-hosted with Philips Research, Eindhoven).His research interests include silicon-based radio frequency/millimeter-wave integrated circuits design and phase-locked loops for high-speed datacommunications.

Wei Meng Lim received the B.E. (Hons.) and M.E.degrees in circuits and systems from Nanyang Tech-nological University (NTU), Singapore, in 2002 and2004, respectively.

Upon his graduation, he joined NTU as a memberof the Research Staff. His research interests includeRF circuit design, RF device characterization, andmodeling.

Kiat Seng Yeo (SM’09) received the B.Eng. (withHonors) and the Ph.D. degrees in electrical engineer-ing from Nanyang Technological University (NTU),Singapore, in 1993 and 1996, respectively.

He is an Associate Chair (Research) of the Schoolof Electrical and Electronic Engineering, NTU, andBoard Member of the Singapore Semiconductor In-dustry Association. He was the Founding Director ofVIRTUS, a research center of excellence jointly setup by NTU and the Economic Development Board.He has published six books, three book chapters, and

320 international top-tier refereed journal and conference papers, and holds25 patents.

Dr. Yeo serves on the editorial board of IEEE TRANSACTIONS ON MICRO-WAVE THEORY AND TECHNIQUES and holds/held key positions in manyinternational conferences as Advisor, General Chair, Co-General Chair, andTechnical Chair. He was awarded the Public Administration Medal (Bronze) onNational Day 2009 by the President of the Republic of Singapore, and was alsoawarded the distinguished Nanyang Alumni Award in 2009 for his outstandingcontributions to the university and society.