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Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha Chandrakasan Massachusetts Institute of Technology presented at ESSCIRC 2005

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Page 1: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS

Benton H. Calhoun and Anantha Chandrakasan

Massachusetts Institute of Technology

presented at

ESSCIRC 2005

Page 2: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

OutlineOutline

Introduction to Static Noise Margin (SNM)Modeling SNMDependencies of SNMImpact of Variation on SNMConclusions

Page 3: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

0 0.15 0.30

0.15

0.3

Q (V)Q

B (

V)

VTC for inverter 2VTC−1 for inverter 1VTC for inv 2 with V

N=SNM

VTC−1 for inv 1 with VN=SNM

Graphical Method for Finding SNMGraphical Method for Finding SNM

BL BLBWL

M5

M4

M6M3

M1

M2

Q QB

VN

VN

−0.2 −0.1 0 0.1 0.2 0.3−0.2

−0.1

0

0.1

0.2

0.3

Q (V)

QB

(V

)

u axis →y a

xis →

Difference in [u,v]VTC for inv 2VTC−1 for inv 1

Inverter 2Inverter 1

E. Seevinck, F. List, J. Lohstroh,“Static-Noise Margin Analysis of MOS SRAM Cells” JSSC, Oct ‘87.

SNM is length of side of the largest embedded square on the butterfly curve

Page 4: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

SNM during Hold and ReadSNM during Hold and Read

0 0.15 0.30

0.15

0.3

Q (V)

QB

(V

)

Hold

0 0.15 0.30

0.15

0.3

Q (V)

QB

(V

)

Read

BL BLBWL=0

M5

M4

M6M3

M1

M2

1 0

BL prech to 1 BLB prech to 1WL=1

M5

M4

M6M3

M1

M2

1 0

Read SNM is worst-case

Page 5: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

OutlineOutline

Introduction to Static Noise Margin (SNM)Modeling SNMDependencies of SNMImpact of Variation on SNMConclusions

Page 6: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Q

QB

simseqns

VT6

−1σ

Modeling SNM HoldModeling SNM Hold

⎟⎟⎠

⎞⎜⎜⎝

⎛−

++

++

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−+−−

++

=

3

3

1

1

31

31

31

1

1

3

31

31

)/exp(1)/)exp((1lnln

nV

nV

nnnn

nnVn

VQVQV

II

nnnnV

QBTTDD

th

thDD

S

Sth

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛ −−⎟⎟

⎞⎜⎜⎝

⎛ −=

th

DS

th

TGSSD V

VnV

VVII exp1exp

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−−−

+=

⎟⎟⎟

⎜⎜⎜

⎟⎟⎟

⎜⎜⎜

⎛+−+−+=

6

6

4

4

64

6

64

64

2

1lnexp

,4)1(1*5.0ln

nV

nV

VVnV

IIQ

VnnnnG

GeGGVVQB

TT

thth

DD

S

S

th

VV

thDDth

DD

BL BLBWL=0

M5

M4

M6M3

M1

M2

Q QBAssumptions:

In Sub-threshold:

•IM3=IM1•IM6=IM4

Page 7: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Modeling SNM ReadModeling SNM Read

Q

QB

simseqns

VT1

−1σ

BL prech to 1 BLB prech to 1WL=1

M5

M4

M6M3

M1

M2

Q=low QB = high

Assumptionswhen Q is low:

•IM2=IM1•IM6=IM4

( )QVVnnV

VQVQVVn

IIVn

QB

TDDT

th

thDDth

S

Sth

−−++

⎟⎟⎠

⎞⎜⎜⎝

⎛−−+−−

+=

22

11

11

21 )/exp(1

)/)exp((1lnln

Page 8: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

OutlineOutline

Introduction to Static Noise Margin (SNM)Modeling SNMDependencies of SNMImpact of Variation on SNMConclusions

Page 9: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

SNM Dependence on VSNM Dependence on VDDDD

0 0.2 0.4 0.8 1.20

0.2

0.4

0.8

1.2

Q

QB

0 0.2 0.4 0.8 1.20

0.2

0.4

0.8

1.2

Q

QB

Hold Read

Read SNM less sensitive in above VT operation

Page 10: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

SNM Dependence on VSNM Dependence on VDDDD

0 0.2 0.4 0.6 0.8 1 1.20

0.1

0.2

0.3

0.4

0.5

VDD

(V)

SN

M (

V)

HoldReadV

DD/2

VDD noise affects SNM by less than half

Page 11: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

SNM Dependence on TemperatureSNM Dependence on Temperature

−40 0 40 80 1200

0.1

0.2

0.3

0.4

0.5

T (°C)S

NM

(V

)

0 0.3 1.20

0.3

1.2

Q (V)

QB

(V

)

100 °C0 °C

VDD=0.3V VDD=1.2V

Temperature impact not large because it affects pFETs and nFETs similarly

Page 12: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Transistor Sizing Impact on SNMTransistor Sizing Impact on SNM

BL BLBWL

M5

M4

M6M3

M1

M2

Q QB

0 2 4 6 8 100

0.02

0.04

0.06

0.08

0.1

Normalized width

SN

M (

V) Hold

Read

M1,4M3,6M2,4

VDD=0.3V

Sizing impact not so large because of logarithmic impact on VTCs

⎟⎟⎠

⎞⎜⎜⎝

⎛−

++

++

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−−+−−

++

=

3

3

1

1

31

31

31

1

1

3

31

31

)/exp(1)/)exp((1lnln

nV

nV

nnnn

nnVn

VQVQV

II

nnnnV

QBTTDD

th

thDD

S

Sth

e.g.

Page 13: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Cell Ratio and SubCell Ratio and Sub--threshold SNMthreshold SNM

1 1.5 2 2.5 3 3.5 4 4.5 50

0.1

0.2

0.3

0.4

0.5

Cell Ratio

SN

M (

V)

1.2V

0.3V

HoldRead

BL BLBWL

M5

M4

M6M3

M1

M2

Q QB

Cell ratio much less important for sub-threshold SNM

Cell ratio = (W/L)1 / (W/L)2 or(W/L)4 / (W/L)5

Page 14: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

OutlineOutline

Introduction to Static Noise Margin (SNM)Modeling SNMDependencies of SNMImpact of Variation on SNMConclusions

Page 15: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Impact of Mismatch on SNMImpact of Mismatch on SNM

0 0.15 0.30

0.15

0.3

Q (V)

QB

(V

)

Hold

BL BLBWL

M5

M4

M6M3

M1

M2

Q QB

Until now, we have assumed that the two sides of the bitcell are symmetric. With mismatch, that is not true.

SNM is the minimum of SNM high and SNM low, which are different due to mismatch

SNM low

SNM high

Page 16: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

−5 5−3

−1

1

3

5

∆VT4

(σ)

Nor

m. R

ead

SN

M h

igh

Sub−threshold

Single FET VSingle FET VTT mismatchmismatch

−5 5−1

0

1

2

3

∆VT (σ)

Nor

m. R

ead

SN

M h

igh

M1

M6

M5M3

M4

M2

−5 5−3

−1

1

3

5

∆VT4

(σ)

Nor

m. R

ead

SN

M h

igh

Above−threshold

BL BLBWL

M5

M4

M6M3

M1

M2

Q QB

Sensitivity of SNM to single FET mismatch isroughly linear.

Above threshold SNM can use 1st order series model

Cannot use 1st order series model for sub-threshold SNM

Page 17: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Mismatch SNM DistributionsMismatch SNM Distributions

−0.1 0 0.20

200

400

600

SNM high (V)

Hold

Read

−0.1 0 0.20

200

400

600

SNM high (V)

Hold

Read

Random mismatch in all 6 transistors

Minimum WL 4 Minimum WL

Like above-threshold, SNM high and SNM low are normally distributed with threshold voltage mismatch

Page 18: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Modeling PDF for Mismatch Modeling PDF for Mismatch

0 0.1 0.2

0

0.1

0.2

SN

M lo

w

SNM high

SNM Hold

0 0.1 0.2

0

0.1

0.2

SN

M lo

wSNM high

SNM Read

SNM is min(SNM high, SNM low); Tail is most important for yield

If SNMhigh, SNMlow are independent and identically distributed (iid),then the pdf for SNM is:

fSNM=2fSNMhigh(1-FSNMhigh)

SNM high and SNM low are nearly identically distributed, but NOT independent

Page 19: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Simulations Compared to ModelSimulations Compared to Model

−0.1 0.110

−1

100

101

102

103

SNM (V)

0 0.06

1

100

10k

SNM (V)

N=100,500,800,1k,50kModel for N−pt M−C

modelsim

Try the model anyway:fSNM=2fSNMhigh(1-FSNMhigh)

Normal distribution

Model matches well for the worst-case tail

1k model within 3% of 50k model

Model based on short sims is accurate for much longer sims

Page 20: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Global Process Corner VariationGlobal Process Corner Variation

0.02 0.10

1k

2k

SNM (V)

HoldRead

Global variation causes variation in SNM

Page 21: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

Global Variation and Local MismatchGlobal Variation and Local Mismatch

−0.1 −0.05 0 0.0510

0

101

102

103

Read SNM (V)

Occ

urre

nces

Model : no global variationMonte−Carlo : no global varnModel : 3σ global varnMonte−Carlo : 3σ global varn

When mismatch occurs in addition to global variation, the mismatch distribution shifts.

Model still works with global variation and mismatch

Page 22: Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm … · 2011. 9. 27. · Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS Benton H. Calhoun and Anantha

ConclusionsConclusions

SNM limits sub-threshold memory yieldSNM most strongly depends on mismatch and global variationProper modeling for the tail of the SNM distribution allows fast estimation of SNM yield