announcements assignment 6 due tomorrow no assignment 7 yet

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Announcements • Assignment 6 due tomorrow • No Assignment 7 yet

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Page 1: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Announcements

• Assignment 6 due tomorrow

• No Assignment 7 yet

Page 2: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Announcements

• Joe & Ali: Game show Buzzer

• Trisha & Matt: EMG & pedal

• Jamy, Lei, Mark: LED cube: parts?

• Jingliang: Piezoelectric charger

• Eric: Water printer(?)

• Philip &Gaurav: model train (parts?)

Page 3: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Lecture 16 Overview

• Logic gates

• Boolean Algebra

• DeMorgan's Theorem

• Karnaugh maps

Page 4: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Simple gate summary

INPUT OUTPUT

A B A AND B

0 0 0

1 0 0

0 1 0

1 1 1

INPUT OUTPUT

A B A NAND B

0 0 1

1 0 1

0 1 1

1 1 0

INPUT OUTPUT

A B A OR B

0 0 0

1 0 1

0 1 1

1 1 1

INPUT OUTPUT

A B A NOR B

0 0 1

1 0 0

0 1 0

1 1 0

BABA AND

BABA OR BABA NOR

BABA NAND

'or NOT AAA

Page 5: Announcements Assignment 6 due tomorrow No Assignment 7 yet

The XOR gate

C

C=A XOR BC=AB

A B C(in) (in) (out)

0 0 0

0 1 1

1 0 1

1 1 0

The XNOR gate

C

C=A NOR BC=AB

A B C(in) (in) (out)

0 0 1

0 1 0

1 0 0

1 1 1

Page 6: Announcements Assignment 6 due tomorrow No Assignment 7 yet

How to build a digital gate

• We can build an inverter with one switch:

• A NAND gate takes two switches in series:

INPUT=0 INPUT=1

INPUT A

INPUT B

Page 7: Announcements Assignment 6 due tomorrow No Assignment 7 yet

CMOS gates• Gates are very easy to build using MOSFET transistors (recall; transistors can be considered as a voltage controlled switch)• p-type conduct when the input=0• n-type conduct when the input=1

Page 8: Announcements Assignment 6 due tomorrow No Assignment 7 yet

CMOS NAND gate• NAND gates are built using 4 MOSFETs• p-type conduct when the input=0• n-type conduct when the input=1

INPUT OUTPUT

A B A NAND B

0 0 1

1 0 1

0 1 1

1 1 0

Page 9: Announcements Assignment 6 due tomorrow No Assignment 7 yet

CMOS NAND gate• The NAND gate is by far the most important• It is cheapest to construct• It can be used to produce all other logic operations

Page 10: Announcements Assignment 6 due tomorrow No Assignment 7 yet

CMOS NAND gate• The NAND gate is by far the most important• It is cheapest to construct• It can be used to produce all other logic operations

XOR

In general, how do we figure out how to build a complex logic circuit?

Page 11: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Method I: Boolean Algebra

0AA

AAA

A1A

00A

1AA

AAA

11A

A0A

AA

CBA C)(BA CB)(A

A·B·C A·(B·C) (A·B)·C

C)(A · B)(A (B·C)A

(A·C) (A·B) C)A·(B

AB BA

B·A A·B

(B·C) A B·CA

C (A·B) CA·B

A·B AB

(NOR) B · A B)(A

(NAND) B A (A·B)

AND: OR: NOT:

Associative Law: Commutative Law:

Distributive Law:Precedence:

DeMorgan's Theorem:

Page 12: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Complete Rules of Boolean Algebra

0AA

AAA

A1A

00A

AA

CBA C)(BA CB)(A

A·B·C A·(B·C) (A·B)·C

AB BA

B·A A·B

(B·C) A B·CA

C (A·B) CA·B

A·B AB

(NOR) B · A B)(A

(NAND) B A (A·B)

AND: OR: NOT:

Associative Law: Commutative Law:

Distributive Law:Precedence:

DeMorgan's Theorem:

C)(A · B)(A (B·C)A

(A·C) (A·B) C)A·(B

1AA

AAA

11A

A0A

Page 13: Announcements Assignment 6 due tomorrow No Assignment 7 yet

DeMorgan's Theorem Proof

"The contradictory opposite of a disjunctive proposition is a conjunctive proposition composed of the contradictories of the parts of the disjunctive proposition (William of Ockham, Summa Logicae)."

Duality between AND and OR means that any logic function can be implemented by using just OR and NOT gates , or by just AND and NOT gates

OR"break the line, change the sign"

Page 14: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Using the Rules of Boolean Algebra

Example: Simplify the following function:

1XX Use

1XX and

Z)(XY)(XYZX Use

=1

expand this

14 gates

3 gates

Page 15: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Method II: Karnaugh Maps• There are often many solutions available to implement a given logic expression• How do we find the most efficient (least number of gates)?• Use a Karnaugh map. Set up the Karnaugh map like this:

Two inputs; A and B Three inputs; A,B and CThree inputs; A, B and C

4 cells8 cells

8 cells

• Each map consists of 2n cells, where n is the number of inputs (logic variables) • Row and column assignments arranged such that adjacent terms change by only one bit• so: use 00,01,11,10 instead of 00,01,10,11• Makes it easier to identify subcubes

Page 16: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Setting up the Maps

Four inputs; A,B,C and D16 cells

Page 17: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Setting up the Maps

• Here's an example:

Truth Table:Karnaugh Map

• The Karnaugh map "wraps around itself" - i.e. the top and bottom, right and left edges are touching.• Adjacent cells contain terms which vary by only one input variable.•A subcube is defined as a set of 2m adjacent cells with the same value. m is an integer, so the subcube can be 1,2,4,8... cells

This is how we want the circuit to behave.

Page 18: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 1

• "Box the ones"

This subcube is represented by A'·B

This subcube is represented by A·C'

• So, the output is true if (A'ANDB) OR (AANDC') are true• "sum of products": A'·B + A·C'• This requires 5 gates:• note clean schematic layout

• The method only works if ALL of the 1's are considered• The minimal expression uses the smallest number of maximal subcubes

Page 19: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

• Draw the table• Find any isolated cells• Find any 2-cell subcubes which are not adjacent to other 2-cell subcubes. Remember wrapping

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

Page 20: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

• Draw the table• Find any isolated cells• Find 2-cell subcubes.• Find 4-cell subcubes which are not adjacent to other four cell subcubes•Find 8-cell subcubes etc etc.• Minimal expression is formed by the smallest number of maximal subcubes

Page 21: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

• A'·B'·D'

Page 22: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

• B'·C'

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

Page 23: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

• C'·D

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

Page 24: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

• A·D

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

Page 25: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

• So sum-of products realization is: O=A'·B'·D'+B'·C'+C'·D+AD• Requires 9 gates

00 01 11 10

00 1 1 0 1

01 0 1 0 0

11 0 1 1 0

10 1 1 1 0

ABCD

Page 26: Announcements Assignment 6 due tomorrow No Assignment 7 yet

Karnaugh Maps: Example 2:A B C D O

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1

• So sum-of products realization is: O=A'·B'·D'+B'·C'+C'·D+AD• Requires 9 gates

A'·B'·D'

B'·C'

C'·D

AD