Anomalous negative bias temperature instability behavior in p -channel metal-oxide-semiconductor field-effect transistors with Hf Si O N ∕ Si O 2 gate stackShih-Chang Chen, Chao-Hsin Chien, and Jen-Chung Lou Citation: Applied Physics Letters 90, 233505 (2007); doi: 10.1063/1.2745649 View online: http://dx.doi.org/10.1063/1.2745649 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/90/23?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Investigation of extra traps measured by charge pumping technique in high voltage zone in p-channel metal-oxide-semiconductor field-effect transistors with HfO2/metal gate stacks Appl. Phys. Lett. 102, 012106 (2013); 10.1063/1.4773914 Investigation of an anomalous hump in gate current after negative-bias temperature-instability in HfO2/metal gatep-channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 102, 012103 (2013); 10.1063/1.4773479 Analysis of anomalous traps measured by charge pumping technique in HfO2/metal gate n-channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 101, 233509 (2012); 10.1063/1.4769444 Analysis of an anomalous hump in gate current after dynamic negative bias stress in HfxZr1-xO2/metal gate p-channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 101, 052105 (2012); 10.1063/1.4739525 Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effecttransistor with high dielectric constant Appl. Phys. Lett. 96, 142110 (2010); 10.1063/1.3384999

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Anomalous negative bias temperature instability behavior in p-channelmetal-oxide-semiconductor field-effect transistors with HfSiON/SiO2 gatestack

Shih-Chang ChenDepartment of Electronics Engineering and Institute of Electronics, National Chiao Tung University,Hsinchu, Taiwan 300, Republic of China

Chao-Hsin Chiena�

Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University,Hsinchu, Taiwan 300, Republic of China and National Nano Device Laboratory, Hsinchu, Taiwan 300,Republic of China

Jen-Chung LouDepartment of Electronics Engineering and Institute of Electronics, National Chiao Tung University,Hsinchu, Taiwan 300, Republic of China

�Received 18 April 2007; accepted 9 May 2007; published online 5 June 2007�

In this letter, the authors systematically investigated the behavior of negative bias temperatureinstability of p-channel metal-oxide-semiconductor field-effect transistors with HfSiON/SiO2 gatestack. They found that typical linear extrapolation does not work well for the lifetime extraction atthe normal operation conditions since the polarities of the net trapped charge inside the high-�dielectrics are not the same at lower and higher stress voltage regimes. In other words, as �Vg��2.5 V electron trapping dominated while hole trapping dominated when �Vg��2.5 V. Thisphenomenon obviously contradicts the essence of the linear prediction in which the samedegradation mechanism is assumed through the entire stress voltage range. © 2007 AmericanInstitute of Physics. �DOI: 10.1063/1.2745649�

Negative bias temperature instability �NBTI� inp-channel metal-oxide-semiconductor field-effect transistors�pMOSFETs� is one of the challenging issues faced by thedevice community in recent years because of its great impacton the device reliability and circuit performance.1,2 Previ-ously, the reaction-diffusion �R-D� model involving a hydro-gen related species was commonly used to explain the spe-cific features of NBTI.3–5 In this model, Si–H bond breakingwas assumed to occur at the Si interface. The resulting dan-gling bonds and hydrogen species that diffuse into gate di-electrics in turn caused threshold voltage shift ��Vth� andinterface state generation ��Nit�.

6 It has been proven to bequite practical in predicting the behaviors both in voltage-and temperature-accelerated NBTI degradations.7,8 Nowa-days, the use of high-� dielectrics seems indispensable dueto the leakage current issue met by the conventional gatedielectrics.9 However, the presented rather severe chargetrapping in the high-� dielectrics will greatly deteriorate thecharacteristics of the devices.10,11 Therefore, the investiga-tion of the charge trapping effect in the high-� dielectrics hasattracted much attention recently, especially in the aspect ofNBTI degradation.12–15 So far, most of the people intuitivelyconsider that the NBTI degradation has the same mechanismthrough the entire stress voltage range and the lifetime pre-diction has been often done by the linear extrapolation. Inthis letter, we found that the typical linear extrapolation doesnot work well for the lifetime extraction since the polaritiesof the trapped charge in the high-� dielectrics are not thesame at lower and higher stress voltage regimes. As a result,more careful attentions shall be paid in trying to predict the

lifetime of the devices with high-� dielectrics.In this study, pMOSFETs were fabricated on �100�

n-type wafers. After standard cleaning, surface treatment wasperformed in an ozone water ambient at room temperature togrow a 0.5 nm thin interfacial oxide layer �SiO2�. Subse-quently, a 2.5 nm HfSiON thin film was deposited by metal-organic chemical-vapor deposition, followed an appropriatehigh-temperature postdeposition annealing to improve thefilm quality. After polycrystalline silicon gate patterning andsource/drain formation, dopant activation was conducted us-ing a rapid thermal annealing system to control the thermalbudget. After passivation and contact hole formation, alumi-num metallization subject to the forming gas annealing at400 °C for 30 min was finally performed to complete thedevice fabrication. The equivalent oxide thickness �EOT� ofthe gate stack was 1.53 nm obtained from high-frequency�100 kHz� capacitance-voltage �C-V� curves at strong inver-sion �EOT=�SiO2

/Cinv� without considering quantum effectby HP4284 LCR meter. During NBTI measurement, stressvoltage was applied to the gate electrode, while the source/drain and substrate terminals were all grounded at room tem-perature and threshold voltage �Vth� was extracted byHP4156 precision semiconductor parameter analyzer withmaximum transconductance �Gm,max� extrapolation method.

Figures 1�a� and 1�b� showed the variations of �Vth and�Nit as a function of stress voltage Vg over time. As ex-pected, the resultant �Vth was negative and its magnitudedecreased with decreasing stress voltage when �Vg��2.5 V.This result has been well known coming from the hole trap-ping in the gate stack.16 However, the tendency was notmonotonic when we kept going on lowering the stress volt-age. As �Vg��2.5 V, we clearly observed that the sign ofa�Electronic mail: chchien@faculty.nctu.edu.tw

APPLIED PHYSICS LETTERS 90, 233505 �2007�

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�Vth changed, indicating that the type of the net trappedcharge in the dielectrics has changed from hole to electronand the degradation became much worse with further deceas-ing stress voltage. This result strongly implies that themechanism of �Vth in the high-� dielectrics is not sole atdifferent stress voltage ranges. Since �Nit increased mono-tonically with increasing stress voltage and depicted onlyrelatively small value, we thought that this phenomenon isclosely related to the bulk traps rather than the interfacestates. Based on the previous model, we found that the fittingcurves based on the model matched very well with our ex-perimental data.12 As a consequence, the results in Fig. 1 canbe well explained by the trap filling of the different chargedspecies at the different stress conditions. This argument canbe verified by the measurements of charge pumping current�Icp�. Figures 2�a�–2�c� show Icp verse base voltage as a func-tion of stress time at different stress voltages of −2.2, −2.5,and −2.7 V, respectively. An obvious positive �negative�shift of Icp edge over time of the device stressed at −2.2 V�−2.7 V� corresponding to the electron trapping �hole trap-ping� has been observed, while almost no charge trappinghas emerged in the device stressed at −2.5 V except for thegeneration of certain interface states.

In order to have physical insight in this phenomenon,illustrative band diagrams with stress voltages of −2.7 and−2.2 V, respectively, are shown in Figs. 3�a� and 3�b�. Fromthe diagrams, we can see that the relative tunneling prob-abilities for hole and electron depict strong dependence onthe applied voltage. For large stress voltage, hole can bemore readily injected into the high-� dielectric than electrondue to the shorter tunneling path. They can also get trappedbecause there are usually plentiful hole traps existing insidethe high-� dielectrics.16 Therefore, the resultant �Vth wasnegative. On the contrary, the hole injection is significantly

suppressed by the presence of the interfacial layer as thestress voltage becomes smaller and then the effect of trappedelectron will gradually prevail over that of trapped hole. As aconsequence, �Vth changed from negative to positive when�Vg��2.5 V.

FIG. 1. �a� �Vth and �b� �Nit vs stress time under various stress conditions.

FIG. 2. Charge pumping current after stressing at �a� −2.2 V, �b� −2.5 V,and �c� −2.7 V.

FIG. 3. Illustrative band diagrams of HfSiON/SiO2 gate stack with stressvoltages of �a� −2.7 V and �b� −2.2 V.

233505-2 Chen, Chien, and Lou Appl. Phys. Lett. 90, 233505 �2007�

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The authentic NBTI lifetime was plotted in Fig. 4. Thelifetime was defined as the time at which the value of ��Vth�is 30 mV irrespective of hole or electron trapping. Remark-ably, there is a turnaround point at �Vg�=2.5 V. This factmeans that the linear extrapolation from the accelerated con-dition to the normal operation condition for the NBTI life-time prediction will fail for the devices with high-� dielec-trics.

In our study, we have systematically investigated the be-havior of NBTI in the pMOSFETs with HfSiON/SiO2 gatestack. We reported that the linear extrapolation can no longerbe employed for the prediction of lifetime at the normal op-erating condition since the polarity of the net trapped charge

in the high-� dielectrics strongly depend on the chosen stressvoltage regime.

The work was supported by UMC Device EngineeringDivision of Taiwan, R.O.C.

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FIG. 4. Authentic NBTI lifetime of pMOSFETs with HfSiON/SiO2 gatestack. The symbols represent experimental data. The dash line stands forlinear extrapolation. An arrow dash line indicates the trend of ��Vth� shift.

233505-3 Chen, Chien, and Lou Appl. Phys. Lett. 90, 233505 �2007�

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