anultra-lowpowerparitygeneratorcircuitbasedon...

Research ArticleAn Ultra-Low Power Parity Generator Circuit Based onQCA Technology

Ismail Gassoumi 1 Lamjed Touil1 Bouraoui Ouni 2 and Abdellatif Mtibaa1

1Laboratory of Electronics and Microelectronics University of Monastir Monastir Tunisia2Networked Objects Control amp Communication Systems Lab University of Sousse Sousse Tunisia

Correspondence should be addressed to Ismail Gassoumi gassoumiismailgmailcom

Received 28 June 2019 Revised 2 September 2019 Accepted 12 September 2019 Published 7 October 2019

Guest Editor Vıtor Monteiro

Copyright copy 2019 Ismail Gassoumi et al is is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work isproperly cited

Quantum-dot cellular automata (QCA) technology is one of the emerging technologies that can be used for replacing CMOStechnology It has attracted significant attention in the recent years due to its extremely low power dissipation high operatingfrequency and a small size In this study we demonstrate an n-bit parity generator circuit by utilizing QCA technology Here anovel XOR gate is used in the synthesis of the proposed circuit e proposed gate is based on electrostatic interactions betweencells to perform the desired function e comparison results demonstrate that the designed QCA circuits have advantagescompared to other circuits in terms of cell count area delay and power consumptione QCADesigner software as widely usedQCA circuit design and verification has been used to implement and to verify all of the designs in this study Power dissipation hasbeen computed for the proposed circuit using accurate QCAPro power estimator tool

1 Introduction

e continuous scaling down of CMOS-based devices insize over the past few decades in accordance with Moorersquoslaw leads to many different and difficult challenges as re-cently these devices are becoming more resistant to scaling[1ndash3] One of the biggest challenges faced by transistor-basedcircuits is power consumption from leakage current due tothe increased threshold voltage and decreased supply voltage[4] e search for new technologies led to quantum-dotcellular automata (QCA) which has appealing features suchas lower energy consumption and less cell density [5] QCAdesigns offer lower energy and area solutions to the existingCMOS logic [6 7] QCA-based designs are suitable forfabrication of nanoscale devices In QCA circuits are fab-ricated by quantum cells and each cell contains fourquantum dots as well as two electrons Quantum dots arenanoscale structures which are constructed from semi-conductors such as InAs and GaAs Transferring in-formation is achieved by propagation of a polarization stateinstead of current in QCA implementation is new

technology attracted lot of researchers due to its direct use inquantum computing Up to date several works have beenrealized for the design of QCA logic circuits such as mul-tipliers adder reversible ALU divider decoder andmemory circuits [8ndash15] Many of these designs have ad-vantages like faster speed and smaller size over their CMOScounterparts In contrast the mass production of ultra-smallsize QCA technology is very difficult Additionally QCAtechnology is prone to high error ratese high error rate ofthis technology compared to traditional CMOS technologyis due to the bridge displacement misalignment and cellomission defects as well as stuck-at-fault which are likelyoccurred in the gates and interconnections Defects can takeplace in both the chemical synthesis phase and the de-position phase During the chemical synthesis phase theQCA cells are manufactured and during the depositionphase the QCA cells are placed on a substrate Howeverdefects are more likely to occur in the deposition phase inwhich perfectly manufactured cells are imperfectly attachedto the substrate QCA devices are also susceptible to tran-sient faults which are caused by thermodynamic effects

HindawiJournal of Electrical and Computer EngineeringVolume 2019 Article ID 1675169 8 pageshttpsdoiorg10115520191675169

radiation and other effects such as the energy differencebetween the ground and the excited state is small

In this framework the exclusive-OR gate is probably avital part of complex digital circuits since it is often operatedas structural blocks in digital fabrication It can be used inthe development of specific communication circuits such asparity generator and checker QCA is one of the importanttechnologies that enable high performance circuit designwith low power consumption features In this context theexclusive-OR gate presents an important component Var-ious QCA-based exclusive-OR gates have been proposed inthe literature which have been designed using the majoritygate-based methodology In order to reduce power con-sumption and hardware complexity this study presents anoptimized QCA exclusive-OR gate by which any complexdigital designs may be synthesized Additionally an opti-mized parity generator circuit is achieved by using theproposed XOR gateemain contributions of the paper areas follows

(i) An efficient design of QCA exclusive-OR gate isproposed

(ii) e 4- 8- 16- and 32 -bit QCA parity generatorcircuits are designed using this proposed gate as abuilding block

(iii) e designed circuits are simulated with QCADe-signer software

(iv) Power dissipation of the proposed designs has beenestimated

e rest of the paper is organized as follows In Section 2the backgrounds of QCA technology are reviewed In Sec-tion 3 our proposed exclusive-OR gate is presented andcompared to the conventional exclusive-OR gates In Section4 parity generator circuits are designed by using the pro-posed gate and are compared to other counterpart designse simulation results of the proposed designs have beenpresented in Section 5 Finally Section 6 concludes thepaper

2 Background of QCA

e basic functional block of QCA is the quantum cell thatconsists of four quantum dots Each dot can hold oneelectron [6] Electrostatic repulsions among the two elec-trons in the quantum cell make sure that the electrons canonly reside in the antipodal sites us these electrons as-sume stable states called polarizations which are energet-ically equal and interpreted as binary ldquo0rdquoandldquo1rdquo [16] eyhave respective polarizations as P ldquominus 1rdquo (logic ldquo0rdquo) andP ldquo+1rdquo (logic ldquo0rdquo) as shown in Figure 1 Polarization of thecells is calculated from equation (1) [17]

P ρ1 + ρ3( 1113857 minus ρ2 + ρ4( 1113857

ρ1 + ρ2 + ρ3 + ρ4 (1)

where ρi shows the electric charge at the i th point Binaryinformation is displayed using the position of two electronsin each logical cell

On the other hand to ensure that proper data flow takesplace QCA circuit clocking is introduced [18] QCA-basedcircuits have a four-phased clocking namely switch holdrelease and relax as illustrated in Figure 2ese four phasesare generated by the traveling electric field wave perpen-dicular to the QCA plane e various clock zones arerepresented by four different colors Clock zero is repre-sented by green clock one by pink clock two by blue andclock three by white Each clocking zone has a phase shift of90 with respect to the adjacent ones Each cell in a clockingzone behaves as latch [19]

Furthermore when placed close to each other the po-larization of one QCA cell influences the polarization of theother again by Coulomb interaction One can exploit thiseffect in order to construct logic gates such as the NOTandthe MAJ gates e inverter is the result of placing the cellssuch that their vertices are touching as illustrated inFigure 3(a) [20] Amajority voter is made up of five cells onedevice cell (center cell) three inputs and an output cell asdepicted in Figure 3(b) e majority voter is driven by threeinput drivers A B and C Its output can be computed asfollows

MV(a b c) AB + BC + AC (2)

Crossover types provide an advantage in circuit design inQCA as it offers a certain amount of design flexibility QCAtechnology has two types of crossover One multilayercrossover and the other is coplanar crossover as depicted inFigures 4(a) and 4(b) respectively [16 21] e multilayercrossover yields high cost due to fabrication issue In thesecond technique two wires are overlapped in a similarplane to facilitate a simple binary wire cross an inverterchain

3 Related Works

31 Previous QCA Exclusive-OR Circuits Up to date awidespread study in QCA has been outlined to achieveexclusive-OR designs [22ndash27] which are used in many ofthe digital logic circuits such as error detection circuitsarithmetic logic circuits multiplexers full adders andcomparators e XOR gate is composed of two inputsand one output Its output is true when two input op-erands are not the same and the output is falseotherwise

In [22] the authors have proposed a novel low-powerXOR gate is designed gate consists of 13 cells and0012 μm2 area It occupies less area among the others is

Quantum dot

P = ndash1Binary ldquo0rdquo

Electron

P = +1Binary ldquo1rdquo

Figure 1 Two different polarizations of the quantum-dot cell

2 Journal of Electrical and Computer Engineering

design is based on the interaction between cells forimplementing the desired function It does not include anycrossover in its structure In addition there is no anymajority gate which leads to less number of cells and powerconsumption In [23] the authors have presented a novelrobust exclusive-OR gate is designed gate consists of 28cells and 002 μm2 area It is implemented without usingany coplanar and multilayer crossover is novel exclu-sive-OR design approach uses one five-input majority gateand two fixed polarization cells e authors in [24] pro-posed a layout with 36 cells extent 0030 μm2 and delay075 is design is developed using a structure of coupledmajority voter minority gate (CMVMIN) two majoritygates and two inverter gates e design proposed in [25]requires 37 QCA cells extent 0030 μm2 and delay 1 is

design has an important number of cells and provides alarge area Also a novel design of the XOR gate has beenproposed by Bahar et al in [26] is design has achieved areduction in the number of used cells and area con-sumption It consists of 12 QCA cells 002 μm2 extent and125 delay Figure 5 shows some previous designed ex-clusive-OR gates

32 ProposedQCAExclusive-ORGate In this section a newefficient exclusive-OR gate is proposed by employingarranged and interacted QCA cells e designed circuitand its simulation results are shown in Figures 6(a) and6(c) respectively Here no majority gates are used toachieve the proposed design e QCADesigner software is

Cloc

king

field

stre

ngth

Switch Hold Release Relax Clock phase

Figure 2 QCA clock zones

A

Output

(a)

A

B

C

Output

(b)

Figure 3 Inverter gate (a) and majority gate (b)

(a)

1

0

(b)

Figure 4 Signal crossover schemes (a) Coplanar crossing (b) Multilayer crossing

Journal of Electrical and Computer Engineering 3

used to verify the functionality of the designed circuit 13eproposed QCA design covers only 9 cells extent 001 μm2and a delay of 05 In contrast the QCA layout proposed in[25] require 37 cells extent 003 μm2 and a delay of 1Consequently the designed XOR gate has an improvement

of 7567 6666 and 50 in terms of cell complexityextent and delay correspondingly compared with thedesign in [25] In addition the proposed gate attains anadvancement of 6785 50 and 3333 in terms of cellintricacy area delay and cost respectively compared with

A

B

Out

(a)

A

B

Out

(b)

A

B Out

(c)

A

B Out

(d)

Figure 5 Exclusive-OR gates (a) design in [24] (b) design in [27] (c) design in [26] and (d) design in [23]

A

B Out

0

(a) (b)

(c)

Figure 6 QCA layout of the designed (a) XOR gate (b) power map and (c) simulation outcomes


the design in [23] 13us the proposed gate can lead to QCAdigital designs with less hardware complexity and powerconsumption

4 Parity Generator Designs

13e logic parity generator is a fundamental componentfor information processing chips and computing systemsin which the accurate matching of all received andtransmitted data needs to be veried It plays an im-portant role in the design of digital circuits As a resultseveral attempts have been done to implement this im-portant logic component especially in the QCA tech-nology [22 23 25 27] In this section we propose a novelQCA circuit for the parity generator Figure 7(a) showsthe proposed logic block implementation of the proposed4 -bit parity generator circuit with three copies of theproposed QCA XOR gate Figure 7(b) shows the simu-lation results of the proposed 4 -bit parity generatorcircuit 13e timing diagram indicates that the parityoutput is correctly obtained It should be noted that thiscircuit can be easily extended to the n-bit QCA paritygenerator circuit Figure 8 shows QCA implementation ofthe proposed 8 -bit parity generator circuit In this focuswe demonstrate only the QCA layouts of 4- and 8 -bitparity generator circuits because of the lack of spaceHere the cell count area and delay of the designed 4- and

8 -bit parity generator circuits are considerably improvedcompared to 4- and 8 bit parity generator circuits in[22 23 25]

A

B

Out

0

A1

0B1

(a)

(b)

Figure 7 QCA layout of the designed (a) 4 bit parity generator and (b) simulation outcomes

0A

0B

A1

00B1

Out0A2

B2

A3 0

B3 0

Figure 8 QCA implementation of the proposed 8 bit paritygenerator circuit


5 Simulation Results and Comparison

e QCADesigner tool version 203 is used to verify thefunctionality of the designed QCA circuits e utilizedparameters for the simulation are as follows cellwidth 18 nm cell height 18 nm dot diameter 5 nmnumber of samples 12800 convergence toler-ance 0001 radius of effect 80 nm relativepermittivity 129 clock high 98E minus 22J clocklow 38E minus 23J clock amplitude factor 2 layer sepa-ration 115 nm and maximum iterations persample 100 Table 1 shows the comparison results of theproposed exclusive-OR gate with previously reportedXOR gates e comparison is carried out considering thecell count and total area as well as latency of the circuit Ascan be seen from Table 1 the proposed XOR circuit hasless number of cells and reduced device area in com-parison with the existing circuits In Table 2 the proposedparity generator circuits have been compared with pre-viously reported parity generator circuits [23 25 28ndash30]Clearly our designs outperform the proposed designs in[23 25 28ndash30] In this work QCAPro software [31] aprobabilistic designing engine has been applied for theenergy depletion study e power dissipation map of theproposed XOR gate is depicted in Figure 6(b) Accordingto Figure 6(b) the darker cells exhibit higher averagepower dissipation and white squares represent the inputcells Table 3 illustrates the power consumed by theproposed QCA XOR design e estimation is performedat temperature T 2 K by employing three channelingenergy levels namely 05Ek 10Ek and 15Ek As is shownin Figure 9 our proposed gate has the lowest energydissipation value at three separate tunneling energy levelsas compared with the circuits in [22 23 25 27 32]Consequently the use of the proposed XOR gate in thedesign of parity generator circuits will provide morepower savings It is noticeable from Figure 10 that ourproposed architectures have least energy dissipation valuein diverse sizes (4 8 16 and 32 bits) compared to existingones

e power consumption of the proposed circuits isanalyzed with the Hartree-Fock approximation [33] eHamiltonian matrix of a mean-field approach isexplained as

H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek

2Cjminus 1 + Cj+11113872 1113873 minus c

minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)

e kink energy cost of two neighboring cells i and jwithopposite polarizations is derived as follows

Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)

For any instance the power depletion of a QCA cell canbe calculated as follows

Table 1 Comparison of the proposed exclusive-OR gate with theprevious work

Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype

XOR [28] 60 009 15 CoplanarXOR [29] 54 008 15 CoplanarXOR [30] 67 006 125 CoplanarXOR [25] 37 003 1 Not requiredXOR [24] 36 003 075 Not requiredXOR [23] 28 002 075 Not requiredXOR [22] 13 0012 05 Not requiredXOR [22] 12 0011 05 Not requiredProposedXOR 9 001 05 Not required

Table 2 Comparison results of parity generators

Circuit No of bits Cell count Area (μm2) Clocknocycle

[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45

Table 3 Power dissipation analysis of the XOR gate

QCA circuitDissipation of power T 20 K

c 05Ek c 1Ek c 15EKXOR [25] 4699 6654 8951XOR [27] 4728 6239 8034XOR [32] 3906 5363 7108XOR [23] 3620 5028 6658XOR [22] 1136 1842 2602Proposed XOR 67 1129 1619


PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion

Quantum-dot cellular automata (QCA) is an upcomingnanoscale technology with great prospect to providecompact circuits with low energy consumption comparedto CMOS technology In this paper a novel design ofexclusive-OR gate in the QCA technology has been pre-sented It is more preferable for QCA implementationssince it does not use any rotate cells and majority gates Itincredibly reduces the area Even parity generator circuitswere designed and analyzed using this proposed gate as abuilding block 13e designed circuits were simulated andveried by using the QCADesigner tool version 203 13epower dissipation of the proposed designs has been in-vestigated using QCAPro tools A comparison of variousXOR gates and parity generator circuits with regards to cellcount area and energy dissipation is analyzed in thispaper 13e comparison results show that the designed QCAcircuits have signicant improvement compared to otherexisting ones

Data Availability

13e data used to support the ndings of this study areavailable from the corresponding author upon request

Conflicts of Interest

13e authors declare that they have no conicts of interest

References

[1] K Bernstein R K Cavin W Porod A Seabaugh andJ Welser ldquoDevice and architecture outlook for beyond CMOSswitchesrdquo Proceedings of the IEEE vol 98 no 12 pp 2169ndash2184 2010

[2] P K Bondyopadhyay ldquoMoorersquos law governs the siliconrevolutionrdquo Proceedings of the IEEE vol 88 no 1 pp 78ndash812002

[3] N Z Haron and S Hamdioui ldquoWhy is CMOS scaling comingto an ENDrdquo in Proceedings of the 2008 3rd InternationalDesign and Test Workshop pp 98ndash103 Monastir TunisiaDecember 2008

[4] R H Dennard F H Gaensslen H-N Yu V Leo RideovtE Bassous and A R Leblanc ldquoDesign of ion-implantedMOSFETrsquos with very small physical dimensionsrdquo IEEE Solid-State Circuits Society Newsletter vol 12 no 1 pp 38ndash50 2007

[5] International Technology Roadmap for SemiconductorsldquoProcess integration devices and structures (PIDS)rdquo 2011httpwwwitrsnetLinks2011ITRSHome2011htm

[6] C S Lent P D Tougaw W Porod and G H BernsteinldquoQuantum cellular automatardquo Nanotechnology vol 4 no 1pp 49ndash57 1993

[7] G L Snider A O Orlov I Amlani et al ldquoQuantum-dotcellular automata review and recent experiments (invited)rdquoJournal of Applied Physics vol 85 no 8 pp 4283ndash4285 1999

[8] S W Kim and E E Swartzlander ldquoParallel multipliers forquantum-dot cellular automatardquo in Proceedings of the 2009IEEE Nanotechnology Materials and Devices Conferencepp 68ndash72 Traverse City MI USA June 2009

[9] S W Kim and E E Swartzlander ldquoMultipliers with coplanarcrossings for quantum-dot cellular automatardquo in Proceedingsof the 10th IEEE International Conference on Nanotechnologypp 953ndash957 Seoul Republic of Korea August 2010

100

80

60

40

20

0XOR [25] XOR [27] XOR [32] XOR [23] XOR [22] Proposed

XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)

Figure 9 13e total power dissipation of the presented XOR gate at three didegerent tunneling energy levels (T 2K)

Ener

gy d

issip

atio

n (E

V)

Even parity generators

4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit

Figure 10 Power dissipation comparison between didegerent size(4- 8- 16- and 32-bit) parity generator designs


[10] M Balali A Rezai H Balali F Rabiei and S Emadi ldquoTo-wards coplanar quantum-dot cellular automata adders basedon efficient three-input XOR gaterdquo Results in Physics vol 7pp 1989ndash1995 2017

[11] T N Sasamal A K Singh and A Mohan ldquoEfficient design ofreversible ALU in quantum-dot cellular automatardquo Optikvol 127 no 15 pp 6172ndash6182 2016

[12] T N Sasamal A K Singh and U Ghanekar ldquoDesign of non-restoring binary array divider in majority logic-based QCArdquoElectronics Letters vol 52 no 24 pp 2001ndash2003 2016

[13] M Kianpour and R S Nadooshan ldquoA novel modular decoderimplementation in quantum-dot cellular automata (QCA)rdquoin Proceedings of the 2011 International Conference onNanoscience Technology and Societal Implications (NSTSI)pp 1ndash5 Bhubaneswar India December 2011

[14] M Kianpour and R S Nadooshan ldquoA novel quantum dotcellular automata X-bittimes 32-bit SRAMrdquo IEEE Transactions onVery Large Scale Integration (VLSI) Systems vol 24 no 3pp 827ndash836 2016

[15] P P Chougule B Sen and T D Dongale ldquoRealization ofprocessing in-memory computing architecture using quan-tum dot cellular automatardquo Microprocessors and Micro-systems vol 52 pp 49ndash58 2017

[16] C S Lent and G L Snider ldquoe development of quantum-dotcellular automatardquo in Field-Coupled Nanocomputing Para-digms Progress and Perspectives N G Anderson andS Bhanja Eds pp 3ndash20 Springer Berlin Germany 2014

[17] S Angizi S Sayedsalehi A Roohi N Bagherzadeh andK Navi ldquoDesign and verification of new n-bit quantum-dotsynchronous counters using majority function-based JK flip-flopsrdquo Journal of Circuits Systems and Computers vol 24no 10 2015

[18] C S Lent and P D Tougaw ldquoA device architecture forcomputing with quantum dotsrdquo Proceedings of the IEEEvol 85 no 4 pp 541ndash557 1997

[19] V Vankamamidi M Ottavi and F Lombardi ldquoTwo-di-mensional schemes for clockingtiming of QCA circuitsrdquoIEEE Transactions on Computer-Aided Design of IntegratedCircuits and Systems vol 27 no 1 pp 34ndash44 2008

[20] W W Liu M OrsquoNeill and E E Swartzlander Quantum-DotCellular Automata 2013

[21] L Liang L Weiqiang M OrsquoNeill and E E SwartzlanderldquoQCA systolic array designrdquo IEEE Transactions on Computersvol 62 no 3 pp 548ndash560 2013

[22] M Berarzadeh S Mohammadyan K Navi andN Bagherzadeh ldquoA novel low power Exclusive-OR via celllevel-based design function in quantum cellular automatardquoJournal of Computational Electronics vol 16 no 3pp 875ndash882 2017

[23] G Singh R K Sarin and B Raj ldquoA novel robust exclusive-ORfunction implementation in QCA nanotechnology with en-ergy dissipation analysisrdquo Journal of Computational Elec-tronics vol 15 no 2 pp 455ndash465 2016

[24] M GWaje and P K Dakhole ldquoDesign and simulation of newXOR gate and code converters using quantum dot cellularautomata with reduced number of wire crossingsrdquo in Pro-ceedings of the 2014 International Conference on CircuitsPower and Computing Technologies (ICCPCT-2014)pp 1245ndash1250 Nagercoil India March 2014

[25] M Poorhosseini and A R Hejazi ldquoA fault-tolerant and ef-ficient XOR structure for modular design of complex QCAcircuitsrdquo Journal of Circuits Systems and Computers vol 27no 7 Article ID 1850115 2018

[26] A N Bahar S Waheed N Hossain and M AsaduzzamanldquoA novel 3-input XOR function implementation in quantumdot-cellular automata with energy dissipation analysisrdquoAlexandria Engineering Journal vol 57 no 2 pp 729ndash7382017

[27] S Sheikhfaal S Angizi S Sarmadi M Hossein Moaiyeri andS Sayedsalehi ldquoDesigning efficient QCA logical circuits withpower dissipation analysisrdquo Microelectronics Journal vol 46no 6 pp 462ndash471 2015

[28] M T Niemier ldquoDesigning digital systems in quantum cellularautomatardquo MS thesis University of Notre Dame NotreDame IN USA 2004

[29] S Hashemi R Farazkish and K Navi ldquoNew quantum dotcellular automata cell arrangementsrdquo Journal of Computa-tional andCeoretical Nanoscience vol 10 no 4 pp 798ndash8092013

[30] S Angizi E Alkaldy N Bagherzadeh and K Navi ldquoNovelrobust single layer wire crossing approach for exclusive orsum of products logic design with quantum-dot cellularautomatardquo Journal of Low Power Electronics vol 10 no 2pp 259ndash271 2014

[31] S Srivastava A Asthana S Bhanja and S Sarkar ldquoQCAP-romdashan error-power estimation tool for QCA circuit designrdquoin Proceedings of the 2011 IEEE International Symposium ofCircuits and Systems (ISCAS) pp 2377ndash2380 Rio de JaneiroBrazil May 2011

[32] T N Sasamal A K Singh and U Ghanekar ldquoDesign andanalysis of ultra-low power QCA parity generator circuitrdquoAdvances in Power Systems and Energy Management Vol 436of Lecture Notes in Electrical Engineering pp 341ndash354Springer Singapore 2018

[33] J Timler and C S Lent ldquoPower gain and dissipation inquantum-dot cellular automatardquo Journal of Applied Physicsvol 91 no 2 pp 823ndash831 2002


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radiation and other effects such as the energy differencebetween the ground and the excited state is small

In this framework the exclusive-OR gate is probably avital part of complex digital circuits since it is often operatedas structural blocks in digital fabrication It can be used inthe development of specific communication circuits such asparity generator and checker QCA is one of the importanttechnologies that enable high performance circuit designwith low power consumption features In this context theexclusive-OR gate presents an important component Var-ious QCA-based exclusive-OR gates have been proposed inthe literature which have been designed using the majoritygate-based methodology In order to reduce power con-sumption and hardware complexity this study presents anoptimized QCA exclusive-OR gate by which any complexdigital designs may be synthesized Additionally an opti-mized parity generator circuit is achieved by using theproposed XOR gateemain contributions of the paper areas follows

(i) An efficient design of QCA exclusive-OR gate isproposed

(ii) e 4- 8- 16- and 32 -bit QCA parity generatorcircuits are designed using this proposed gate as abuilding block

(iii) e designed circuits are simulated with QCADe-signer software

(iv) Power dissipation of the proposed designs has beenestimated

e rest of the paper is organized as follows In Section 2the backgrounds of QCA technology are reviewed In Sec-tion 3 our proposed exclusive-OR gate is presented andcompared to the conventional exclusive-OR gates In Section4 parity generator circuits are designed by using the pro-posed gate and are compared to other counterpart designse simulation results of the proposed designs have beenpresented in Section 5 Finally Section 6 concludes thepaper

2 Background of QCA

e basic functional block of QCA is the quantum cell thatconsists of four quantum dots Each dot can hold oneelectron [6] Electrostatic repulsions among the two elec-trons in the quantum cell make sure that the electrons canonly reside in the antipodal sites us these electrons as-sume stable states called polarizations which are energet-ically equal and interpreted as binary ldquo0rdquoandldquo1rdquo [16] eyhave respective polarizations as P ldquominus 1rdquo (logic ldquo0rdquo) andP ldquo+1rdquo (logic ldquo0rdquo) as shown in Figure 1 Polarization of thecells is calculated from equation (1) [17]

P ρ1 + ρ3( 1113857 minus ρ2 + ρ4( 1113857

ρ1 + ρ2 + ρ3 + ρ4 (1)

where ρi shows the electric charge at the i th point Binaryinformation is displayed using the position of two electronsin each logical cell

On the other hand to ensure that proper data flow takesplace QCA circuit clocking is introduced [18] QCA-basedcircuits have a four-phased clocking namely switch holdrelease and relax as illustrated in Figure 2ese four phasesare generated by the traveling electric field wave perpen-dicular to the QCA plane e various clock zones arerepresented by four different colors Clock zero is repre-sented by green clock one by pink clock two by blue andclock three by white Each clocking zone has a phase shift of90 with respect to the adjacent ones Each cell in a clockingzone behaves as latch [19]

Furthermore when placed close to each other the po-larization of one QCA cell influences the polarization of theother again by Coulomb interaction One can exploit thiseffect in order to construct logic gates such as the NOTandthe MAJ gates e inverter is the result of placing the cellssuch that their vertices are touching as illustrated inFigure 3(a) [20] Amajority voter is made up of five cells onedevice cell (center cell) three inputs and an output cell asdepicted in Figure 3(b) e majority voter is driven by threeinput drivers A B and C Its output can be computed asfollows

MV(a b c) AB + BC + AC (2)

Crossover types provide an advantage in circuit design inQCA as it offers a certain amount of design flexibility QCAtechnology has two types of crossover One multilayercrossover and the other is coplanar crossover as depicted inFigures 4(a) and 4(b) respectively [16 21] e multilayercrossover yields high cost due to fabrication issue In thesecond technique two wires are overlapped in a similarplane to facilitate a simple binary wire cross an inverterchain

3 Related Works

31 Previous QCA Exclusive-OR Circuits Up to date awidespread study in QCA has been outlined to achieveexclusive-OR designs [22ndash27] which are used in many ofthe digital logic circuits such as error detection circuitsarithmetic logic circuits multiplexers full adders andcomparators e XOR gate is composed of two inputsand one output Its output is true when two input op-erands are not the same and the output is falseotherwise

In [22] the authors have proposed a novel low-powerXOR gate is designed gate consists of 13 cells and0012 μm2 area It occupies less area among the others is

Quantum dot

P = ndash1Binary ldquo0rdquo

Electron

P = +1Binary ldquo1rdquo

Figure 1 Two different polarizations of the quantum-dot cell





Cloc

king

field

stre

ngth



A

Output

(a)

A

B

C

Output

(b)


(a)

1

0

(b)





A

B

Out

(a)

A

B

Out

(b)

A

B Out

(c)

A

B Out

(d)


A

B Out

0

(a) (b)

(c)







A

B

Out

0

A1

0B1

(a)

(b)


0A

0B

A1

00B1

Out0A2

B2

A3 0

B3 0






H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek


minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)


Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)



Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype




[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45





PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





Cloc

king

field

stre

ngth



A

Output

(a)

A

B

C

Output

(b)


(a)

1

0

(b)





A

B

Out

(a)

A

B

Out

(b)

A

B Out

(c)

A

B Out

(d)


A

B Out

0

(a) (b)

(c)







A

B

Out

0

A1

0B1

(a)

(b)


0A

0B

A1

00B1

Out0A2

B2

A3 0

B3 0






H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek


minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)


Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)



Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype




[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45





PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia




A

B

Out

(a)

A

B

Out

(b)

A

B Out

(c)

A

B Out

(d)


A

B Out

0

(a) (b)

(c)







A

B

Out

0

A1

0B1

(a)

(b)


0A

0B

A1

00B1

Out0A2

B2

A3 0

B3 0






H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek


minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)


Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)



Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype




[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45





PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia






A

B

Out

0

A1

0B1

(a)

(b)


0A

0B

A1

00B1

Out0A2

B2

A3 0

B3 0






H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek


minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)


Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)



Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype




[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45





PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





H

minus Ek

21113944

i

Cifi j minus c

minus cEk

21113944

i

Cifi j

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

minus Ek


minus cminus Ek

2Cjminus 1 + Cj+11113872 1113873

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(3)


Eij 1

4πε0εr

1113944

4

n11113944

4

m1

qiqj

ri minus rj

11138681113868111386811138681113868

11138681113868111386811138681113868 (4)



Circuit Cellcount

Area(μm2)

Clocknocycle

Crossovertype




[28]

4 187 032 2758 465 092 416 1024 241 52532 2220 596 65

[29]

4 168 028 2758 408 08 416 912 209 52532 1968 516 65

[30]

4 188 02 2258 369 049 22516 847 146 32532 1862 358 425

[25]

4 111 014 28 269 043 316 603 113 432 1312 281 5

[23]

4 87 010 1758 213 030 27516 480 081 37532 1044 208 475

Proposed design

4 37 005 158 97 018 2516 227 050 3532 511 13 45





PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


PTotal ddtE

h

2ddtΓrarr

( ) middot λrarr+h

2Γrarr d

dtλrarr

( ) P1 + P2

(5)

6 Conclusion


Data Availability




References










100

80

60

40

20


XOR

Circuits

γ = 05Ekγ = 1Ekγ = 15Ek

Tota

l ene

rgy

diss

ipat

ion

(meV

)


Ener

gy d

issip

atio

n (E

V)


4000300020001000

0[30] [27] [23] Proposed

design

4-bit8-bit

16-bit32-bit






























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia





























RoboticsJournal of




VLSI Design



Shock and Vibration







Journal of



Volume 2018



Volume 2018


Journal of




SensorsJournal of



RotatingMachinery





Propagation






Hindawi


Advances in

Multimedia


anultra-lowpowerparitygeneratorcircuitbasedon...

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