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Altera Stratix V Network Reference

Platform Porting Guide

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Contents

Altera Stratix V Network Reference Platform Porting Guide........................... 1-1

Stratix V Network Reference Platform: Prerequisites.............................................................................1-1Legacy Board Support..................................................................................................................... 1-1

Features of the Stratix V Network Reference Platform.......................................................................... 1-2Contents of the Stratix V Network Reference Platform.........................................................................1-3Developing Your Custom Platform...........................................................................................................1-3

Initializing Your Custom Platform................................................................................................1-5Removing Unused Hardware.........................................................................................................1-5Integrating Your Custom Platform with the AOCL...................................................................1-6Setting up the Software Development Environment.................................................................. 1-6Branding Your Custom Platform.................................................................................................. 1-7Establishing Host Communication...............................................................................................1-7Connecting the Memory.................................................................................................................1-8Integrating an OpenCL Kernel...................................................................................................... 1-9Programming Your FPGA Quickly Using CvP...........................................................................1-9Guaranteeing Timing Closure..................................................................................................... 1-10

Stratix V Network Reference Platform Design Architecture...............................................................1-11Host-FPGA Communication over PCIe.....................................................................................1-11DDR3 as Global Memory for OpenCL Applications................................................................1-16QDRII as Heterogeneous Memory for OpenCL Applications................................................1-18Host Connection to OpenCL Kernels.........................................................................................1-19Implementation of UDP Cores as OpenCL Channels .............................................................1-19FPGA System Design.....................................................................................................................1-21Guaranteed Timing Closure.........................................................................................................1-26

Addition of Timing Constraints.................................................................................................. 1-28Connection to the Altera SDK for OpenCL...............................................................................1-28FPGA Programming Flow............................................................................................................1-30Host-to-Dev ice MMD Software Implementation..................................................................... 1-37OpenCL Utilities Implementation...............................................................................................1-38

Stratix V Network Reference Platform Implementation Considerations..........................................1-40Troubleshooting.........................................................................................................................................1-40Document Revision History.....................................................................................................................1-42

TOC-2

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Altera Stratix V Network Reference PlatformPorting Guide 1

2014.12.15

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The Altera Stratix V Network Reference Platform Porting Guide describes the procedures and designconsiderations you can implement to modify the Altera® Stratix® V Network Reference Platform (s5_net)into your own Custom Platform for use with the Altera Software Development Kit (SDK) for OpenCL™(1)(2) (AOCL). This document also contains reference information on the design decisions for s5_net, whichmakes use of features such as heterogeneous memory buffers and I/O channels to maximize hardwareusage on a computing card designed for networking.

Stratix V Network Reference Platform: PrerequisitesThe Altera Stratix V Network Reference Platform Porting Guide assumes that you are an experiencedFPGA designer who is familiar with Altera FPGA design tools and concepts.

These design tools and concepts include:

• FPGA architecture, including clocking, global routing and I/Os

• High-speed design

• Timing analysis

• Quartus® II software

• Qsys design and Avalon® interfaces

• Tcl scripting

• Designing with LogicLock ™ regions• PCI Express® (PCIe®)

• DDR3 external memory

Legacy Board SupportThe Altera Software Development Kit (SDK) for OpenCL (AOCL) attempts to automigrate your existingCustom Platform to the most recent Altera Complete Design Suite (ACDS) version.

Refer to the Custom Platform Automigration for Forward Compatibility section in the Altera SDK for OpenCL Custom Platform Toolkit User Guide for more information and instructions.

(1) OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of the Khronos Group™.(2) The Altera SDK for OpenCL is based on a published Khronos Specification, and has passed the Khronos

Conformance Testing Process. Current conformance status can be found at www.khronos.org/conform‐ance.

© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are

trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as

trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performanceof its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,

product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

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The AOCL Custom Platform Toolkit is available in the AOCL board directory (that is, ALTERAOCLSDK‐ROOT /board/custom_platform_toolkit).

Caution: The Stratix V Network Reference Platform (s5_net) and the Altera Stratix V Network ReferencePlatform Porting Guide are not compatible with Custom Platforms created prior to AOCL version 14.0.

Related Information

Altera SDK for OpenCL Custom Platform Toolkit User Guide

Features of the Stratix V Network Reference Platform

Prior to designing an Altera Software Development Kit (SDK) for OpenCL (AOCL) Custom Platform,decide on design considerations that allow you to fully utilize the available hardware on your computingcard.

The following figure depicts the hardware features on a hypothetical computer card that the Stratix VNetwork Reference Platform (s5_net) targets.

DDR3-1600

DDR3-1600

PCIe Gen2 x8

FPGA

Stratix V D8

QDRII + 500 MHz

QDRII + 500 MHz

QDRII + 500 MHz

QDRII + 500 MHz

10GE

10GE

Features of s5_net:

1. OpenCL Host

A PCI Express (PCIe)-based host that connects to the Stratix V PCIe Gen2 x8 Hard intellectualproperty (HIP) core.

2. OpenCL Global Memory

The hardware provides two separate 4 gigabytes (GB)-DDR3 memory buffers. s5_net uses both bankstogether to create 8 GB of global memory.

3. Heterogeneous Memory

s5_net uses the four on-board quad data rate II (QDRII) memory interfaces to implement a total of 64megabytes (MB) of heterogeneous memory for the Altera Offline Compiler (AOC). By default, thehost application allocates memory into the OpenCL global memory (that is, DDR3) when an AOCL

kernel program loads into the OpenCL runtime. However, based on the kernel arguments, the hostmight relocate memory to other buffers available on the computing card (that is, QDRII). Accesses toheterogeneous memory buffers are advantageous for network applications because they require the fastrandom access bandwidth that QDR provides.

4. OpenCL I/O Channels

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The two 10-Gbps Ethernet (10GbE) I/Os connect to a full user datagram protocol (UDP) stack thatprovides an Avalon Streaming (Avalon-ST) interface for direct connection to OpenCL kernels.

5. FPGA Programming

The computing card uses the Configuration via Protocol (CvP)-capable PCIe HIP. s5_net uses Altera'sCvP feature for implementing fast reprogramming over PCIe.

6. Guaranteed Timing

Timing guarantee is achievable via the Altera Quartus II compilation flow for CvP. s5_net delivers aprecompiled netlist in a .personax file that the AOC imports into each kernel compilation.

Contents of the Stratix V Network Reference Platform

The Stratix V Network Reference Platform (s5_net) is available for download on the OpenCL ReferencePlatforms page of the Altera website.

The following table highlights the contents of s5_net:

Windows File or Folder Linux File or Directory Description

board_env.xml board_env.xml eXtensible Markup Language (XML) file thatdescribes s5_net to the Altera Software Develop‐ment Kit (SDK) for OpenCL (AOCL).

windows64 linux64 Contains memory-mapped device (MMD) library,kernel mode driver, and executables for the AOCLutilities (that is, install, flash, program,diagnose) for your 64-bit operating system.

source source Contains source codes for the MMD library andAOCL utilities in the linux64 and windows64directories.

include include Contains header files necessary for compiling an

OpenCL host application and accessing board-specific application programming interface (API)calls. For s5_net, these files are necessary for userdatagram protocol (UDP) initialization.

Related Information

OpenCL Reference Platforms page

Developing Your Custom Platform

Use the tools available in Stratix V Network Reference Platform (s5_net) and the Altera Software

Development Kit (SDK) for OpenCL (AOCL) Custom Platform Toolkit together to create your ownCustom Platform. Altera recommends that you familiarize yourself with the contents of both thisdocument and the Altera SDK for OpenCL Custom Platform Toolkit User Guide.

Before you begin

Developing your Custom Platform requires in-depth knowledge of the contents in the followingdocuments and tools:

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2014.12.15 Contents of the Stratix V Network Reference Platform 1-3

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1. Altera SDK for OpenCL Custom Platform User Guide

2. Contents of the AOCL Custom Platform Toolkit

3. Altera Stratix V Network Reference Platform for OpenCL Porting Guide

4. Altera documentation for all the intellectual properties (IPs) in your Custom Platform

5. Altera SDK for OpenCL Getting Started Guide

6. Altera SDK for OpenCL Programming Guide

In addition, you must independently verify all the Hard IPs (HIPs) on your computing card (for example,PCI Express (PCIe) controllers, DDR3 external memory, and Ethernet).

1. Initializing Your Custom Platform on page 1-5To initialize your Altera Software Development Kit (SDK) for OpenCL (AOCL) Custom Platform,copy the Stratix V Network Reference Platform (s5_net) to another directory and rename it.

2. Removing Unused Hardware on page 1-5After you store the Stratix V Network Reference Platform (s5_net) to your own directory and performsome preliminary modifications, modify the Quartus II design files.

3. Integrating Your Custom Platform with the AOCL on page 1-6After you modify your Quartus II design files, integrate your Altera Software Development Kit (SDK)for OpenCL (AOCL) Custom Platform with the AOCL.

4. Setting up the Software Development Environment on page 1-6Prior to building the software layer for your Altera Software Development Kit (SDK) for OpenCL(AOCL) Custom Platform, you must set up the software development environment.

5. Branding Your Custom Platform on page 1-7Modify the library, driver and source files in the Stratix V Network Reference Platform (s5_net) toreference your Altera Software Development Kit (SDK) for OpenCL (AOCL) Custom Platform.

6. Establishing Host Communication on page 1-7After you modify and rebrand the Stratix V Network Reference Platform (s5_net) to your own CustomPlatform, use the tools and utilities in the Custom Platform to establish communication between yourFPGA accelerator board and your host application.

7. Connecting the Memory on page 1-8

Calibrate the external memory intellectual properties (IPs) and controllers in your Custom Platform,and connect them to the host.

8. Integrating an OpenCL Kernel on page 1-9After you establish host communication and connect the external memory, test the FPGAprogramming process from kernel creation to program execution.

9. Programming Your FPGA Quickly Using CvP on page 1-9After you verify that the host can program you FPGA device successfully, establish the Configuration via Protocol (CvP) programming capability of your Custom Platform.

10.Guaranteeing Timing Closure on page 1-10When you modify the Stratix V Network Reference Platform (s5_net) into your own Custom Platform,ensure that guaranteed timing closure holds true for your Custom Platform.

Related Information

• Altera SDK for OpenCL Custom Platform Toolkit User Guide

• Altera SDK for OpenCL Getting Started Guide

• Altera SDK for OpenCL Programming Guide

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Initializing Your Custom PlatformTo initialize your Altera Software Development Kit (SDK) for OpenCL (AOCL) Custom Platform, copy the Stratix V Network Reference Platform (s5_net) to another directory and rename it.

1. Download s5_net from the OpenCL Reference Platforms page on the Altera website.

2. Store the s5_net directory into a directory that you own (that is, not a system directory) and thenrename it ( ).

3. Remove the /hardware/s5_net/persona directory.4. Rename the /hardware/s5_net directory to match the name of your FPGA

board (), and then modify the name attribute of the board eXtensible Markup Language(XML) element in the board_spec.xml file with this name.

5. Modify the board_env.xml file so that the name and default fields match the changes you made in Step4.

6. In the AOCL, invoke the command aoc --list-boards to confirm that the Altera OfflineCompiler (AOC) displays the board name in your Custom Platform.

Removing Unused HardwareAfter you store the Stratix V Network Reference Platform (s5_net) to your own directory and perform

some preliminary modifications, modify the Quartus II design files.

1. Instantiate your PCI Express (PCIe) controller.

For detailed instructions on instantiating your PCIe controller, refer to the Stratix V Avalon-MM Interface for PCIe Solutions User Guide.

For information on the design parameters for instantiating the PCIe controller for s5_net, refer to theHost-FPGA Communication over PCIe section.

2. In Qsys, open the /hardware//board.qsys Qsys system file.

a. Remove the cpld_bridge component.

b. Remove the qdr_0 component.

c. Remove the DDR3 memory controllers.

Because several components use the clock that ddr3a generates, it might be easier to remove only the second DDR3 controller (ddr3b) and reparameterize ddr3a to match your memory.

3. Remove the cpld.sdc file from the /hardware/ directory.

4. In Qsys, open the /hardware//system.qsys file.

a. Remove the udp_0 component.

5. In the Qsys System menu, click Remove Dangling Connections to remove invalid connection pointsbetween system.qsys and board.qys.

6. Modify both Quartus II settings files (.qsf ) to use only the pinouts and settings for your system. Ensurethat the only differences between these files are in the settings in the Revision Specific Settingssection of the files.

Related Information

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Host-FPGA Communication over PCIe on page 1-11

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Integrating Your Custom Platform with the AOCLAfter you modify your Quartus II design files, integrate your Altera Software Development Kit (SDK) forOpenCL (AOCL) Custom Platform with the AOCL.

1. Update the /hardware//board_spec.xml file by removing thequad data rate (QDR) and Ethernet channels from it. Ensure that there is at least one global memory interface, and all the global memory interfaces correspond to the exported interfaces from the

board.qsys Qsys system file.2. In the /hardware//scripts directory, modify the post_flow.tcl

file to not call the create_fpga_bin.tcl file. You can do so by commenting out the line of code containingthe command call_script_as_function scripts/create_fpga_bin.tcl.

3. Set the environment variable ACL_QSH_COMPILE_CMD to quartus_sh --flow compile

top -c base.

Setting this environment variable instructs the AOCL to compile the base revision corresponding tothe base.qsf Quartus II Settings File in the /hardware/directory of your Custom Platform.

4. Perform the steps outlined in the ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/README.txt fileto compile the ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/boardtest/boardtest.cl OpenCL

kernel source file.The environment variable ALTERAOCLSDKROOT points to the location of the AOCL installation.

The hardware compilation stage will fail because of the absence of the fpga.bin file. However, theQuartus II compilation should complete successfully and produce a boardtest.aoco Altera OfflineCompiler Object file.

5. If compilation fails because of timing failures, fix the errors, or compile ALTERAOCLSDKROOT /board/

custom_platform_toolkit/tests/boardtest.cl with different seeds by including the --seed option of

the aoc command (for example, aoc --seed 2 boardtest.cl).

Setting up the Software Development EnvironmentPrior to building the software layer for your Altera Software Development Kit (SDK) for OpenCL (AOCL)Custom Platform, you must set up the software development environment.

Setting Up Software Development Environment for Windows on page 1-6

Setting Up the Software Development Environment for Linux on page 1-7

Setting Up Software Development Environment for Windows

1. Install the GNU make utility on your Windows development machine.

Note: Altera used the GNU make utility version 3.81a to build the software in the Stratix V Network Reference Platform (s5_net).

2. Install Microsoft Visual Studio.

Note: Microsoft Visual Studio 2008 (9.0) was used to build the software in s5_net.

3. Set up the software development environment so that the AOCL user can invoke AOCL commandsand utilities at a normal command prompt.

4. Modify the /source/Makefile.common file so that TOP_DEST_DIR points tothe top-level directory of your Custom Platform.

5. Set the JUNGO_LICENSE variable to your Jungo WinDriver license in the Makefile.common file.

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For information on how to acquire a Jungo Windriver license, visit the Jungo Connectivity Ltd.website.

6. To check that you have set up the software development environment properly, invoke the gmake or

gmake clean command.

Related Information

Jungo Connectivity Ltd. website

Setting Up the Software Development Environment for Linux

1. Ensure that you use a Linux distribution that Altera supports.

Note: Altera used the GNU Compiler Collection (GCC) version 4.2.3 to build the software in theStratix V Network Reference Platform (s5_net).

2. Modify the /source/Makefile.common file so that TOP_DEST_DIR points to the top-level directory of your Custom Platform.

3. To check that you have set up the software environment properly, invoke the make or make cleancommand.

Branding Your Custom PlatformModify the library, driver and source files in the Stratix V Network Reference Platform (s5_net) toreference your Altera Software Development Kit (SDK) for OpenCL (AOCL) Custom Platform.

1. In the software available with the s5_net Reference Platform, ensure that you replace all references tos5_net to your Custom Platform.

2. Modify the linklib element in /board_env.xml eXtensible MarkupLanguage (XML) file to your custom memory-mapped device (MMD) library name.

3. Modify the PACKAGE_NAME and MMD_LIB_NAME fields in the /source/Makefile.common file.

4. In your directory, modify the information in the linux64/driver/hw_pcie_constants.h file for Linux and the source\include\hw_pcie_constants.h file for Windows.

Update the following lines of code with information of your Custom Platform:

#define ACL_PCI_SUBSYSTEM_VENDOR_ID 0x1172#define ACL_PCI_SUBSYSTEM_DEVICE_ID 0x0005#define ACL_BOARD_PKG_NAME "s5_net"#define ACL_VENDOR_NAME "Altera Corporation"#define ACL_BOARD_NAME "Network Reference Platform"

Note: The IDs must match the parameters in the PCI Express (PCIe) controller hardware.

5. For Windows systems, update the DeviceList field in the \windows64\driver\acl_boards.inf Setup Information file.

6. Run make in the/source directory to generate the driver.

Establishing Host CommunicationAfter you modify and rebrand the Stratix V Network Reference Platform (s5_net) to your own CustomPlatform, use the tools and utilities in the Custom Platform to establish communication between yourFPGA accelerator board and your host application.

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1. Program your FPGA device with the base hardware configuration file and reboot your system.

2. Invoke lspci on Linux or open the Device Manager on Windows, and confirm that a PCI Express(PCIe) device with your vendor and device IDs exists.

This step confirms that your operating system recognizes the PCIe device.

3. Set the environment variable AOCL_BOARD_PACKAGE_ROOT to point to the location of the current

Custom Platform. Then run the aocl install utility command to install the kernel driver on yourmachine.

4. Ensure that you properly set the LD_LIBRARY_PATH environment variable on Linux or the PATH environment variable on Windows.

For more information on the settings for LD_LIBRARY_PATH or PATH , refer to the Altera SDK for OpenCL Getting Started Guide.

5. Perform one of the following tasks to instruct the memory-mapped device (MMD) software not to useConfiguration via Protocol (CvP) or flash memory to program the FPGA:

• To force the MMD to program via the quartus_pgm executable, set the environment variable ACL_PCIE_FORCE_USB_PROGRAMMING to a value of 1.

• To force the MMD to program via your custom programming method, modify the/source/host/mmd/acl_pcie_device.cpp file. Trace the appearance of the

environment variable ACL_PCIE_FORCE_USB_PROGRAMMING in the source code, and replacethe existing instruction with your custom programming method.

6. Modify the version_id_test function in the MMD source code in the /source/host/mmd/acl_pcie_device.cpp file to exit after reading from the version ID register.

7. Remake the MMD software.

8. Run the aocl diagnose utility command and confirm the version ID register reads back the IDsuccessfully. You may set the environment variables ACL_HAL_DEBUG and ACL_PCIE_DEBUG to a value of 1 to visualize the result of the diagnostic test on your terminal.

Related Information

• Host-FPGA Communication over PCIe on page 1-11

• Altera SDK for OpenCL Getting Started Guide

Connecting the MemoryCalibrate the external memory intellectual properties (IPs) and controllers in your Custom Platform, andconnect them to the host.

1. In your Custom Platform, instantiate your external memory IP based on the information in the DDR3as Global Memory for OpenCL Applications section.

2. Update the /hardware//board_spec.xml file to reflect themodifications.

3. Remove the boardtest hardware configuration file that you create previously, and recompile the ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/boardtest/boardtest.cl

kernel source file.The environment variable ALTERAOCLSDKROOT points to the location of the Altera SoftwareDevelopment Kit (SDK) for OpenCL (AOCL) installation.

4. Reprogram the FPGA with the new boardtest hardware configuration file and then reboot yourmachine.

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5. Modify the memory-mapped device (MMD) source code to exit after checking the UniPHY statusregister in the function wait_for_uniphy. Rebuild the MMD software.

6. Run the aocl diagnose utility command and confirm that the host reads back both the version IDand the value 0 from the uniphy_status component.

The utility should return the message Uniphy are calibrated.

7. Consider using the SignalTap II Logic Analyzer to confirm the successful calibration of all memory controllers.

Related Information

DDR3 as Global Memory for OpenCL Applications on page 1-16

Integrating an OpenCL KernelAfter you establish host communication and connect the external memory, test the FPGA programmingprocess from kernel creation to program execution.

1. Perform the steps outlined in ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/README.txt file tobuild the hardware configuration file from the ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/boardtest/boardtest.cl kernel source file.

The environment variable ALTERAOCLSDKROOT points to the location of the Altera SoftwareDevelopment Kit (SDK) for OpenCL (AOCL) installation.

2. Program your FPGA device with the boardtest.aocx Altera Offline Compiler Executable file and rebootyour machine.

3. Remove the modifications to early exit that you implemented before and then invoke the aocl

diagnose command, where is the string you define in yourCustom Platform to identify each board.

By default, is the acl number (for example, acl0 to acl15) that corresponds to your

FPGA device. In this case, invoke the aocl diagnose acl0 command.

4. Build the boardtest host application. The .sln file for Windows and the Makefile for Linux are availablein the ALTERAOCLSDKROOT /board/custom_platform_toolkit/tests/boardtest directory.

Attention: You must modify the .sln file to link it against the memory-mapped device (MMD) library in your Custom Platform.

5. Set the environment variable CL_CONTEXT_COMPILER_MODE_ALTERA to a value of 3.

For more information on this environment variable, refer to the Troubleshooting section.

Related Information

Troubleshooting on page 1-40

Programming Your FPGA Quickly Using CvPAfter you verify that the host can program you FPGA device successfully, establish the Configuration viaProtocol (CvP) programming capability of your Custom Platform.

1. Invoke the following command to generate the CvP files:

quartus_cpf -c --cvp .sof .rbf

You may include this command in the /hardware//scripts/post_flow.tcl file so that it generates the CvP files automatically after each compilation.

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Your Quartus II compilation directory should contain the files .sof ,.periph.rbf , and .core.rbf files.

2. Program the base.sof file and then reboot your machine.

3. (Optional) You may use the Quartus II Programmer to verify basic CvP functionality. Invoke the

quartus_cvp command to program the base.core.rbf file.

4. Define the contents of your fpga.bin file by adding Tcl code to the /hardware//scripts/post_flow.tcl file that generates the file. Then, modify the memory-

mapped device (MMD) source code and the program utility so that you can use the file.

You may use the existing format if you remove the proprietary host-to-flash programming over thecpld_bridge component from both the hardware and software.

5. If you set the environment ACL_PCIE_FORCE_USB_PROGRAMMING earlier, unset it. Then, set theenvironment variable ACL_PCIE_FORCE_PERIPH_REPLACE_USB to a value of 1. Alternatively,modify the /source/host/mmd/acl_pcie_device.cpp file to use CvP but notflash memory fo reprogramming periphery changes. Flash programming is unavailable because anearlier modification step has removed the necessary hardware.

6. Navigate to the directory containing the boardtest.aocx Altera Offline Compiler Executable file. Invoke

the command aocl program boardtest.aocx to reprogram the device.

Confirm that the message Program succeed appears.

Note: By default, is the acl number. If you have retained the default naming

convention, invoke the aocl program command using acl0 as . Alterna‐

tively, if you use another naming convention for , use that in your aocl utility command.

Guaranteeing Timing ClosureWhen you modify the Stratix V Network Reference Platform (s5_net) into your own Custom Platform,ensure that guaranteed timing closure holds true for your Custom Platform.

1. Establish the floorplan of your design.

Important: Consider all design criteria outlined in the FPGA System Design section and the AlteraSDK for OpenCL Custom Platform Toolkit User Guide.

2. Compile several seeds of boardtest.cl until you generate a compiled design that achieves timing closurecleanly.

3. Copy the /hardware/s5_net/persona/base.root_partition.personax file into your CustomPlatform.

4. Copy the boardtest.aocx Altera Offline Compiler Executable file from the timing-closed compilation inStep 2 into your Custom Platform. Rename the file base.aocx.

5. Derive the top revision top.qsf file from your base.qsf file by including the changes described in the CvP section.

6. Remove the ACL_QSH_COMPILE_CMD environment variable.

7. Recompile boardtest.cl. In the Fitter Preservation section of the report, confirm that the Top partition isimported.

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The Incremental Compilation Placement Preservation section should show 100% placement for Top.Similarly, the Incremental Compilation Routing Preservation section should show 100% routing forTop.

8. Confirm that you can use the .aocx file to reprogram over CvP by invoking the aocl program

acl0 boardtest.aocx command.

9. Ensure that the environment variable CL_CONTEXT_COMPILER_MODE_ALTERA is not set. Runthe boardtest_host executable.

Related Information

• Altera SDK for OpenCL Custom Platform Toolkit User Guide

• CvP on page 1-31

• FPGA System Design on page 1-21

Stratix V Network Reference Platform Design Architecture

Altera created the Stratix V Network Reference Platform (s5_net) based on various design considerations.Familiarize yourself with these design considerations. Having a thorough understanding of the design

decision-making process might help in the design of your own Altera Software Development Kit (SDK)for OpenCL (AOCL) Custom Platform.

Host-FPGA Communication over PCIeTo set up the PCI Express (PCIe) Hard intellectual property (HIP) that enables communication betweenthe host and the FPGA board, you must configure the IP settings, and set v arious IDs, constants andparameters..

Parameter Settings for PCIe Instantiation on page 1-11

Values for PCIe Device Identification Registers on page 1-12

Version ID on page 1-13

Definitions of Hardware Constants in Software Header Files on page 1-13

PCIe Kernel Driver on page 1-14

SG-DMA on page 1-16

Parameter Settings for PCIe InstantiationThe Stratix V Network Reference Platform (s5_net) instantiates the Stratix V PCI Express (PCIe) Hardintellectual property (HIP) to implement a host-to-device connection over PCIe.

Dependencies

• Altera Stratix V PCIe HIP core

• For Windows systems, Jungo WinDriver

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HIP Configuration Settings

The table below highlights some of the HIP configuration settings:

Parameter Setting

Lanes Lane Rate: Gen2 (5.0 gigabits per second (Gbps))

Number of Lanes: x8

Note: This setting is the fastest configurationthat can support Configuration viaProtocol (CvP).

Enable Configuration via Protocol (CvP) On

Base Address Registers (BARs) The design uses only a single BAR (BAR 0).

Rx Buffer Credit Allocation Low

Note: This setting is derived experimentally.

Address Translation Tables Number of address pages: 256

Note: This setting is derived experimentally.

Size of address pages: 12 bits

Important: The number and size of theaddress pages must match the values in the memory-mappeddevice (MMD) layer.

Values for PCIe Device Identification RegistersWhen building the PCI Express (PCIe) hardware, set the following PCIe IDs related to the devicehardware.

ID Register Name Parameter Name in PCIe IPCore Description

Vendor ID vendor_id_hwtcl Identifies the manufacturer of the FPGAdevice.

Always set this register to Altera's vendorID: 0x1172

Device ID device_id_hwtcl Identifies the FPGA device.

Set the device ID to the device code of theFPGA device on your accelerator board.

For the Stratix V Network Reference

Platform (s5_net), this register is set to0xD800 for the Stratix V D8 FPGA.

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ID Register Name Parameter Name in PCIe IP

Core

Description

Subsystem Vendor ID subsystem_vendor_id_hwtcl Identifies the manufacturer of the acceler‐ator board.

Set this register to the vendor ID of manufacturer of your accelerator board.

If you are a board vendor, set this register toyour vendor ID.

Subsystem Device ID subsystem_device_id_hwtcl Identifies the accelerator board.

The Altera Software Development Kit(SDK) for OpenCL (AOCL) uses this ID toidentify the board because the softwaremight perform differently on differentboards. If you create a Custom Platformthat supports multiple boards, use this ID todistinguish between the boards. Alterna‐tively, if you have multiple Custom

Platforms, each supporting a single board,you can use this ID to distinguish betweenthe Custom Platforms.

Important: Make this ID unique toyour Custom Platform.

You can find these PCIe ID definitions in the PCIe controller instantiated in the board.qsys system. TheseIDs are necessary in the driver and the AOCL programming flow. The kernel driver uses the Vendor ID,Subsystem Vendor ID and the Subsystem Device ID to identify the boards it supports. The AOCLprogramming flow refers to the Device ID to ensure that it programs a device with an Altera OfflineCompiler Executable file (.aocx) targeting that specific device.

Version IDThe Stratix V Network Reference Platform (s5_net) instantiates a version_id component that connects tothe PCI Express (PCIe) Avalon master.

Before communicating with any part of the FPGA system, the PCIe first reads from this version_idregister to confirm the following:

• The PCIe can access the FPGA fabric successfully.

• The address map matches the map in the memory-mapped device (MMD) software.

Update the VERSION_ID parameter in the version_id component to a new value with every slave additionor removal from the PCIe Base Address Registers (BAR) 0 bus, or whenever the address map changes.

Definitions of Hardware Constants in Software Header FilesAfter you build the PCI Express (PCIe) component in your hardware design, you need a software layer tocommunicate with the board via PCIe. To enable this communication, you must define the hardwareconstants for the software in the form of header files.

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The Stratix V Network Reference Platform (s5_net) includes three header files that describe the hardwaredesign to the software. The location of these header files are as follows:

• For Linux systems, the location is /linux64/driver

• For Windows systems, the location is \source\include

The following table describes the hardware constants header files:

Header File Name Description

hw_pcie_constants.h Header file that defines most of the hardware constants for theboard design.

Example constants in this file include the IDs described in theValues for PCIe Device Identification Registers section, BaseAddress Registers (BAR) number, and offset for differentcomponents in your design. In addition, this header file alsodefines the name strings of ACL_BOARD_PKG_NAME, ACL_VENDOR_ NAME and ACL_BOARD_NAME.

Keep the information in this file in sync with any changes to theboard design.

hw_pcie_dma.h Header file that defines direct memory access (DMA)-relatedhardware constants.

Refer to the SG-DMA section for more information.

hw_pcie_cvp_constants.h Header file that defines Configuration via Protocol (CvP)-relatedhardware constants.

Refer to the CvP section for more information.

Related Information

• SG-DMA on page 1-16

• CvP on page 1-31• Values for PCIe Device Identification Registers on page 1-12

PCIe Kernel DriverA PCI Express (PCIe) kernel driver is necessary for the OpenCL runtime library to access your boarddesign via a PCIe bus.

The Stratix V Network Reference Platform (s5_net) provides the PCIe kernel driver for the followingoperating systems:

• For Windows systems, the location of the driver is \windows64\driver

• For Linux systems, the location of the driver is /linux64/driver

Use the Altera Software Development Kit (SDK) for OpenCL (AOCL) install utility to install thekernel driver. Refer to the aocl install section for more information.

For Windows systems, the kernel driver, the WinDriver application programming interface (API), is athird-party driver from Jungo Connectivity Ltd. For more information about the WinDriver, refer to theJungo Connectivity Ltd. website or contact a Jungo Connectivity representative.

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For Linux systems, an open-source, memory-mapped device (MMD)-compatible kernel driver is availablewith s5_net. The following table highlights some of the files included in the Linux kernel driver:

File Name Description

pcie_linux_driver_exports.h Header file that defines the special commands the kernel driversupports. It defines the interface of the kernel driver. The MMDlayer uses this header file to communicate with the device.

After you install the kernel driver, it works as a character device.The basic operations to the driver are open(), close(), read(),and write(). To support more complex commands, an acl_cmdstruct variable is necessary to pass the command of interest tothe kernel driver through the read() or write() operation.

To execute a command, perform the following tasks:

1. Create a variable as type acl_cmd_struct.

2. Specify the command you want to execute with theappropriate parameters.

3. Send the command through a read() or write() operation.

aclpci.c File that implements the basic structures and functions that aLinux kernel driver requires (for example, the init and removefunctions, probe function, and functions that handle interrupts).

aclpci_fileio.c File that implements the file I/O operations of the kernel driver.The Linux kernel driver available with s5_net supports four fileI/O operations, namely open(), close(), read() and write().Implementation of these file I/O operations allows the userapplication to access the kernel driver via file I/O system calls(open/read/write/close).

aclpci_cmd.c File that implements the special commands defined in the pcie_linux_driver_exports.h file. Examples of these special commands

include SAVE_PCI_CONTROL_REGS, LOAD_PCI_ CONTROL_REGS, DO_CVP, and GET_PCI_SLOT_INFO.

aclpci_dma.c File that implements direct memory access (DMA)-relatedroutine in the kernel driver.

Refer to the SG-DMA section for more information.

aclpci_cvp.c File that implements Configuration via Protocol (CvP)-relatedroutine in the kernel driver.

Refer to the CvP section for more information.

aclpci_queue.c File that implements a queue structure for use in the kerneldriver. Such a queue structure eases programming.

Related Information

• aocl install on page 1-39

• SG-DMA on page 1-16

• CvP on page 1-31

• Jungo Connectivity Ltd. website

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SG-DMAFor more information on scatter-gather direct memory access (SG-DMA), visit the Modular SG-DMApage on the Altera Wiki website.

Hardware

The acl_dma_core.qsys file encapsulates and parameterizes the modular SG-DMA hardware. It presentsslave ports for the control and status registers (dma_csr) and the descriptors (dma_descriptors). It alsoprovides separate masters for read and write operations. The acl_dma .qsys file is the component instanti‐ated in the board.qys system. It adds the following features:

• An address span extender for non-DMA memory accesses

• A merged read/write master

The merged read/write master issues constant bursts of size 16. As a result, it suffers 1/16 efficiency degradation from sharing the time interface. However, because the bandwidth of this unit exceeds thebandwidth of the PCI Express (PCIe) connection by more than this amount, there is no observable host-to-memory bandwidth degradation.

Software

When the memory-mapped device (MMD) receives a request for data transfer, it uses DMA when both of the following conditions are true:

1. The transfer size is bigger than 1024 bytes.

2. There are 64-byte alignments with the starting addresses for both the host buffer and the device offset.

Perform the following tasks to carry out a DMA transfer:

1. Check if there are remaining bytes to be sent.

2. Unpin the memory from the previous transfer.

3. Pin the memory for the new transfer.

4. Set up the Address Translation Tables on the PCIe.

5. Create and send the DMA descriptor.

6. Wait until the DMA finishes and then repeat Step 1.

Attention: For the Stratix V Network Reference Platform (s5_net), this implementation is inside theLinux kernel driver at /linux64/driver/aclpci_dma.c. For Windows systems, theimplementation is inside the MMD at \source\host\mmd\acl_pcie_dma_windows.cpp.

Related Information

Modular SG-DMA page on Altera Wiki

DDR3 as Global Memory for OpenCL ApplicationsThe Stratix V Network Reference Platform (s5_net) targets a computing card that has two banks of 4gigabytes (GB) x72 DDR3-160 SDRAM.

Completion of the tasks below are necessary to access these banks as global memory for OpenCLapplications.

For more information on the Altera DDR3 UniPHY intellectual property (IP), refer to the External Memory Interface Handbook.

DDR3 IP Instantiation on page 1-17

1-16 SG-DMAOCL008-14.1.0

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DDR3 Connection to PCIe Host on page 1-17

DDR3 Connection to OpenCL Kernel on page 1-18

Related Information

External Memory Interface Handbook

DDR3 IP Instantiation

The Stratix V Network Reference Platform (s5_net) uses two Altera DDR3 controllers with UniPHYintellectual property (IP) to communicate with the physical memories.

The table below describes the IP configuration settings:

IP Parameter Configuration Setting

Timing Parameters As per the computing card's data specifications.

Phase-locked loop (PLL)/delay-lockedloop (DLL) Sharing

s5_net is configured such that both memory controllers canshare the same PLL and DLL.

Avalon Width Power of 2 Currently, OpenCL does not support non-power-of-2 buswidths. As a result, s5_net uses the option that forces the DDR3

controller to power of 2. Use the additional pins of this x72 corefor error checking between the memory controller and thephysical module.

Byte Enable Support OpenCL requires byte-level granularity to all memories;therefore, byte-enable support is necessary in the core.

Performance Enabling reordering and a deeper command queue look-aheaddepth might provide increased bandwidth for some OpenCLkernels. For a target application, adjust these and otherparameters as necessary.

Debug Debug is disabled for production.

After you instantiate the UniPHY IP, you typically need to run the _pin_assignments.tclTcl script to add additional constraints to the Quartus II project. For more information on this process,refer to the External Memory Interface Handbook.

Related Information

External Memory Interface Handbook

DDR3 Connection to PCIe HostConnect all global memory systems to the host via the OpenCL Memory Bank Divider component.

The Altera DDR3 UniPHY intellectual property (IP) core has two banks where their width and addressconfigurations match those of the DDR3 SDRAM. Altera tunes the other parameters such as burst size,

pending reads, and pipelining. These parameters are customizable for an end application or board design.The Avalon master interfaces from the bank divider connect to their respective memory controllers. TheAvalon slave connects to the PCI Express (PCIe) and direct memory access (DMA) cores. Implementa‐tions of appropriate clock crossing and pipelining are based on the design floorplan and clock domainsspecific to the computing card. The Altera SDK for OpenCL Custom Platform Toolkit User Guide specifiesthe connection details of the snoop and memorg ports.

Important: Instruct the host to check for the successful calibration of the memory controller.

OCL008-14.1.0

2014.12.15 DDR3 IP Instantiation 1-17


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The board.qsys system uses a custom IP component named UniPHY Status to AVS to aggregate differentUniPHY status conduits into a single Avalon slave port named s. This slave connects to thepipe_stage_host_ctrl component so that the PCIe host can access it.

Related Information

Altera SDK for OpenCL Custom Platform Toolkit User Guide

DDR3 Connection to OpenCL KernelThe OpenCL kernel needs to connect directly to the memory controller via a FIFO-based clock crosser.

A clock crosser is necessary because the kernel interface for the compiler must be clocked in the kernelclock domain. In addition, the width, address width, and burst size characteristics of the kernel interfacemust match those specified in the bank divider connecting to the host. Appropriate pipelining also existsbetween the clock crosser and the memory controller.

QDRII as Heterogeneous Memory for OpenCL ApplicationsThe OpenCL heterogeneous memory feature allows Altera Software Development Kit (SDK) for OpenCL(AOCL) users to take advantage of the nonuniform memory architecture in a Custom Platform.

An AOCL Custom Platform groups memories with similar characteristics into a single global memory

system. Each Custom Platform has a designated default global memory system. In the case of the Stratix VNetwork Reference Platform (s5_net), the default global memory system consists of the two DDR3memory banks. The default global memory system must start at base address 0 from the host's perspec‐tive. Both the hardware design and the board_spec.xml file in the Custom Platform reflect this addressassignment. In s5_net, the DDR global memory system is named DDR.

In addition to the DDR global memory system, the computing card that the s5_net Reference Platformtargets includes four banks of quad data rate (QDR) memory. These four banks belong to a globalmemory system named QDR. AOCL users can only allocate memory in the QDR global memory systemusing an attribute on their global memory buffers. All addressable global memory must be contiguousfrom the host's perspective; therefore, the QDR memory base address must start where the DDR memory ends.

For more information on the Altera QDR UniPHY intellectual property (IP), refer to the External

Memory Interface Handbook.

The procedure for implementing the QDR subsystem is similar to the one outlined in the Developing Your Custom Platform section. Below is a list of high-level tasks:

1. Instantiate and parameterize the UniPHY memory controllers.

2. Connect the UniPHY memory controllers to the host via a new OpenCL Memory Bank Dividerinstance.

3. Connect the UniPHY memory controller to the UniPHY Status to AVS component.

4. Export the UniPHY memory controller to the OpenCL kernel via clock-crossing bridges.

1-18 DDR3 Connection to OpenCL KernelOCL008-14.1.0

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Below are special QDR subsystem design considerations for s5_net:

• QDR provides separate read and write ports.

By default, the OpenCL Memory Bank Divider produces a single bidirectional master for each memory controller. In Qsys, select the Separate read/write ports option to support separate read and writemasters. With respect to the kernel, instantiate clock crosses and separate read and write interfaces.

• The 275 MHz QDR afi clock and 4-to-1 multiplexing in the bank divider make it difficult to meettiming.

To achieve timing closure robustly, open the qdr.qsys file in Qsys, and select the option to pipeline theoutputs in the OpenCL Memory Bank Divider memory_bank_divider_1. Doing so adds a pipelinestage for each master that the bank divider creates.

Related Information

• Developing Your Custom Platform on page 1-3

• External Memory Interface Handbook

Host Connection to OpenCL KernelsThe PCI Express (PCIe) host needs to pass commands and arguments to the OpenCL kernels via the

control register access (CRA) Avalon slave port that each OpenCL kernel generates. The OpenCL KernelInterface component exports an Avalon master interface (kernel_cra) that connects to this slave port.The OpenCL Kernel Interface component also generates the kernel reset (kernel_reset) that resets alllogic in the kernel clock domain.

The Stratix V Network Reference Platform (s5_net) instantiates the OpenCL Kernel Interface componentand sets the number of global memory systems parameter to 2. The parameter setting is 2 because s5_nethas DDR and QDR memories. Below is a list of connection settings in s5_net:

• For the default DDR memory, the generated memorg_host0x018 conduit must connect to the DDR bank divider (memory_bank_divider_0).

• For the default DDR memory, the config_addr attribute in the board_spec.xml file must be set to0x018.

• For the QDR memory, the memorg_host0x100 conduit must connect to the QDR bank divider(memory_bank_divider_1).

• For the QDR memory, the config_addr attribute in the board_spec.xml file must be set to 0x100.

Implementation of UDP Cores as OpenCL ChannelsOpenCL kernels can communicate directly with I/O using the Altera Software Development Kit (SDK) forOpenCL (AOCL) channels extension.

For the Stratix V Network Reference Platform (s5_net), Altera uses the PLDA quick user datagramprotocol (QuickUDP) intellectual property (IP) core to implement a full UDP stack on top of the available10 gigabits per second Ethernet (GbE) channels on the card. QuickUDP provides an Avalon Streaming(Avalon-ST) interface that can connect directly to the OpenCL kernel, allowing it to send and receiveUDP network traffic without concern for UDP or lower-level protocols.

Attention: The UDP Hardware Stack QuickUDP IP is a licensed IP from PLDA. Refer to the PLDAwebsite for information on acquiring and installing the appropriate license.

Caution: Improper installation of the QuickUDP IP license causes the AOCL users to encounter thefollowing error message when they compile with a Custom Platform that contains theQuickUDP IP:

OCL008-14.1.0

2014.12.15 Host Connection to OpenCL Kernels 1-19


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Error (292014): Can't find valid feature line for core PLDA

QUICKTCP (73E1_AE12) in current license.

There is no actual dependency on the TCP Hardware Stack QuickTCP IP from PLDA.

QuickUDP IP Instantiation on page 1-20

QuickUDP Configuration via PCIe-Based Host on page 1-20

QuickUDP Connection to OpenCL Kernel on page 1-20

Related Information

PLDA website

QuickUDP IP InstantiationThe Stratix V Network Reference Platform (s5_net) instantiates two quick user datagram protocol(QuickUDP) intellectual property (IP) cores because the computing card it targets has two 10 gigabits persecond Ethernet (Gb) channels.

The two 10 Gigabit Media Independent Interface (XGMII) interfaces from these cores connect to a single10GBASE-R PHY with two channels. The Verilog instantiation of the PHY IP core is in the quickudp_wrapper.v file. This file contains parameters such as the multitenant unit (MTU) and the number of sessions supported. Most parameters are accessible via QuickUDP's Avalon Memory-Mapped (Avalon-MM) slave interface.

QuickUDP Configuration via PCIe-Based HostAltera Software Development Kit (SDK) for OpenCL (AOCL) users need to set their own parameters suchas media access control (MAC), intellectual property (IP) address, ports, and destinations. Altera providesaccess to the quick user datagram protocol (QuickUDP) configuration space to the host over PCI Express(PCIe) by connecting pipe_stage_host_ctrl to the config_udp0 and config_udp1 interfaces of theudp.qsys subsystem. AOCL users can then configure the QuickUDP settings in their host software usingthe application programming interface (API) in the aocl_net.h header file available in the Stratix VNetwork Reference Platform (s5_net).

QuickUDP Connection to OpenCL KernelEach quick user datagram protocol (QuickUDP) core produces a read and write stream for a total of fourAltera Software Development Kit (SDK) for OpenCL (AOCL) channels available to the kernel. Thesestreams cross into the kernel clk domain and are listed in the board spec.xml file.

Attention: AOCL supports only basic Avalon Streaming (Avalon-ST) with no packet support.

QuickUDP provides an Avalon-ST interface with full packet support along with additional metadataabout the payload. Because OpenCL does not support the packet extensions, the packetization signals areconverted to data, and the AOCL user's application must handle all packetization.

QuickUDP also provides additional metadata that the application can use. For a full explanation of thesesignals, refer to the QuickUDP documentation on the PLDA website. In the Stratix V Network Reference

Platform (s5_net), the payload, packetization signals, and metadata are concatenated into a single 256-bitwide vector exported as an AOCL channel.

1-20 QuickUDP IP InstantiationOCL008-14.1.0

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Use the information in the following table to access the desired components of the channel's data:

Table 1-1: Bit Mapping for the 256-Bit AOCL Channel to QuickUDP

Bit Range Name Description

[0:127] payload Packet payload

[128] sop Start of packet signal

[129] eop End of packet signal

[130:133] empty On EOP, this field indicates how many bytesare unused

[134:149] payload_size Size of the packet

Set to 0 for outbound packets

[150:181] rem_ip Indicates the remote IP for incoming packets

[182:197] rem_port Indicates the remote port for incoming packets

[198:205] channel Avalon channel

[206] error Avalon error signal

Related Information

PLDA website

FPGA System DesignTo integrate all components, close timing, and deliver a post-fit netlist that functions in the hardware, youmust first address several additional FPGA design complexities. These design complexities include arobust reset sequence, establishment of a design floorplan, global routing management, pipelining, andintellectual property (IP) encryption. Optimizations of these design complexities occur in tandem withone another in order to meet timing and board hardware optimization requirements.

Clocks on page 1-22

Resets on page 1-22

Floorplan on page 1-23

Global Routing on page 1-24

Pipelining on page 1-25

Encrypted IPs on page 1-25

OCL008-14.1.0

2014.12.15 FPGA System Design 1-21


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Clocks

The following clock domains affect the Qsys hardware system:

• 250 MHz PCI Express (PCIe) clock

• 200 MHz DDR3 clock

• 275 MHz quad data rate (QDR) clock

• 156.25 MHz ethernet clock

• 100 MHz general clock (config_clk)• Kernel clock that can take on any clock frequency

With the exception of the kernel clock, the Stratix V Network Reference Platform (s5_net) is responsiblefor closing timing of these clocks. However, because the board design must clock cross all interfaces in thekernel clock domain, the board design also has logic in this clock domain. It is crucial that this logic isminimal and achieves an Fmax higher than typical kernel performance.

Related Information

Guaranteed Timing Closure on page 1-26

Resets

The FPGA system design includes the implementation of the following reset drivers:1. The por_reset_counter in the board.qsys system implements the power-on-reset. This reset issues a

reset for a number of cycles after the FPGA completes configuration. It resets all the hardware on thedevice.

2. The PCI Express (PCIe) bus issues a PERST reset that resets all hardware on the device.

3. The OpenCL Kernel Interface component issues the kernel_reset that resets all logic in the kernelclock domain.

The first two resets are combined into a single global_reset; therefore, there are only two reset sourcesin the system. However, these resets are explicitly synchronized across the various clock domains,resulting in several reset interfaces.

Important notes regarding resets:

1. Synchronizing resets to different clock domains might cause several high fan-out resets.

Qsys automatically synchronizes resets to the clock domain of each connected component. In doingso, Qsys instantiates new reset controllers with derived names that might change when the designchanges. This name change makes it difficult to make and maintain global clock assignments to someof the resets. As a result, for each clock domain, there are explicit reset controllers. For example,global_reset drives reset_controller_pcie and reset_controller_ddr3a; however, they aresynchronized to the PCIe and DDR3 clock domains, respectively. Because both of these resets havehigh fan-out signals, they are assigned to global routing in the Quartus II Settings File (.qsf ).

2. Resets and clocks must work together to propagate reset to all logic.

Resetting a circuit in a given clock domain involves asserting the reset over a number of clock cycles.

However, your design may apply resets to the phase-locked loops (PLLs) that generate the clocks for agiven clock domain. This means a clock domain can hold in reset without receiving the clock edgenecessary for synchronous resets. In addition, a clock holding in reset might prevent propagation of a

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2014.12.15


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reset signal because it is synchronized to and from that clock domain. Avoid such situations by ensuring that your design satisfies the following criteria:

• Generate the global_reset

aocl s5 net platform

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