United States Patent [191 Slechta, Jr. et a1.

4,384,325 May 17, 1983

[11]

[45]

[54] APPARATUS AND METHOD FOR SEARCHING A DATA BASE USING VARIABLE SEARCH CRITERIA

[75] Inventors: Leo J. Slechta, Jr., Rosemount; Bennett W. Manning, Eagan; Nancy E. Precksliot, Minneapolis; Howard M. Wagner, Roseville, all of Minn.

[73] Assignee: Sperry Corporation, New York, NY.

[21] Appl. No.: 161,983

[22] Filed: Jun. 23, 1980

[51] Int. Cl.3 .............................................. .. G06F 7/34 [52] US. Cl. .................................................. .. 364/200 [58] Field of Search 364/200 MS File, 900 MS File

[56] References Cited U.S. PATENT DOCUMENTS

3,648,254 3/1972 Beausoleil 364/200 3,906,455 9/1975 Houston 364/200 4,115,850 9/1978 Houston 364/200 4,130,867 12/1978 Bachman . . . . . . . . .. 364/200

4,152,762 5/1979 Bird . . . . . . . . . . . . .. 364/200

4,221,003 5/1980 Chang 364/900 4,267,568 ll/1980 Dechant 364/200

Primary Examiner-Gareth D. Shaw Assistant Examiner—Stephen A. Soffen

( 4O

DATA BASE

MEMORY

Attorney, Agent, or Firm—Wil1iam C. Fuess; Kenneth T. Grace; Marshall M. Truex

[57] ABSTRACT Apparatus for and method of searching a data base using variable search criteria. The data base consists of a set of ?les or portions thereof. Each ?le is divided into a number of records whereby all records of a given ?le have the same format but the records of different ?les may have different formats. A ?eld format register is used to de?ne the format of the records within a given ?le. The ?eld format register speci?es the location and width of each ?eld within a record. To perform a search, a ?eld-by-?eld comparison of each record is made to a reference word. The comparison yields a less than, equal to or greater than result for each ?eld of each record. A ?eld comparison register describes the expected result of the ?eld-by-?eld comparison. A given ?eld is designated true if the comparison yields the expected result speci?ed for that ?eld in the ?eld comparison register. A given ?eld is designated false if the comparison yields other than the expected result speci?ed in the ?eld comparison register. A hit on a given record is de?ned as satisfying a Boolean expres sion using the ?eld-by-?eld true/false de?nitions as input variables. A given record is a miss if the Boolean expression is not satis?ed.

4 Claims, 18 Drawing Figures

REFERENCE WORD 2 42

REFERENCE WORD I

new '‘ 45 FORMAT coMPARAroRs REGISTER

44\ (LT/EQ/GT) FIELD /-47

COMPARISON :9 EQUAL REGISTER TEST

(Tau: /FALSE 1

BOOLEAN r" 43 FLAG

MEMORY

45\ H

BOOLEAN BOOLEAN " “9

EXPRESSION EVALUATOR

v

(HlT/ MISS)

U.S. Patent May17, 1983 Sheetlofll 4,384,325

--|o COMPUTER

Fig. I I~|| P-IOO

HSSF

2| ~22 PROCESSOR PROCESSOR

‘ I-so £-3| [23 < INTERNAL BUS >

I-32 I._33 1-34 I/Q MEMORY HSSF

K24 \25 \:oo COMPUTER

2°] Fig. 2

BYTE I23456789lOl|l2|3l4|5|6l7|8|9 — - - - - - - - --3Q3|32

I}IEOIHOEOHEOiOEOEI{OEOEOEOEI |E—>m. El llllllllll ||||1 ____ 1

t t— B-BIT FIELD 40-BIT FIELD

' 32" BIT FIELD

24"BIT FIELD

IS-BIT FIELD

8-BIT FIELD

US. Patent May 17, 1983 Sheet 2 of 11 4,384,325

(4| r 40

REFERENCE WORD 2 {42

DATA BASE

MEMORY REFERENCE WORD I

43\ U FIELD »- 46

FORMAT t) COMPARATORS REGISTER

44 (LT/EQ/GT)

\ FIELD p47 COMPARISON > EQUAL REGtSTER TEST

U (TRUE I FALSE )

aoouzm "'48 FLAG

MEMORY

453 H "' 49

BOOLEAN : BOOLEAN EXPRESSION EVALUATOR

( HIT/ MISS )

U.S. Patent May 17, 1983 Sheet 3 of 11 4,384,325

I I (101

< ,7 HSSF BUS

COMPARE COMPARE CONTROLLER ARRAY ARRAY

(I28 BITS: IK) (I28 BITS: IKI

200} 300] ° . _ 302/ ' . .

COMPARE COMPARE ARRAY o 0 0 ARRAY

(I28 BITSxlK) (I28 BITSxlK)

102 301 303 HSSF

IMTERFACE '00

101 f HSSF BUS >

V r103 —] h MPC BUS A I

INTERFACE , I LOG'C MPC SEQUENCER I

220/ 240/ 260/ | CONTROLLER!

102 \200

U.S. Patent May17, 1983 Sheet6 of 11 4,384,325

r103 < MPC BUS

f ‘ T T l A l

- '6 1s, a‘, “i 16, I6’, 15, m” I 26l 262 1 f if 2,63 ‘r258 ‘(269

BOOLEAN LIMIT FLD EVALUATOR REG ADDR MDROU MDROL MEMORY REG

32x|6 is? 264 266 270 27!

4/ r f L DELAY H|T REG STACK MDRIU MDRIL

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RD/WR/SEARCH MAR F272 SEQUENCER STACK 276

\ .6, f 265 I

CLOCK

273 ‘Z274 ‘Z275 L SEQUENCER

6i 6, no, \260 16,16, ‘ ' V v v

< HSSF BUS > 101/

U.S. Patent May 17, 1983

(DUI-POIN

O- FIELD (O-IZ? COMBINATIONS) l- OPERATOR

__F_'ig. I00

WORD O

UI-DOIN

Sheet 7 of 11 4,384,325

O= AND I = XOR

2 = OR

3= NOT 4 = RIGHT PARENS

5 = LEFT PARENS

__@y. lOb

Fig. 10c

—->' '¢—50 ns SI .READ BOOLEAN EVALUATOR MEMORY

. FORM FLAG ADDRESS

.READ FLAG AT COMPARE ARRAY

. TRANSFER FLAG TO SEQUENCER

. SELECT FLAG OR STACK

.PERFORM BOOLEAN OPERATION

A~B+B'(C+D)

Fig. [0d

l5 7 O

( NOT (3) 0 FIELD VAR (A)

I AND (O) O FIELD VAR (B)

l OR (2) O FlELD VAR (B)

I AND (O) l RIGHT PARENS (4)

D FIELD VAR (C) l OR (2)

O FIELD VAR (D) I LEFT PARENS (5)

4,384,325 I

APPARATUS AND METHOD FOR SEARCHING A DATA BASE USING VARIABLE SEARCH

CRITERIA

BACKGROUND OF THE INVENTION

The present invention generally relates to apparatus for and methods of searching digital bases and more speci?cally relates to searching through the utilization of user speci?ed variable search criteria.

Performing complex searches using general purpose processors can prove quite inef?cient if multiple in structions are required to operate upon each ?eld of each record. Yet the search tasks may be quite simple in nature and very repetitive in relation to the normal tasks accomplished by general purpose processors. A special purpose processor can be designed which will ef? ciently search a given large data base. Such special purpose processors are common in the communication industry, for example. Most such processors, however, are not sufficiently flexible to be applied to a wide range of data base search problems.

SUMMARY OF THE INVENTION

The present invention has a number of features which greatly enhances the flexibility of efficient data base searches. A ?eld format register permits the format of each record of a ?le to be speci?ed by the user. This ?eld format register speci?es the width (i.e., how many bytes) and location (i.e., which bytes) of each ?eld in a record. Thus, enhanced flexibility is available in de?n ing the format of the information within the data base. A second important feature of the present invention is

the comparison of each record on a ?eld-by-?eld basis to a reference word. This comparison yields an indica tion of whether a ?eld is less than, equal to or greater than the corresponding ?eld of the reference word. This indication (i.e., less than, equal to, or greater than) is compared against an expected result for that ?eld. The expected result (i.e., less than, equal to, or greater than) is stored in the ?eld comparison register on a ?eld-by-?eld basis. If the indication for a ?eld following comparison is the same as the expected result, that ?eld of that record is de?ned to be true. If the indication and

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25

30

35

the expected result are different, that ?eld of that record ‘ is de?ned to be false. The actual hit or miss determination for a given re

cord is made by determining whether a Boolean Ex pression supplied by the user is or is not satis?ed by the true and false determinations of the ?elds within that record. This feature provides great ?exibility in specify ing very complex searches, because it permits a logical relationship amongst the individual ?eld-by-?eld arith metic comparisons. The Boolean expression is executed using the true and false determinations of each record as inputs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows the High Speed Search Function in its outboard con?guration. FIG. 2 shows the High Speed Search Function in its

inboard con?guration. FIG. 3 shows the operation of a complex search. FIG. 4 shows the overall block diagram of the High

Speed Search Function. FIG. 5 is a block diagram of CONTROLLER 200.

50

65

2 FIG. 6 is a block diagram of one COMPARE AR

RAY. FIG. 7 shows a possible con?guration of the ?eld

format register. FIG. 8 shows the circuitry used to perform the ?eld

by-?eld comparison. FIG. 9 is a block diagram of SEQUENCER 260. FIG. 10a is the format used for each byte of the B001

ean Expression table. FIG. 10b lists the de?ned Boolean Operators. FIG. 100 shows the Boolean Expression table for a

sample Boolean Expression. FIG. 10d shows the sample Boolean Expression. FIG. 11 shows the detailed circuitry for the ?rst two

stages of the Boolean Evaluator. FIG. 12 shows the detailed circuitry for the last two

stages of the Boolean Evaluator. FIG. 13 shows the detailed circuitry for stages three

and four of the Boolean-Evaluator. FIG. 14 shows the pipelined timing of the Boolean

Evaluator. FIG. 15 shows execution of a sample Boolean Ex

pression. DETAILED DESCRIPTION OF THE

PREFERRED EMBODIMENT

The preferred embodiment of the present invention has been incorporated into a product of the assignee of this invention. The product is called the High Speed Search Function. Other aspects of the detailed con struction may be found in the related United States patent applications entitled, High Speed Data Base Search System, Ser. No. 161,993 and Variable Speed Synchronous Clock, Ser. No. 161,987 also assigned to the assignee of this invention. FIG. I shows the High Speed Search Function,

HSSF 100, employed in the outboard con?guration. HSSF 100 is coupled to COMPUTER 10 via Input /Output cable 11. In the outboard con?guration, HSSF 100 appears to COMPUTER 10 as a peripheral device. The outboard con?guration is most desirable for sys tems in which COMPUTER I0 is in existence and no physical changes are deemed desirable. The primary disadvantages of the outboard con?guration are the bandwidth limitation imposed on the INPUT/OUT PUT Cable 11 and the software overhead within COM PUTER 10 required to communicate with HSSF 100 as a peripheral device. FIG. 2 shows HSSF 100 used in the inboard con?gu

ration. As can be seen, HSSF 100 is located physically within COMPUTER 20. In this con?guration, HSSF 100 is provided with input power and structural support from COMPUTER 20. Other resources may be shared as well. The most signi?cant advantages of the inboard con?guration accrue from the communication path between HSSF 100 and the other elements of COM PUTER 2|]. Through the use of INTERNAL BUS 23, HSSF 100 communications with PROCESSOR 21 and 22, I/O 24, and MEMORY 25. By using INTERNAL BUS 23, the bandwidth and control structure may be optimized to produce the highest performance with the lowest software overhead. FIG. 3 shows the overall operation of HSSF 100.

Notice that the operation is the same whether HSSF 100 is employed in the inboard or the outboard con?gu ration. The entire data base to be searched is loaded into DATA BASE MEMORY 40. Usually this will be a complete ?le, though partial ?les may be searched with

4,584,325 3

some degradation in overall system performance. DATA BASE MEMORY 40 has one addressable loca tion for each of the records to be searched. Therefore, the basic ‘word size (in bits) of DATA BASE MEM ORY 40 must be at least equivalent to the record size (in bits). REFERENCE WORD 1 42 and REFERENCE WORD 2 41 each store an entire record. For normal searches, only REFERENCE WORD 1 42 is used. For range searches, both are used permitting “within range" and “without range" comparisons. FIELD FORMAT REGISTER 43 de?nes the for

mat of each record of the ?le (in DATA BASE MEM ORY 40) and the REFERENCE WORD(s). It is as sumed that all records during a given search have the same format. However, because FIELD FORMAT REGISTER 43 is loaded to initiate a search, consider able format ?exibility is achieved. As a practical consid eration, FIELD FORMAT REGISTER 43 is byte oriented rather than bit oriented and de?nes each ?eld of a record by position (in the record) and length in bytes. COMPARATORS 46 makes an arithmetic compari

son between each record from DATA BASE MEM ORY 40 and the REFERENCE WORD(s). This arith metic comparison is done on a ?eld-by-?eld basis as de?ned by FIELD FORMAT REGISTER 43, but all ?elds are compared in parallel. For a normal search, arithmetic comparison yields a less than, equal to, or greater than result for each ?eld of a record. For a range search one such indication (i.e., less than, equal to, or greater than) is produced for each REFERENCE WORD for each ?eld of the record. By structuring DATA BASE MEMORY 40 to have one record per addressable location, making COMPARATORS 46 and the REFERENCE WORD’s one record wide, and utilizing FIELD FORMAT REGISTER 43, all ?elds of an entire record are compared in parallel using a single read access to DATA BASE MEMORY 40.

Before initiation of a search, FIELD COMPARI SON REGISTER 44 is loaded with an expected result for each arithmetic comparison on a ?eld-by-?eld basis. The expected result is less than, equal to, or greater than. EQUAL TEST 47 performs a logical comparison between the ?eld-by-?eld results yielded by COMPAR ATORS 46 (i.e., arithmetic comparison) and the ex pected results in FIELD COMPARISON REGISTER 44. EQUAL TEST 47 yields a true for a given ?eld if the actual result from COMPARATORS 46 is the same as the expected result from FIELD COMPARISON REGISTER 44. The use of the arithmetic comparison followed by the logical comparison is important since the inputs (i.e., ?le to be searched and REFERENCE WORD(s) must be arithmetically compared to achieve the desired result, whereas the ?nal output (i.e., hit or miss) is logical. Again COMPARATORS 46 perform an arithmetic comparison whereas EQUAL TEST 47 yields a purely logical (i.e., true or false) output. BOOLEAN FLAG MEMORY 48 stores the true/

false output of EQUAL TEST 47. The contents of BOOLEAN FLAG MEMORY 48 are used as inputs to BOOLEAN EVALUATOR 49. BOOLEAN EX PRESSION 45 is supplied at initiation of a search and is used to specify the relationship between ?elds during a search. BOOLEAN EXPRESSION 45 may be quite simple or quite complex. BOOLEAN EVALUATOR 49 determines whether BOOLEAN EXPRESSION 45 is or is not satis?ed by the true/false indications for a record stored within BOOLEAN FLAG MEMORY

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40

45

55

60

4 48. If BOOLEAN EXPRESSION 45 is satis?ed, the record is de?ned as a hit. Otherwise the record is de ?ned as a miss. Notice that even though all ?elds of a record are arithmetically and locally compared once and only once, a given BOOLEAN EXPRESSION may or may not make use of the results for a given ?eld. An actual example of a comparison is discussed below. FIG. 4 shows the internal construction of HSSF 100.

HSSF BUS 101 supplies the main communication path between CONTROLLER 200 and the COMPARE ARRAY’s. COMPARE ARRAY 300 is the basic unit of DATA BASE MEMORY 40. It has the capacity to store a ?le of up to 1024 records wherein each record has up to 128 bits. To use HSSF 100 for ?les having more than 1024 records, additional COMPARE AR RAY’s are added in the dimension of COMPARE ARRAY 301. Each COMPARE ARRAY added in that dimension provides 1024 more addressable locations, thereby providing for up to 1024 more records per ?le. To expand the maximum record size, COMPARE AR RAY’s are added in the dimension of COMPARE ARRAY 302. Each COMPARE ARRAY added in that dimension increases the record size by 128 bits. The COMPARE ARRAY’s are identical and contain the necessary hardware (e.g., portions‘ of REFERENCE WORD 1 42, REFERENCE WORD 2 41, FIELD FORMAT REGISTER 43, COMPARATORS 46, etc.) to permit the expansion in either dimension. HSSF 100 can accommodate up to 16 COMPARE ARRAY’s providing a ?le size of from L024 records of 2,048 bits each to 16,384 records of l28 bits each in increments of 1,024 records by 128 bits. CONTROLLER 200 contains the interface, control,

and sequencing logic needed to operate HSSF 100. Cable 102 couples HSSF 100 via CONTROLLER 200 to its external environment. FIG. 5 shows CONTROL LER 200 in more detail. INTERFACE LOGIC 200 is coupled to cable 102. INTERFACE LOGIC 220 is that element which is different in the inboard and outboard con?gurations. INTERFACE LOGIC 220 communi cates with the micro programmed controller, MPC 240, and SEQUENCER 260 via MPC BUS 103. MPC 240 provides overall control of HSSF 100 primarily for interface control, search initiation, and mode control. SEQUENCER 260 contains the hardwired circuitry which actually controls the timing of the search itself. Hardwired logic is required (instead of micro pro grammed logic) to meet the desired performance re quirements (i.e., basic normal search cycle time of one microsecond per record).

FIG. 6 shows the construction of one COMPARE ARRAY. TRANSCEIVERS 310 are used to interface to HSSF BUS 101a (i.e., 32 data bits of HSSF BUS 101). MEMORY 311 actually stores the data base. It is con structed using industry standard CMOS static random access memory (RAM) devices. REG 1 313 and REG 2 312 are 128 bit registers which store the records to be compared (i.e., contents of one addressable location of MEMORY 311 in REG 2 312 and REFERENCE WORD in REG 1 313). Notice that for a range search the arithmetic comparison is simply repeated. COMPARATORS 314 performs the arithmetic com

parison between the contents of REG 2 312 and REG 1 313. FIELD FORMAT REG 315 is a 16 bit register which de?nes the boundaries of each ?eld to COM PARATORS 314. Each bit position of FIELD FOR MAT REG 315 corresponds to a different byte of COMPARATORS 314.

4,384,325 5

FLAG REG 317 is a 32 bit register which has two bit positions for each byte of the I28 bit words compared by COMPARATORS 314. This is necessary, since in the worst case, FIELD FORMAT REG 315 could de?ne each byte of COMPARATORS 314 as a separate ?eld and the arithmetic comparison yields one of three results (i.e., less than, equal to, or greater than) for each ?eld. Exclusive-ORs 318 and 319 exclusive-OR the ?ags from FLAG REG 32 (i.e., the results from COM PARATORS 128) with the output of FIELD COM PARISON REG 316 (i.e., expected results). Notice that FIELD COMPARISON REG 316 is actually a RAM. The exclusive-ORing is done four bytes at a time (i.e., results of arithmetic comparison for four bytes are ex clusive-ORed with expected results for those four bytes). In this manner, Exclusive-ORs 318 and 319, along with gate 320, generate true/false indications for four bytes in parallel. The true/false indications (i.e., one bit per byte) are transferred via cable 335 to FLAG MEMORY 321. The arithmetic comparison results for the remaining bytes are similarly exclusive-ORed with the expected results.

Before initiation of a search, MEMORY 311 is loaded with all or a portion of the data base. REG 1 313 is loaded with the Reference Word (note REG 1 313 is loaded twice for range searches). FIELD FORMAT REG 315 is loaded with the description of the records loaded into MEMORY 311. FIELD COMPARISON REG 316 is loaded with the expected results of the arithmetic comparison for each byte. COMPARE ARRAY 300 performs the arithmetic and logical com parisons and loads FLAG MEMORY 321 with the

I true/false indications for each byte. FIG. 7 shows the format of FIELD FORMAT REG

315. One bit position is used for each byte of the 128 bit word of the COMPARE ARRAY. As the record size is expanded, FIELD FORMAT REG 315 is effectively expanded in the same manner as DATA BASE MEM ORY 40 (see also FIG. 4 and the discussions above). A binary one in a given bit position signi?es that a ?eld ends at the corresponding byte position of the records. Similarly, a binary zero in a given bit position signi?es that the corresponding byte is within a ?eld which ends at a different byte position in the record.

20

30

45 FIG. 8 shows the manner in which ?elds are de?ned ‘

for arithmetic comparison purposes. As explained above, FLAG REG 317, FIELD COMPARISON REG 316, Exclusive-ORs 318 and 319, gate 320, and FLAG MEMORY 321 handle each byte as if it were a separate ?eld, since in the worst case, each byte may be a ?eld. However, ?eld boundaries must be de?ned to COMPARATORS 314 to generate accurate arithmetic comparisons. COMPARATORS 314 consists of a num ber of simple monolithic COMPARATOR circuits 3140, 3141, . . . . Each COMPARATOR circuit (i.e.,

COMPARATOR circuit 3140, 3141, . . . ) is capable of performing a simple arithmetic comparison between one byte of REG 1 313 and the corresponding byte of REG 2 312. The function of FIELD FORMAT REG 315 is the tying together of adjacent bytes of COM PARATORS 314 as required. For multi-byte ?elds, the less than or greater than result of the most signi?cant byte is the arithmetic comparison result for the entire ?eld. If the most signi?cant byte is equal, however, the result of the next most signi?cant, not equal, byte is controlling on the entire ?eld. Of course, if all bytes of a ?eld are equal, the result for the ?eld is equal.

55

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6 Gates 3142 and 3143 supply the equal comparison

enable to COMPARATOR 3140 (i.e., N+ 1“ byte) and COMPARATOR 3141 (i.e., N'h byte), respectively. Notice that COMPARATOR 3140 (N+ l‘r byte) is enabled for equal comparison if FIELD FORMAT REGISTER 315 has the bit position set corresponding to the N'" byte. That means that COMPARATOR 3140 is the least signi?cant (or perhaps only) byte of a ?eld, and should therefore, be enabled for equal comparison. COMPARATOR 3140 is also enabled for equal com parison by gate 3142 if an equal to result is received from COMPARATOR 3141 (Nm byte). This will occur when all lesser signi?cant bytes of a ?eld also have an equal to result. Notice that the less than and greater than results are also propagated from less signi?cant to more signi?cant bytes. As explained above, the arithmetic comparisons are

made on a byte-for-byte basis in parallel. The result for each byte is propagated‘to FLAG REG 317 (see also FIG. 6). The function of FIELD FORMAT REGIS TER 315 is to tie results of less signi?cant bytes to more signi?cant bytes within the same ?eld whenever the more signi?cant byte has an equal to result. FIG. 9 shows SEQUENCER 260 in detailed block

diagram form. CLOCK 276 is used to generate the overall timing signals. The COMPARE ARRAYS are loaded and read via HSSF BUS 101 (See also FIG. 4). The major data interface is via the output memory data register, MDROU 268 and MDROL 269, and the input memory data register, MDRIU 270 and MDRIL 271. HIT STACK 266 simply stores the search hit record addresses. FLD ADDR REG 263 provides the addressing to

the COMPARE ARRAYS for the searches which are not all done in sequence (i.e., link ?eld is employed). RD/WR/SEARCH SEQUENCER 265 actually con trols the detailed operation of the COMPARE AR RAYS. DELAY REG 264 permits a variable search cycle time as a function of maximum number of bytes per ?eld and number of terms in the Boolean Expres slons.

BOOLEAN EVALUATOR MEMORY 261 stores the Boolean Expression in such a form as to be executed (or evaluated) by RD/WR/SEARCH SEQUENCER using the true/false logical compare results as inputs. FIG. 100 shows the format for each entry in BOOL

EAN EVALUATOR MEMORY 261 as initially pre pared by the host. The entry may specify an operator (i.e., Boolean operator) or an input variable (i.e., true or false indication for a speci?ed ?eld of a record). Each entry is eight bits wherein the most signi?cant bit (i.e., 27 or 2") is a binary zero to denote a variable or a binary one to denote a Boolean operator. If a variable is indi cated, the seven least signi?cant bits of the entry (i.e., 20-26 or 23-214) simply give the byte position of the most signi?cant byte of the desired ?eld. If a Boolean operator is indicated, the three least signi?cant bits of the byte (i.e., 20-22 or 23-210) de?ne the Boolean Opera tor.

FIG. 10b lists the six codes used to specify the six de?ned Boolean Operators. If we consider the expres sion shown in FIG. 10d as an example of a desired search de?nition, FIG. 10c shows the entry prepared to represent that expression. In this example, A, B, C, and D are the results of the logical comparison (i.e., either true or false) for ?elds, A, B, C, and D, respectively. A record is a hit (i.e., satis?es the search criteria) if:

4,384,325 7

(1) Field A of a record when arithmetically compared to ?eld A of the Reference Word does not yield the expected result (i.e., less than, equal to, or greater than speci?ed for ?eld A by FIELD COMPARISON REG ISTER 44 and Field B does; or

(2) Field B of a record when arithmetically compared against the corresponding ?eld of the Reference Word yields the expected result and either or both of ?elds C and D also do. The actual entry stored in BOOLEAN EVALUA

TOR MEMORY 261 is different in format though it contains the same information as the initially prepared entry. The format change occurs as a result of MPC 240

8 (See also FIG. 5) parsing the initially prepared entries to produce a more compact and easier to use representa tion of the expression. The parsing occurs during the loading of BOOLEAN EVALUATOR MEMORY 261 before initiation of a search. Below is included a portion of the listing of the micro program used by MPC 240 to control the search functions. Parsing of the initially prepared entries and loading of BOOLEAN EVALU ATOR MEMORY 261 utilizes the logic beginning at logical address LBEX (i.e., numerical address 000543). The entire microprogram listing may be found in the above identi?ed US. patent application entitled High Speed Data Base Search System.

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- 1011. 000551 15 00 121 05 4 2 00 :1 A0 5111 . Ac .RAM.A ce~1 .ccsAv . ccsAv-2 1010. 000552 15 00 121 011 4 :1 01 :1 L1 A~o.A11.Acc.A :cmr .ecsAv . 1019. 00055: 15 00 000 015 2 :15 2 101 A0. 00A1A. 1 com . . 1.0A0 5011-1 CHAR 5111 1 020. 000554 15 00 .111 05 4 2 10 2 1.1 A110.A1:.111.. 1 CI‘WT .0311 . 1.1As11 1011 2110 can 1021 . 000555 15 00 :101 05 4 :1 01 :1 1.1 A110.A11.A1:c. A 00111 .csAva . SAVE 1011 L1“ :11 1021 . 000550 15 00 000 015 2 :15 2 1.01 Ac.00A1A. 1 50111 . - USE LOAD BOY" 102:1. . 51111115

1 024. 000551 15 00 001 0 010 10 2 111 vecn .111. . 1 com .01 . 10 1.0A0 2010 1025. 000510 05 0'1 000 0 00:1 0:1 2 111 LC‘HI .sruoa . 1 000 FALSE . . coumen F011 1025. . 11 5111115

1 021 . 000511 15 00 000 150 :1 0 2 5111 0110. 1 00M . - 10211. 1' 00051.2 1 1 00 111 0 000 00 0 111 . .0 we: .5-1 . 5111" AGAIN UNTIL 1 025. _. COUNTER-0 1030. 00051: 15 00 311 05 4 2 10 2 1.1 A110.A0.11L. 1 00111 .0511 . 111514 1031 . 000514 15 00 1 1 1 05 4 2 01 :1 LI A110.A4.Acc .A crwr .csAv1 . sAve 1.1As11c0 110 10:12. 000515 15 00 201 011 2 00 :1 1.01 5 Ac . 11A11. A com .511110 . 151 151 0111111 10:12. 1 000515 0:1 0:1 205 0 000 00 0 m . .0 1:011 2:110. r0511 . 11 1101 151 0111111 10:14. 000511 15 00 1 11 015 2 00 a 101 A1: . 11A11.A 50111 .0511111 . 51101111! 0111511 10:15. . 5114111015115

1055. 000500 15 00 111 05 5 2 10 2 1:1 s0As.Ac .111. 1 00111 .0111 . 15s comlnul: 10:11. 000501 15 00 201 04 0 :1 00 :1 A1 111 . A11.11A14.A c0111 .enrus . 25110 FLAG 10:15. 1 - 000502 0:1 04 24s 0 000 00 0 111 . . 0 - can 1155,1101! . snun-Acc-wz 011A! 1029. 1 000502 0:1 05 25:1 0 000 00 0 1111 . .0 0011 1105.11011 . 1040. 1 000004 0:1 00 :11: 0 000 00 0 141 . . 0 0011 11102. 11111-1 . 51111011 1041 . 000005 15 00 001 0 010 10 2 110011 141 VECFLKL . 1 00111 .01 . 1042. 000505 05 01 000 0 005 0:1 2 1111 tcrmsruus. 1 0110 FALSE. . c111 - 01

I043. 000601 16 01) H7 076 2 00 J FUCH! LOl ACJHILA CONT .CSMII . 1044. 000510 10 00 002 05 4 :1 01 :1 r0511: 11 Ar1u.An.Acc .A CONT £50" ~ 1045. 00051 1 15 00 111 05 5 2 10 2 A01 s0A5.Ac .111. 1 50111 N 77 - gag-"cm" m" 1045. -

1041. 1 000512 0: 04 222 0 000 00 0 111 . .0 0511 1150.001 . DAVIE N01‘ 1045. 1' 000512 1 1 00 211 0 000 00 0 111 . . "PM J" 1 "'5" ‘""n 1045. 000514 15 00 :101 015 2 00 3 L0! Ac .11A14.A 1::1141 .CSAV3 . cum in WW5" "I5 1050. 000515 15 00 :100 05 4 :1 01 a u A110. R.Ac1:.A CONT 1'65"‘) - "i" 1051 . 1 000515 0:1 00 210 0 000 00 0 111 . .0 =50 TRULDPER - FUR" 1" B5" "'5' 1052. 000511 15 00 1 11 015 2 00 :1 101 A0 .111111.A c0111 .csAv1 . FORM 5514 INST 105:1. 000520 15 00 :100 00 4 :1 01 :1 1.1 Auu.A11.Acc.A 52:1 +g?évgpu . F011 2110 011411 1054. 1 000521 0:: 00 215 0 000 00 0 111 . .0 E - - 1055. 000522 15 00 :102 015 2 00 :1 N01 1.01 A0 . RAM. A com .c5Av4 . E51 502 HO" FOR 1055. -

1051. 0005221 15 00 20:1 05 5 2 10 2 A51 saAs.Ac.111..1 00111’ .020: . lF - 0 111511 N01 1055. '

1055. 1 000524 0:1 02 240 o 000 00 0 141 . . 0 - C1" "1 J‘E" ' 1050. 1 000525 11 00 2:1: 0 000 00 0 1111 . . 0 RPBA .516 - ‘5* 0' 3"” "9“ 1051 . 000525 15 00 :101 015 2 00 :1 _ 1.01 Ac . 11Au.A . 1052. 000521 15 00 :00 0s 4 :1 01 :1 L1 A110.A11.A1:0. A - - 105:. 000520 15 00 044 015 2 1:1 2 1.01 10.1w. 1 00111 .044 . 1101 FLAG 10 11151 1054 . 000521 15 00 205 05 4 :1 01 :1 1.1 AND.A11.Acc .A com . 11151 . 10 011511 1 055. 1 000522 0:1 00 155 0 000 00 0 111 . . can 11105.01‘! - 1 055. 000525 15 00 .101 015 2 00 :1 1.01 Ac . 11A14.A c0111 .c5Av3 ~ 1 051. 000524 15 00 000 115 -1 :1 01 :1 1.1 A110." . Acc.A c0111 .csAv0 - 1055. 000525 15 00 044 015 2 1s 2 1.01 A1: .1111. 1 00111 .044 . 1101 11110 10 11151 1050. 000535 15 00 205 05 4 :1 01 :1 L1 A110.A11.Ac0.A c0111 . 11151 . 111001111 0514 11151 1515, 1- 00.1631 . 0:1 00 215 0 000 00 0 111 . . 0 can 1005,0250 . 10 1100 111114 OPERA 1 01 1 . AND STORE

1012 . 0011540 15 00 1 11 015 2 00 :1 01:01 1.01 A1: . 11A14.A c0111 .c5Av1 .1 PREP 1Q 250 PASS 1 01:1. 000541 15 00 120 05 4 :1 01 :1 1.1 A110.AR. Acc,A - 1 014. 000542 15 00 :01 015 2 00 :1 1.01 A1: . RAM. A . - 1015. 1 000543 1 1 00 210 0 000 00 0 141 . . 0 RPDA .500112 . IEPiAY FOR 2ND H0" 1015. 1 000544 0:1 00 :112 0 000 00 0 1.11 . . 0 0511 111115 . XXI-l - "P0" “D E‘ 1011. 000545 15 00 1 1 1 015 2 00 :1 NO" 1.01 A: . RAH. A ' c0111 .05“ I - 1010. 000545 15 00 203 05 5 2 1o 2 A01 SBAS. Ac .KL. 1 COM 1201' - "m ' N“ 1015. 1 000541 03 02 :12 0 000 00 0 1 111 . . 0 can 02 .11111-1 . 1159B!" BAD El 1000. 000550 15 00 014 015 2 1 :1 2 11010 1.01 AC . 110. 1 com’ .014 . 10110 FLAG NOY 1081. 000551 16 00 301 O4 5 2 0O 3 Al ADD.AC.RAM.A CONT .CSAVII . 1052 . 1 000552 0:1 00 255 0 000 00 0 I111 . . CB" TRUE - F "3"‘ -

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ACC‘CHAR COUNT IF CRAR COUNT - 9 ALL CHAR AFR ' 0 TO HSSFISET END FLAG IN HEM INS TRU CC NOT 0 I LOAD INST FOR REM SIMU RAAI CELLS FIRST LOAO INOEX REGISTER RAM AODR TO SAVE BEN INST PRIOR TO KFR TO DETA- INC ADOII BY FABRICATEO INST RUC TO ACC XFER TO BEM BEN INST TO TEMP RAN. GO TO OPERATOR ROUTINE NANOLE THE LAST BEN INST RUC PRIOR TO AFR TO BEN FOR EVALUAI [ON SET 51 T I4 IN INSTR

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000404- I I 000406I I 2 0004IOI I 3 0004| 2-14

4,384,525

1202. 000762 15 O0 006 0 010 I0 1 MI VECR.HL,II CONT I05 . SKIP LDC 17 AND SET IZOJ. . UP CNIR FOR NEXT 5 l 204 . 000753 \6 00 001 076 3 I0 I LDI All . KL. l I CUNT .Ul . OOOOOt I21 GOOD El 1 205 . 000754 05 0| 000 O 003 00 3 Mi LCTR , . 1 C00 FALSE | I LOCATIONS I205. 000755 \5 00 001 04 G J l 0 I PREP3 M AOLLAR .KL . I CONT .01 - DDOUOZIQI 1207- T 000755 I l 00 355 O 000 00 l ill . . ll RPBA ‘ PREP3 - I208. . . 000010-27

1209. 000767 I6 00 017 O 010 I D 2 MI VECR. I‘L . I CONT . 017 . SETUP COUNTER ‘2X0. 000770 05 01 000 O 0021 O0 2 MI LCTR, . l CJCI FALSE , . TU IIRlTE NEXT \5 L0 121 l . OOOTTI I6 00 200 07E 2 l3 2 LD‘ AC . K0 . I CONT I0200 . SET UPPER Bl T INDIC I212. . ATE BAD El'S 1211. 000772 16 O0 001 D4 6 3 10 2 P3594 Al ADILAR. KLJ CONT .Ol - 100001 =30

FIGS. 11, 12 and 13 show the detailed construction of the Boolean Evaluator. FIG. 14 shows the overall Bool ean Evaluator timing, and FIG. 15 shows a timing ex ample.

Referring to FIG. 11, BOOLEAN EVALUATOR MEMORY 901 is loaded with the parsed entries from MPC BUS 103 before search initiation. The loading is accomplished using 16 bit words as shown. Actually only 15 bit words are required as is evident below. BOOLEAN EVALUATOR MEMORY 901 is ad dressed via ADDRESS COUNTER 900 which simply sequences through the addressable locations of BOOL EAN EVALUATOR MEMORY 901 to sequentially access the de?nitions of the Boolean operators and variables as required. The 15 bit output of BOOLEAN EVALUATOR MEMORY 901 is stored in D FLIP- ' FLOPS 902 at sequence S1. The 15 bit output of D FLIP-FLOPS 902 is divided as shown for transfer to D FLIP-FLOPS 904, D FLIP-FLOPS 905, MUX 906 and MUX 907. The two least signi?cant bit positions (i.e., bits 0 and 1) are transferred to D FLIP-FLOPS 905. Bit positions 2, 3, and 4 are transferred to both MUX 906 and MUX 907. D FLIP-FLOPS 905 receives bit posi tions 5,6, and 7. The remaining bit positions (i.e., 8-14) are transferred to D FLIP-FLOPS 904. As can be seen, the lower order bit positions (i.e., 0-7) specify variables in that these bit positions represent addressing informa tion used to address FLAG MEMORY 321 of the COMPARE ARRAYS. See FIG. 6. Notice that the addressing information is received through physical cables 101e, f and g (i.e., portions of I-ISSF 101). These physical cables correspond to the functional cables 913 and 914 of FIG. 11. MUX 906 and‘ MUX 907 normally select the output

of D FlIP-FLOPS 902 for transfer to FLIP-FLOPS 910 and 911, respectively. During loading, however, the three bit BOOLEAN CAL (i.e., calibrate) ADDR (i.e., address) signal is selected. The three bit outputs of MUX 906 and 907 are stored by FLIP-FLOPS 910 and 911. Cables 913 and 914 are used to address the Boolean Flag Memories (i.e., BFM 941 and BFM 942) in the COMPARE ARRAY’S as shown in FIG. 13.

Referring again to FIG. 11, D FLIP-FLOPS 905 receives bit positions 0, 1, 5, 6, and 7 from D FLIP FLOPS 902. Bit positions 0 and 1 are inverted by in verter 909 and supplied as signals H->FLMEM 0-1 to REG 943 as shown on FIG. 13. The corresponding two bit output is the selection input to MUX 945. As is dis cussed below, this is the byte selection from the flag memories (i.e., BFM 941 and 942). As can be seen in FIG. 11, bit positions 5, 6, and 7 are output from D FLIP-FLOPS 905 as three bit signals designated H_>FLEM 5-7 (Card 0-7) and H—+FLEM 5-7 (CARD 9-15). These are equivalent signals as shown. By refer ring to FIG. 13, it can be seen that signal H—>FLMEM 5-7 is used as the three bit selection input to MUX 940. As explained further below, MUX 940 selects one of the eight CARD ADR inputs corresponding to bit posi tions 5, 6 and 7 of the flag memories. As explained above, the most signi?cant bit positions

(i.e., bit positions 8-14) of BOOLEAN EVALUATOR

25

30

45

MEMORY 901 and hence D FLIP-FLOPS 902 are the control signals used to specify the Boolean operators. Referring again to FIG. 11, it is seen that bit positions 8-14 are stored within D FLIP-FLOPS 904. Notice that bit position 8 is also inverted by inverter 903 and stored in the inverse. Bit position 8 is output in both true and complement form as signals L—>F CARD SEL 0-7 and L—+F CARD SEL 8-15. These signals select either the eight lower order or eight higher order COMPARE ARRAY’s (i.e., cards since each COMPARE ARRAY is a single printed circuit card and differs from other COMPARE ARRAY’s only by the card position). The remaining six bit positions perform the major control functions in evaluating the Boolean Expression. These six bit positions are stored in D FLIP-FLOPS 908 at stage S3.

Referring to FIG. 12 it can be seen that these six bit positions are transferred to D FLIP-FLOPS 920 via cable 912. Notice that bit positions 11-14 are again stored during stage S5 in D FLIP-FLOPS 924. Bit position 14 is inverted by inverter 923 before storing at stage S5. The inverted bit position 14 is stored in D FLIP-FLOPS 933 at stage 6. The storing of these con trol signals in successive stages permits the six stage pipelining as discussed below. Bit positions 9 and 10 serve as two of the three selector inputs to MUX 919. The third selector input, called signal IF+FLMEM SEL, determines whether MUX 919 will select the FLAG 1 or FLAG 2 input. The signals L—>FLAG 2 and L—>FLAG 1 are received via lines 937 and 938 from MUX 945 (See also FIG. 13). These are essentially the Boolean Variables as read from BFM 941 and BFM 942. Referring again to FIG. 12, it can be seen that FLAG 1 and FLAG 2 are stored in FLIP-FLOPS 922 and FLIP-FLOPS 921, respectively. The remaining inputs to MUX 919 (i.e., data inputs 2, 3, 6, and 7) are from STACK 934. STACK 934 is a push-down/pOp-up stack which is used to provide the capability for using parenthesis in a given Boolean Expression. Inputs 2 and

t 6 of MUX 919 are the true outputs from STACK 934

50

55

whereas inputs 3 and 7 are inverted by inverter 918. MUX 919 selects one output from the true or comple

ment of FLAG 1, FLAG 2, or STACK 934. Therefore, selector input A0 (i.e., Bit position 9) permits selection of the true or complement of a term. Input Al (i.e., Bit position 10) permits selection of a ?ag or STACK 934. Input A2 (i.e., signal FLMEM SEL) permits selection of either FLAG 1 or FLAG 2 if a FLAG input is de sired. FLIP-FLOP 925 stores the selected output of MUX

919 during stage S5. Bit positions.“ and 12 are used during stage S5 as selector inputs to MUX 931. To be selected are the outputs of gate 926, gate 928, gate 930, or F/F 925. The output of gate 926 is the selected flag of STACK 934 (i.e., output of FLIP-FLOP 925) ORed with the true output of FLIP-FLOPS 932 which is derived from the previous output of MUX 931. This function corresponds to the ORing of terms in an ex pression. Similarly, the output of gate 930 is simply the ANDing of terms in an expression. The output of gate 928 is similarly the Exclusive -OR. The direct output of

4,384,325 13

F/F 925 is called a load. Therefore, MUX 931 selects from OR, AND, Exclusive -OR or Load of terms based upon selection by bit positions 11 and 12. D FLIP-FLOP 933 stores the complement of bit

position 14. Notice that the output of D FLIP-FLOP 933 is ANDed by gate 935 with the output of FLIP FLOP 932. This permits bit position 14 to enable output (i.e., hit or miss) at the end of an expression. FLIP FLOP 932 is also called the accumulator (or ACC) since it stores the current value of the expression at stage S6. FLIP-FLOPS 932 is loaded from the output of MUX 931. The output of MUX 931 is also used to load STACK 934. Notice that bit position 13 is used to push the stack down. Bit position 10 is used to pop the stack up. Because STACK 934 is only read on a pop (i.e., end paren in Boolean Expression), bit position 10 is also used as the selector input to MUX 919 for selecting the output of STACK 934. ‘

Referring to FIG. 13, the selection of Boolean Vari ables (i.e., ?ags) can be seen. The selection of the ?ags occurs during stages S3 and S4. As explained above, BFM 941 and 942 are physically located on the printed circuit cards as part of the COMPARE ARRAY’S. BFM 941 and 942 correspond to FLAG MEMORY 321 (See also FIG. 6). As seen in FIG. 6, BFM 941 and 942 are loaded with the ?ags from four bytes via cable 335. The signals H—>FLAG 0-3 are designated on FIG. 13. The write enables (i.e., input WE) to BFM 941 and 942 are designated signals L—>LD FLMEM l and L—>LD FLMEM 2, respectively. Addressing of BFM 941 and 942 is via cables 914 and 913 as explained above. REG 944 stores the four bit outputs of BFM 941 and

' 942 during stage 83. During stage S4, MUX 945 selects FLAG 1 and FLAG 2 and transfers these via lines 937 and 938 for evaluation as explained above. REG 944 is constantly enabled for output (i.e., input OE is grounded) and clocked via the 20 MHz CLOCK signal.

Selection by MUX 945 is based upon signals H->FLMEM 0—1 as stored during stage S3 in REG 943. As explained above, signals H—>FLMEM 0-1 are sim ply bit positions 0 and 1 inverted by inverter 909 (see also FIG. 11).

Referring again to FIG. 13, it can be seen that MUX 945 is enabled by one output of REG 943. MUX 940 selects one of eight card addresses based upon signal

5

14 AND, OR, XOR or Load). Hit position 14 signi?es END of the expression. Though the preferred embodiment of the present’

invention is incorporated into the High Speed Search Function product, those skilled in the art will readily see the application of the present invention to systems having signi?cantly different architectures. What is claimed is: l. A method of conducting a search of a data base

10 having a plurality of records comprising:

15

20

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45 I-I->FLMEM 5-7 as explained above. MUX 940 is en- ‘ abled for output whenever a low is present on line 949. This is a control signal used during translation of CARD ADR. FIG. 14 shows the overall timing of the Boolean

Evaluator which employs a six stage pipeline. Each stage requires approximately 50 nanoseconds as shown. The operation performed during each stage is shown. The reader may want to again consult FIGS. 11, 12 and 13 to review the circuitry which performs the desired function at each stage. As a convenience, the stages are noted. FIG. 15 shows an example of Boolean Evaluation

using the expressions:

The parsed Boolean operators and variable descriptions are read from BOOLEAN EVALUATOR MEMORY (i.e., BEM) 901 at stage S1. As explained above, the variables A, B and C are ?ags which are addressed using BEM bit positions 0-7. Bit position 10 speci?ed FLAG or STACK (and POP). Bit position 13 deter mines PUSH. Bit position 9 determines true or comple ment. Bit positions 11 and 12 specify function (i.e.,

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arithmetically comparing a plurality of ?elds of a record within said data base to a like plurality of corresponding ?elds of a reference word in order to derive a like plurality of arithmetic comparison ?rst results;

logically comparing said plurality of arithmetic com parison ?rst results of said arithmetically compar ing to a like plurality of user supplied expected results for said arithmetically comparing of said like plurality of fields of said record in order to derive a like plurality of logical comparison second results;

determining whether said plurality of logical compar ison second results of said logically comparing when used as a plurality of inputs to a user supplied Boolean expression do satisfy said user supplied Boolean expression;

indicating as a Boolean expression hit upon said re cord whenever said user supplied Boolean expres sion is satis?ed upon said determining and indicat ing as a Boolean expression miss upon said record whenever said Boolean expression is not satis?ed upon said determining; and

repeating said arithmetically comparing, said logi cally comparing, and said indicating for said plural ity of records within said data base;

whereby said Boolean expression hit indicates that a logical relationship amongst and between said like plurality of logical comparison second results has been satis?ed;

whereby since said plurality of logical comparison second results were generated in respect of said plurality of arithmetic comparison first results, said Boolean expression hit means that a logical rela— tionship amongst and between individual arithme tic comparisons of each of said plurality of ?elds of a record has been satis?ed.

2. An apparatus for comparing a ?rst record to a second record wherein said ?rst and second records have a plurality of ?elds comprising: '

an arithmetic comparator means for comparing each of said plurality of ?elds of said ?rst record to each corresponding one of said plurality of ?elds of said second record in order to produce a like plurality of arithmetic comparison results;

storing means for storing a plurality of user speci?ed expected results to said arithmetic comparator comparing of each of said plurality of ?elds of said ?rst record to said each corresponding one of said plurality of ?elds of said second record;

logical comparator means, respectively coupled to said arithmetic comparator means for receiving said plurality of arithmetic comparison results and to said storing means for receiving said user speci ?ed expected results, for comparing said plurality of arithmetic comparison results from said arithme tic comparator to said plurality of user speci?ed

4,384,325 15 16

expected results from said storing means wherein said true and false results output of said logical the output of said logical comparator means is true comparator means. for each one of said plurality of ?elds if one said 3. An apparatus according to claim 2 further compris plurality of arithmetic comparison results is the ing: same as a corresponding one of said plurality of t 5 ?eld format register means for de?ning length and said user speci?ed expected results and wherein the position within said ?rst record of each of said output of said logical comparator means is false for plurality of ?elds; each one of said plurality of ?elds if one said plural- and wherein said arithmetic comparator means further ity of arithmetic comparison results is not the same m comprise: . as a corresponding one of said plurality of said user arithmetic comparator means responsively coupled speci?ed expected results; and to said ?eld format register means for receiving

Boolean ‘evaluator means, respectively coupled to therefrom Said length and_sa1d P°5_m°" wlthm 531d said logical comparator means for receiving the ?rst record of each of said plurality of ?elds, and

for locating said each of said plurality of ?elds of said ?rst record in accordance with said length and said position.

4. Apparatus according to claim 2 or 3 wherein said storing means further comprises:

a ?eld comparison register. # i 1' l it

true and the false results thereof, for determining 15 said ?rst record to be a hit if a user supplied Bool ean expression is satis?ed by said true and false results output of said logical comparator means and for determining said ?rst record to be a miss if said user supplied Boolean expression is not satis?ed by 20

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