LM709

Application Note 24 A Simplified Test Set for Op Amp Characterization

Literature Number: SNOA637

A Simplified Test Set forOp Amp Characterization

INTRODUCTION

The test set described in this paper allows complete quanti-tative characterization of all dc operational amplifier param-eters quickly and with a minimum of additional equipment.The method used is accurate and is equally suitable for labo-ratory or production test — for quantitative readout or for limittesting. As embodied here, the test set is conditioned fortesting the LM709 and LM101 amplifiers; however, simplechanges discussed in the text will allow testing of any of thegenerally available operational amplifiers.

Amplifier parameters are tested over the full range of com-mon mode and power supply voltages with either of two out-put loads. Test set sensitivity and stability are adequate fortesting all presently available integrated amplifiers.

The paper will be divided into two sections, i.e., a functionaldescription, and a discussion of circuit operation. Completeconstruction information will be given including a layout forthe tester circuit boards.

FUNCTIONAL DESCRIPTION

The test set operates in one of three basic modes. Theseare: (1) Bias Current Test; (2) Offset Voltage, Offset CurrentTest; and (3) Transfer Function Test. In the first two of thesetests, the amplifier under test is exercised throughout its fullcommon mode range. In all three tests, power supply volt-ages for the circuit under test may be set at ±5V, ±10V,±15V, or ±20V.

POWER SUPPLY

Basic waveforms and dc operating voltages for the test setare derived from a power supply section comprising a posi-tive and a negative rectifier and filter, a test set voltage regu-lator, a test circuit voltage regulator, and a function genera-tor. The dc supplies will be discussed in the section dealingwith detailed circuit description.

The waveform generator provides three output functions, a±19V square wave, a −19V to +19V pulse with a 1% dutycycle, and a ±5V triangular wave. The square wave is thebasic waveform from which both the pulse and triangularwave outputs are derived.

The square wave generator is an operational amplifier con-nected as an astable multivibrator. This amplifier provides anoutput of approximately ±19V at 16 Hz. This square wave isused to drive junction FET switches in the test set and togenerate the pulse and triangular waveforms.

The pulse generator is a monostable multivibrator driven bythe output of the square wave generator. This multivibrator isallowed to swing from negative saturation to positive satura-tion on the positive going edge of the square wave input andhas a time constant which will provide a duty cycle of ap-proximately 1%. The output is approximately −19V to +19V.

The triangular wave generator is a dc stabilized integratordriven by the output of the square wave generator and pro-vides a ±5V output at the square wave frequency, invertedwith respect to the square wave.

The purpose of these various outputs from the power supplysection will be discussed in the functional description.

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FIGURE 1. Functional Diagram of Bias Current Test Circuit

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BIAS CURRENT TEST

A functional diagram of the bias current test circuit is shownin Figure 1. The output of the triangular wave generator andthe output of the test circuit, respectively, drive the horizontaland vertical deflection of an oscilloscope.

The device under test, (cascaded with the integrator, A7), isconnected in a differential amplifier configuration by R1, R2,R3, and R4. The inputs of this differential amplifier are drivenin common from the output of the triangular wave generatorthrough attenuator R8 and amplifier A8. The inputs of the de-vice under test are connected to the feedback networkthrough resistors R5 and R6, shunted by the switch S5a andS5b.

The feedback network provides a closed loop gain of 1,000and the integrator time constant serves to reduce noise atthe output of the test circuit as well as allowing the output ofthe device under test to remain near zero volts.

The bias current test is accomplished by allowing the deviceunder test to draw input current to one of its inputs throughthe corresponding input resistor on positive going or nega-tive going halves of the triangular wave generator output.This is accomplished by closing S5a or S5b on alternatehalves of the triangular wave input. The voltage appearingacross the input resistor is equal to input current times the in-put resistor. This voltage is multiplied by 1,000 by the feed-back loop and appears at the integrator output and the ver-tical input of the oscilloscope. The vertical separaton of thetraces representing the two input currents of the amplifier un-der test is equivalent to the total bias current of the amplifierunder test.

The bias current over the entire common mode range maybe examined by setting the output of A8 equal to the amplifiercommon mode range. A photograph of the bias current oscil-loscope display is given as Figure 2. In this figure, the totalinput current of an amplifier is displayed over a ±10V com-mon mode range with a sensitivity of 100 nA per verticaldivision.

The bias current display of Figure 2 has the added advan-tage that incipient breakdown of the input stage of the deviceunder test at the extremes of the common mode range iseasily detected.

If either or both the upper or lower trace in the bias currentdisplay exhibits curvature near the horizontal ends of the os-cilloscope face, then the bias current of that input of the am-plifier is shown to be dependent on common mode voltage.The usual causes of this dependency are low breakdownvoltage of the differential input stage or current sink.

OFFSET VOLTAGE, OFFSET CURRENT TEST

The offset voltage and offset current tests are performed inthe same general way as the bias current test. The only dif-ference is that the switches S5a and S5b are closed on thesame half-cycle of the triangular wave input.

The synchronous operation of S5a and S5b forces the ampli-fier under test to draw its input currents through matchedhigh and low input resistors on alternate halves of the inputtriangular wave. The difference between the voltage dropacross the two values of input resistors is proportional to thedifference in input current to the two inputs of the amplifierunder test and may be measured as the vertical spacing be-tween the two traces appearing on the face of the oscillo-scope.

Offset voltage is measured as the vertical spacing betweenthe trace corresponding to one of the two values of sourceresistance and the zero volt baseline. Switch S6 and Resis-tor R9 are a base line chopper whose purpose is to providea baseline reference which is independent of test set and os-cilloscope drift. S6 is driven from the pulse output of the func-tion generator and has a duty cycle of approximately 1% ofthe triangular wave.

Figure 3 is a photograph of the various waveforms presentedduring this test. Offset voltage and offset current are dis-played at a sensitivity of 1 mV and 100 nA per division, re-spectively, and both parameters are displayed over a com-mon mode range of ±10V.

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FIGURE 2. Bias Current and CommonMode Rejection Display

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FIGURE 3. Offset Voltage, Offset Currentand Common Mode Rejection Display

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TRANSFER FUNCTION TEST

A functional diagram of the transfer function test is shown inFigure 4. The output of the triangular wave generator and theoutput of the circuit under test, respectively, drive the hori-zontal and vertical inputs of an oscilloscope.

The device under test is driven by a ±2.5 mV triangular wavederived from the ±5V output of the triangular wave generatorthrough the attenuators R11, R12, and R1, R3 and through thevoltage follower, A7. The output of the device under test isfed to the vertical input of an oscilloscope.

Amplifier A7 performs a dual function in this test. When S7 isclosed during the bias current test, a voltage is developedacross C1 equal to the amplifier offset voltage multiplied bythe gain of the feedback loop. When S7 is opened in thetransfer function test, the charge stored in C1 continues toprovide this offset correction voltage. In addition, A7 sumsthe triangular wave test signal with the offset correction volt-age and applies this sum to the input of the amplifier undertest through the attenuator R1, R3. This input sweeps the in-put of the amplifier under test ±2.5 mV around its offset volt-age.

Figure 5 is a photograph of the output of the test set duringthe transfer function test. This figure illustrates the functionof amplifier A7 in adjusting the dc input of the test device sothat its transfer function is displayed on the center of the os-cilloscope face.

The transfer function display is a plot of VIN vs VOUT for anamplifier. This display provides information about three am-plifier parameters: gain, gain linearity, and output swing.

Gain is displayed as the slope, ∆VOUT/∆VIN of the transferfunction. Gain linearity is indicated change in slope of theVOUT/VIN display as a function of output voltage. This displayis particularly useful in detecting crossover distortion in aClass B output stage. Output swing is measured as the ver-tical deflection of the transfer function at the horizontal ex-tremes of the display.

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FIGURE 4. Functional Diagram of Transfer Function Circuit

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FIGURE 5. Transfer Function Display

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DETAILED CIRCUIT DESCRIPTION

POWER SUPPLIES

As shown in Figure 6, which is a complete schematic of thepower supply and function generator, two power supplies areprovided in the test set. One supply provides a fixed ±20V topower the circuitry in the test set; the other provides ±5V to±20V to power the circuit under test.

The test set power supply regulator accepts +28V from thepositive rectifier and filter and provides +20V through the

LM100 positive regulator. Amplifier A1 is powered from thenegative rectifier and filter and operates as a unity gain in-verter whose input is +20V from the positive regulator, andwhose output is −20V.

The test circuit power supply is referenced to the +20V out-put of the positive regulator through the variable divider com-prising R7, R8, R9, R10, and R26. The output of this divider is+10V to +2.5V according to the position of S2a and is fed tothe non-inverting, gain-of-two amplifier, A2. A2 is poweredfrom +28V and provides +20V to +5V at its output. A3 is a

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NOTE: All resistor valves in ohms.All resistors 1⁄4W, 5% unless specified otherwise.

FIGURE 6. Power Supply and Function Generator

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unity gain inverter whose input is the output of A2 and whichis powered from −28V. The complementary outputs of ampli-fiers A2 and A3 provide dc power to the circuit under test.

LM101 amplifiers are used as A2 and A3 to allow operationfrom one ground referenced voltage each and to provideprotective current limiting for the device under test.

FUNCTION GENERATOR

The function generator provides three outputs, a ±19Vsquare wave, a −19V to +19V pulse having a 1% duty cycle,and a ±5V triangular wave. The square wave is the basicfunction from which the pulse and triangular wave are de-rived, the pulse is referenced to the leading edge of thesquare wave, and the triangular wave is the inverted and in-tegrated square wave.

Amplifier A4 is an astable multivibrator generating a squarewave from positive to negative saturation. The amplitude ofthis square wave is approximately ±19V. The square wavefrequency is determined by the ratio of R18 to R16 and by thetime constant, R17C9. The operating frequency is stabilizedagainst temperature and power regulation effects by regulat-ing the feedback signal with the divider R19, D5 and D6.

Amplifier A5 is a monostable multivibrator triggered by thepositive going output of A4. The pulse width of A5 is deter-mined by the ratio of R20 to R22 and by the time constantR21C10. The output pulse of A5 is an approximately 1% dutycycle pulse from approximately −19V to +19V.

Amplifier A6 is a dc stabilized integrator driven from theamplitude-regulated output of A4. Its output is a ±5V triangu-lar wave. The amplitude of the output of A6 is determined bythe square wave voltage developed across D5 and D6 andthe time constant Radj C14. DC stabilization is accomplishedby the feedback network R24, R25, and C15. The ac attenua-tion of this feedback network is high enough so that the inte-grator action at the square wave frequency is not degraded.

Operating frequency of the function generator may be variedby adjusting the time constants associated with A4, A5, andA6 in the same ratio.

TEST CIRCUIT

A complete schematic diagram of the test circuit is shown inFigure 7. The test circuit accepts the outputs of the powersupplies and function generator and provides horizontal andvertical outputs for an X-Y oscilloscope, which is used as themeasurement system.

The primary elements of the test circuit are the feedbackbuffer and integrator, comprising amplifier A7 and its feed-back network C16, R31, R32, and C17, and the differential am-plifier network, comprising the device under test and thefeedback network R40, R43, R44, and R52. The remainder ofthe test circuit provides the proper conditioning for the deviceunder test and scaling for the oscilloscope, on which the testresults are displayed.

The amplifier A8 provides a variable amplitude source ofcommon mode signal to exercise the amplifier under testover its common mode range. This amplifier is connected asa non-inverting gain-of-3.6 amplifier and receives its inputfrom the triangular wave generator. Potentiometer R37 al-lows the output of this amplifier to be varied from ±0 volts to±18 volts. The output of this amplifier drives the differentialinput resistors, R43 and R44, for the device under test.

The resistors R46 and R47 are current sensing resistorswhich sense the input current of the device under test. Theseresistors are switched into the circuit in the proper sequenceby the field effect transistors Q6 and Q7. Q6 and Q7 are

driven from the square wave output of the function generatorby the PNP pair, Q10 and Q11, and the NPN pair, Q8 and Q9.Switch sections S1b and S1c select the switching sequencefor Q8 and Q9 and hence for Q6 and Q7. In the bias currenttest, the FET drivers, Q8 and Q9, are switched by out ofphase signals from Q10 and Q11. This opens the FETswitches Q6 and Q7 on alternate half cycles of the squarewave output of the function generator. During the offset volt-age, offset current test, the FET drivers are operated syn-chronously from the output of Q11. During the transfer func-tion test, Q6 and Q7 are switched on continuously by turningoff Q11. R42 and R45 maintain the gates of the FET switchesat zero gate to source voltage for maximum conductanceduring their on cycle. Since the sources of these switchesare at the common mode input voltage of the device undertest, these resistors are connected to the output of the com-mon mode driver amplifier, A8.

The input for the integrator-feedback buffer, A7, is selectedby the FET switches Q4 and Q5. During the bias current andoffset voltage offset current tests, A7 is connected as an inte-grator and receives its input from the output of the device un-der test. The output of A7 drives the feedback resistor, R40.In this connection, the integrator holds the output of the de-vice under test near ground and serves to amplify the volt-ages corresponding to bias current, offset current, and offsetvoltage by a factor of 1,000 before presenting them to themeasurement system. FET switches Q4 and Q5 are turnedon by switch section S1b during these tests.

FET switches Q4 and Q5 are turned off during the transferfunction test. This disconnects A7 from the output of the de-vice under test and changes it from an integrator to anon-inverting unity gain amplifier driven from the triangularwave output of the function generator through the attenuatorR33 and R34 and switch section S1a. In this connection, am-plifier A7 serves two functions; first, to provide an offset volt-age correction to the input of the device under test and, sec-ond, to drive the input of the device under test with a ±2.5mV triangular wave centered about the offset voltage. Duringthis test, the common mode driver amplifier is disabled byswitch section S1a and the vertical input of the measurementoscilloscope is transferred from the output of theintegrator-buffer, A7, to the output of the device under test byswitch section S1d. S2a allows supply voltages for the deviceunder test to be set at ±5, ±10, ±15, or ±20V. S2b changesthe vertical scale factor for the measurement oscilloscope tomaintain optimum vertical deflection for the particular powersupply voltage used. S4 is a momentary contact pushbuttonswitch which is used to change the load on the device undertest from 10 kΩ to 2 kΩ.

A delay must be provided when switching from the inputtests to the transfer function tests. The purpose of this delayis to disable the integrator function of A7 before driving it withthe triangular wave. If this is not done, the offset correctionvoltage, stored on C16, will be lost. This delay between open-ing FET switch Q4, and switch Q5, is provided by the RC fil-ter, R35 and C19.

Resistor R41 and diodes D7 and D8 are provided to controlthe integrator when no test device is present, or when afaulty test device is inserted. R41 provides a dc feedbackpath in the absence of a test device and resets the integratorto zero. Diodes D7 and D8 clamp the input to the integrator toapproximately ±0.7 volts when a faulty device is inserted.

FET switch Q1 and resistor R28 provide a ground referenceat the beginning of the 50-ohm-source, offset-voltage trace.This trace provides a ground reference which is independentof instrument or oscilloscope calibration. The gate of Q1 is

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driven by the output of monostable multivibrator A5, andshorts the vertical oscilloscope drive signal to ground duringthe time that A5 output is positive.

Switch S3, R27, and R28 provide a 5X scale increase duringinput parameter tests to allow measurement of amplifierswith large offset voltage, offset current, or bias current.

Switch S5 allows amplifier compensation to be changed for101 or 709 type amplifiers.

CALIBRATION

Calibration of the test system is relatively simple and re-quires only two adjustments. First, the output of the mainregulator is set up for 20V. Then, the triangular wave genera-tor is adjusted to provide ±5V output by selecting Radj. Thissets the horizontal sweep for the X-Y oscilloscope used asthe measurement system. The oscilloscope is then set up for1V/division vertical and for a full 10 division horizontalsweep.

Scale factors for the three test positions are:

1. Bias Current Display (Figure 2)

Ibias total 100 nA/div. vertical

Common Mode Voltage Variable horizontal

2. Offset Voltage-Offset Current (Figure 3)

Ioffset 100 nA/div. vertical

Voffset 1 mV/div. vertical

Common Mode Voltage Variable horizontal

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Note: All resistors 1/4W, 5% unless specified otherwise *2N3819 matched for on resistance within 200Ω Select for BVGS > 45V

FIGURE 7. Test Circuit

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3. Transfer Function (Figure 5)

VIN 0.5 mV/div.

VOUT 5V/div. @ Vs ±20V

5V/div. @ Vs ±15V

2V/div. @ Vs ±10V

1V/div. @ Vs ±5V

CONSTRUCTION

Test set construction is simplified through the use of inte-grated circuits and etched circuit layout.

Figures 8, 9, 10 give photographs of the completed tester.Figure 11 shows the parts location for the components onthe circuit board layout of Figure 12. An attempt should bemade to adhere to this layout to insure that parasitic couplingbetween elements will not cause oscillations or give calibra-tion problems.

Table 1 is a listing of special components which are neededto fit the physical layout given for the tester.

TABLE 1. Partial Parts List

T1 Triad F-90X

S1 Centralab PA2003 non-shorting

S2 Centralab PA2015 non-shorting

S3, S4 Grayhill 30-1 Series 30 subminiaturepushbutton switch

S5, S6 Alcoswitch MST-105D SPDT

CONCLUSIONS

A semi-automatic test system has been described which willcompletely test the important operational amplifier param-eters over the full power supply and common mode ranges.The system is simple, inexpensive, easily calibrated, and isequally suitable for engineering or quality assurance usage.

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FIGURE 8. Bottom of Test Set

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FIGURE 9. Front Panel

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FIGURE 10. Jacks

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FIGURE 11. Component Location, Top View

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FIGURE 12. Circuit Board Layout

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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