application note an-1005 - international rectifier

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Application Note AN-1005

ww.irf.com 1AN-1005

Power MOSFET AvalancheDesign Guidelines

By Tim McDonald, Marco Soldano, Anthony Murray, Teodor Avram

Table of Contents

PageTable of Figures ...................................................................................3

Introduction ..........................................................................................4

Overview ...................................................................................4

Avalanche Mode Defined ..........................................................4

Avalanche Occurrences in Industry Applications.......................4

Flyback Converter Example............................................4

Automotive Fuel Injector Coil Example ...........................5

Avalanche Failure Mode............................................................5

Power MOSFET Device Physics ....................................5

Rugged MOSFETs .........................................................6

Avalanche Testing Details .........................................................8

Single Pulse Unclamped Inductive Switching .................8

Decoupled VDD Voltage Source.....................................9

Table of Contents continued on next page…

www.irf.com 2AN-1005

Avalanche Rating ......................................................................10

EAS Thermal Limit Approach ...........................................10

Single Pulse Example ..........................................10

Repetitive Pulse ...................................................12

Statistical Approach ........................................................15

Buyer Beware............................................................................16

Conclusion.................................................................................16

The purpose of this note is to better understand and utilize IR HEXFETTM Power MOSFETs, it isimportant to explore the theory behind avalanche breakdown and to understand the design andrating of rugged MOSFETs. Several different avalanche ratings are explained and theirusefulness and limitations in design is considered.


Table of Figures

Figure 1 Flyback Converter Circuit 4Figure 2 Flyback Converter Switch Under Avalanche Waveform 4Figure 3 Flyback Converter Switch Under Avalanche Waveform (Detail) 4Figure 4 Automotive Injector Coil Circuit 5Figure 5 Automotive Injection Coil in Avalanche Waveforms 5Figure 6 Power MOSFET Cross Section 5Figure 7 Power MOSFET Circuit Model 5Figure 8 Power MOSFET Cross Section Under Avalanche 6Figure 9 Basic HEXFET Structure 6Figure 10 Power MOSFET Random Device Failure Spots 7Figure 11 Good Source Contact vs. Bad Contact Illustration 7Figure 12 IA at Failure vs. Test Temperature 8Figure 13 Single Pulse Unclamped Inductive Switching Test Circuit 8Figure 14 Single Pulse Unclamped Inductive Switching Test Circuit Output Waveforms 9Figure 15 Decoupled VDD Voltage Source Test Circuit Model 9Figure 16 Decoupled VDD Voltage Source Test Circuit Waveforms 9Figure 17 Typical Simulated Avalanche Waveforms 10Figure 18 IRFP450 (500V Rated) Device Avalanche Waveforms 10Figure 19 IRFP32N50K Data Sheet Excerptions 11Figure 20 Transient Thermal Impedance Plot, Junction to Case 11Figure 21 Maximum Avalanche Energy vs. Temperature for Various Drain Currents 12Figure 22 IRF7484 EAR vs. TSTART for Various Duty Cycles, Single ID 13Figure 23 IRF7484 Typical Avalanche Current vs. Pulsewidth for Various Duty Cycles 13Figure 24 IRF7484 Data Sheet Excerptions 14Figure 25 IRF7484 Typical Effective Transient Thermal Impedance, Junction-to-Ambient 15Figure 26 Avalanche Current vs. Time for Various Inductor Values 15Figure 27 Failure Energy Distribution 15


INTRODUCTION

Overview

International Rectifier has provided rugged PowerMOSFET semiconductor devices for almost 20years. To better understand and utilize IRHEXFET

TMPower MOSFETs, it is important to

explore the theory behind avalanche breakdown andto understand the design and rating of ruggedMOSFETs. Several different avalanche ratings areexplained and their usefulness and limitations indesign is considered.

Avalanche Mode Defined

All semiconductor devices are rated for a certainmax reverse voltage (BVDSS for Power MOSFETs).Operation above this threshold will cause highelectric fields in reversed biased p-n junctions. Dueto impact ionization, the high electric fields createelectron-hole pairs that undergo a multiplicationeffect leading to increased current. The reversecurrent flow through the device causes high powerdissipation, associated temperature rise, andpotential device destruction.

Avalanche Occurrences In IndustryApplications

Flyback Converter Example

Some designers do not allow for avalancheoperation; instead, a voltage derating is maintainedbetween rated BVDSS and VDD (typically 90% or less).In such instances, however, it is not uncommon thatgreater than planned for voltage spikes can occur,so even the best designs may encounter aninfrequent avalanche event. One such example, aflyback converter, is shown in Figures 1-3.

During MOSFET operation of the Flyback Converter,energy is stored in the leakage inductor. If theinductor is not properly clamped, during MOSFETturnoff the leakage inductance discharges throughthe primary switch and may cause avalancheoperation as shown in the VDS, ID, and VGS versustime waveforms in Figures 2 and 3.

Note: Red (VDS), Blue (ID), Black (VGS)

In this application, built in avalanche capability is anadditional Power MOSFET feature and safeguardsagainst unexpected voltage over-stresses that mayoccur at the limits of circuit operation.


Automotive Fuel Injector Coil Example

Other applications, such as automotive fuel injection,are designed to experience avalanche. See theexample Injector Coil circuit below.

During switch operation, energy is stored in thesolenoid inductance. Following switch turnoff, theinductor discharges on the primary switch causingavalanche operation as simulated in Figure 5.

In this application, avalanche tested and rateddevices are a necessity for reliable circuit operation.

AVALANCHE FAILURE MODE

Some power semiconductor devices are designed towithstand a certain amount of avalanche current fora limited time and can, therefore, be avalancherated. Others will fail very quickly after the onset ofavalanche. The difference in performance stems

from particular device physics, design, andmanufacturing.

Power MOSFET Device Physics

All semiconductor devices contain parasiticcomponents intrinsic to the physical design of thedevice. In Power MOSFETs, these componentsinclude capacitors due to displaced charge in thejunction between p and n regions, resistorsassociated with material resistivity, a body diodeformed where the p+ body diffusion is made into then- epi-layer, and an NPN (bi-polar junction transistorhenceforth called BJT) sequence (BJT) formedwhere the n+ source contact is diffused. See Figure6 for Power MOSFET cross section that incorporatesthe parasitic components listed above and Figure 7for a complete circuit model of the device.


In avalanche, the p-n junction acting as a diode nolonger blocks voltage. With higher applied voltage acritical field is reached where impact ionization tendsto infinity and carrier concentration increases due toavalanche multiplication. Due to the radial fieldcomponent, the electric field inside the device ismost intense at the point where the junction bends.This strong electric field causes maximum currentflow in close proximity to the parasitic BJT, asdepicted in Figure 8 below. The power dissipationincreases temperature, thus increasing RB, sincesilicon resistivity increases with temperature. FromOhm’s Law we know that increasing resistance atconstant current creates an increasing voltage dropacross the resistor. When the voltage drop issufficient to forward bias the parasitic BJT, it will turnon with potentially catastrophic results, as control ofthe switch is lost.

Typical modern Power MOSFETs have millions ofidentical trenches, cells or many strips in parallel toform one device, as shown in Figure 9. For Robustdesigns, then, avalanche current must be sharedamong many cells/strips evenly. Failure will thenoccur randomly in a single cell, at a hightemperature. In weak designs, the voltage requiredto reach breakdown electric field is lower for onedevice region (group of cells) than for others, socritical temperature will be reached more easilycausing the device to fail in one specific area.

Rugged MOSFETs

First introduced in the middle 1980’s, AvalancheRugged MOSFETs are designed to avoid turning onthe parasitic BJT until very high temperature and/orvery high avalanche current occur. This is achievedby:

Reducing the p+ region resistance withhigher doping diffusion

Optimizing cell/line layout to minimize the“length” of RB

The net effect is a reduction of RB, and thus thevoltage drop necessary to forward bias the parasiticBJT will occur at higher current and temperature.Avalanche Rugged MOSFETs are designed tocontain no single consistently weak spot, soavalanche occurs uniformly across the devicesurface until failure occurs randomly in the activearea. Utilizing the parallel design of cells, avalanchecurrent is shared among many cells and failure willoccur at higher current than for designs with a singleweak spot. A Power MOSFET which is welldesigned for ruggedness will only fail when thetemperature substantially exceeds rated TJMAX.


An analysis of various IR devices tested todestruction indicates that failure spots occurrandomly in the active area. Some samples areshown in the Figure 10:

The risk of manufacturing process or fabricationinduced “weak cell” parts is always present. TheSEM cross-section micrograph on the top shows onesuch example. The Source metal contacts the n+layer at the near surface, but not the p+ layer. As aresult the BJT base is floating and easily triggerable.An example of a good contact is shown on thebottom. The source metal contacts and shorts the n+layer to the p+ layer thus suppressing the parasiticBJT operation.

Parts with weak cells such as are shown on the topof Figure 11 can be removed from the population by100% avalanche (EAS) stress testing duringproduction.

Through over 20 years of experience, InternationalRectifier has evolved design and manufacturingdisciplines to validate power MOSFET designruggedness of “EAS rated” devices. Presently IR usesa “three legged” approach during design:

1.) Statistically significant samples of prospectivedesigns are tested to failure at test conditionschosen to reach extremes in temperature andcurrent stress. Representative parts from DOEelements are tested to assure uniform avalanchefailure across expected variation of critical processsteps.


2.) Each design is tested to failure acrossTemperature and Inductor (time in avalanche) toassure that failure extrapolates to zero at atemperature well in excess of TJMAX. (See sampleFigure 12 of “IAS at failure vs. Tstart” below.)

3.) A sample of Final design parts are stressed withrepetitive avalanche pulses of such a value to raisejunction temperature to TJMAX.

This “three legged” solution helps assure thatdesigns are rugged and can be avalanche rated. Tosummarize then: International Rectifier utilizes thefollowing factors to provide rugged avalancheMOSFETs:

Improved Device Design:o to mute the parasitic BJT by

reducing RB

o to eliminate the effect of weakercells in particular positions of the

AVALANCHE TESTING DETAILSInternational Rectifier performs avalanche stresstesting on its power semiconductor devices toassure conformance of new designs with avalancherating, to validate parts for ruggedness, and toscreen production for weak devices.

Single Pulse Unclamped InductiveSwitching

During the mid 1980’s, IR initially used the singlepulse unclamped inductive switching test circuit foravalanche testing that is shown below in Figures 13and 14. This circuit is still referenced in older“legacy” product datasheets.

layout (i.e., cells along devicetermination, gate bussing, etc.)

Improved Manufacturing Process:o to guarantee more uniform cellso to reduce incomplete or malformed

cell occurrences Improved Device Characterization:

o to assure devices fail uniformlyacross wide range of ID,Temperature

o To assure device fails at very high(extrapolated) temperature

o To assure device is capable ofsurviving multiple avalanche cyclesat the thermal limit

100% Avalanche Stress Testing


From the Figure 13 schematic we can calculate thesingle pulse avalanche energy (EAS) as:

DDDS

DSASAS

VV

VILE

2

2

(1)

The measured energy values depend on theavalanche breakdown voltage, which tends to varyduring the discharge period due to the temperatureincrease. Also note that for low voltage devicesVDSS-VDD may become quite small, limiting theuse of this circuit since it introduces high-test error.

Decoupled VDD Voltage Source

To surpass the limitations of the Single PulseUnclamped Inductive Switching test circuit,International Rectifier started using the DecoupledVDD Voltage Source illustrated in Figures 15 and 16since the mid to late 1980’s.

Here a driver FET and recirculation diode are addedso that the voltage drop across the inductor duringavalanche is equal to the avalanche voltage. Withthis circuit (neglecting the angular ESR in theinductor) the energy can be simply calculated as:

2

2

1ASAS ILE (2)

A better and more accurate reading of the avalancheenergy can be obtained by measuring instantaneousvoltage and current in the device and integrating asdescribed in the following equation:

dttitE AS

t

tDSSAVAS )()(

2

1)( (3)

For further reference, Figures 17 and 18, depictideal and actual avalanche waveforms, respectively.


AVALANCHE RATINGGenerally, there are three approaches to avalancherating devices:

1. Thermal Limit Approach: The device israted to the value(s) of energy, EAS, thatcauses an increase in junction temperatureup to TJMAX. International Rectifier EAS

avalanche rated MOSFETs are rated in thismanner.

2. Statistical Approach: Devices are tested upto the failure point. The rating is given usingstatistical tools (e.g., Average (EAS) – 6σ) applied to the failure distribution. Some IRparts are rated this way and indicated asEAS(tested), generally in addition to thethermally limited rating. However, someMOSFET suppliers provide only this ratingon their datasheets.

3. No rating at all.

While the first two approaches provide a value foravalanche energy, the designer must take care toknow the important differences that are outlinedbelow.

EAS THERMAL LIMIT APPROACH

Single Pulse

The single pulse avalanche rating (EAS) is based onthe assumption that the device is rugged enough tosustain avalanche operation under a wide set ofconditions subjection only to not exceeding themaximum allowed junction temperature. Typically,the avalanche rating on the data sheet is the valueof the energy that increases the junctiontemperature from 25º C to TJMAX, assuming aconstant case temperature of 25º C and assuming aspecified value of ID (usually set at 60% of ID (25º C).


For example, consider the International Rectifier 500V 32 A device as excerpted from the datasheet below,

with the following initial conditions:

Single Pulse Avalanche Current:IAS = ID = 32 A

Starting Temperature:TSTART =25º C

Inductor Value: L = 0.87 mH

To calculate the temperature increase due to theavalanche power dissipation we utilize a thermalmodel with Ohm’s Law equivalence. The resultingequation follows:

AVTH PZT (4)

The average power dissipated during avalanche canbe calculated as

kWAVt

tIVP

av

avASAVAV 10326505.0

2

1

(5)

Avalanche voltage can be estimated as

VVBVV DSSAV 6505003.13.1 (6)

Now from Equation 2 we can calculate

mJmHILE ASAS 4453287.05.02

1 22

which agrees with the datasheet value withinrounding of the least significant digit.

The duration of the avalanche power pulse can becalculated, assuming the inductor is discharging witha constant voltage applied to it, as

sV

AmH

V

ILt

AV

pk

av 43650

3287.0 (7)

The thermal impedance (ZTH) for this pulsewidthcan be read from the Transient Thermal ImpedancePlot provided with the datasheet, as shown in Figure20.


The temperature increase due to avalanche and thefinal junction temperature can therefore becalculated using Equation 4

CkWPZT AVGTH 12010012.0

CTCTTT JMAXstartJ 150145 (8)

showing that the datasheet rating the calculatedTJMAX within minor reading ZTH from Figure 20.

Figure 21 is included in datasheets for EAS ratedparts and shows many values of EAS for varyingstarting TJ and ID. Each point along the curvesshown represents the energy necessary to raise thetemperature to TJMAX.

Note that this curve belies the myth of trying tocompare datasheet table EAS values : by varyingcurrent and/or temperature the EAS value can varyby a range of 800x! Specifying EAS at lower ID

values results in higher EAS even though the devicestress (TJ) is the same.

Repetitive Pulse

Historically, International Rectifier has rated therepetitive pulse avalanche energy (EAR) at 1/10000of PD (25°C). This practice is now supplanted onnewer products by an explicit rating of avalancheoperation up to the TJMAX condition.

Datasheets utilizing this newer rating also include:

EAS: the single pulse rating ZTH graph: ZTH vs. Time for various duty

cycles (example in Figure 20 preceded bydiscussion)

EAS graph: EAS vs. Tstart for various ID(example in Figure 21 followed bydiscussion)

EAR graph: EAR vs. Tstart for various dutycycles, single ID (example and discussion tofollows)

IAR graph: Typical Avalanche Current vs.Pulsewidth for various duty cycles (exampleand discussion to follow below).

The EAR graph shows the avalanche energynecessary to raise the junction temperature from thestarting temperature to TJMAX for various duty cycles,at a given current. A sample EAR graph is given inFigure 22. The top curve represents single pulsebehavior at 125A, while the bottom curve representsrepetitive pulse operation at 125A, 10% duty cycle.In repetitive pulse operation, the junctiontemperature does not have sufficient time betweenpulses to return to the ambient level. The larger theduty cycle, the higher the junction temperature willbe when the next pulse arrives. Therefore, withincreasing duty cycle, the avalanche energy requiredto raise the junction temperature to TJMAX will belower.


The IAR graph (see Figure 23) shows how theavalanche current varies with the avalanchepulsewidth for various duty cycles, with a “budgeted”increase in junction temperature due to avalanchelosses assumed at (∆T) = 25°C. An effect similar to that in the EAR graph occurs. In repetitive pulseoperation, the junction temperature does not havesufficient time to decrease to the ambienttemperature between pulses. As a result, thestarting temperature for subsequent pulses will behigher than the ambient temperature. Therefore, asmaller amount of avalanche energy,

corresponding to smaller avalanche current, willraise the junction temperature to TJMAX forsubsequent pulses. So for increasing duty cycles,the avalanche current required to raise the junctiontemperature by 25°C will decrease.

A detailed specific example now follows to illustratehow to design for repetitive avalanche operation.This example will utilize the Automotive FuelInjection Coil circuit, shown earlier in Figure 4, withthe 40V 14A IRF7484 MOSFET (Figure 24).


Data on IRF7484 is excerpted from the datasheet below:

The initial conditions are:

Ambient Temperature: Ta = 120°C Solenoid Inductance: L = 5mH Solenoid Resistance: RL = 15Ω Pulse Frequency: f = 125Hz Supply Voltage: VDD= 14.5V

By applying Kirchoff’s Laws to the Fuel InjectionCoilcircuit we find

AVLDD VtiRdi

tdiLV )(

)((9)

Using boundary condition at t = 0, i(t) = IL = IAR,yieldsthe general solution in the time domain:

1)(t

L

R

L

DDAVt

L

R

AR

LL

eR

VVeIti (10)

Solving for the avalanche pulsewidth (tav) assumingi(tav) = 0 gives

sVV

AmH

VV

RI

R

Lt

DDAV

LAR

L

av 1095.1452

15966.01ln

15

51ln

(11)since avalanche voltage can be obtained frommeasurement (best), or estimated from the IRF7484datasheet using Equation 6 as

VVBVV DSSAV 52403.13.1 ,

and avalanche current can be calculated as

Am

V

RR

VII

onDSL

DDARL 966.0

1015

5.14

)(

(12)

Repetitive avalanche energy can be calculated as

mJsVAtVI

E avAVARAR 74.2

2

10952966.0

2

(13)

Average avalanche, and conduction power valuescan be calculated as

Ws

mJ

t

EP

av

ARAV 1.25

109

74.2

, (14)

mWHzmJfEP ARave 34312574.2 (15)

WmADRIP onDSLcond 121013.010)966.0( 2)(

2 (16)

since the avalanche duty cycle can be calculated as

013.0125109 HzsftD av (17)

The average junction temperature can be calculatedas

CCWCWmWTRPPT acondaveSS 2.13712050)121343()(

(18)The peak rise in junction temperature due to eachavalanche pulse is given by

CWCWZPT THAV 5.418.01.25 (19)

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where the thermal impedance (ZTH) is approximatedfrom the Transient Thermal Impedance Plot providedwith the datasheet, as shown in Figure 25.

Note that TSS+∆T = 137.2+17.1 =154.3ºC <TJMAX

STATISTICAL APPROACH

In this case, a sample of devices is tested for failurewithout limiting the maximum junction temperature toTJMAX. The test consists of increasing the inductancevalue under a defined IAS until each device fails. Asshown in Figure 26, the energy, defined as the areaunder the IAS curve, increases linearly with the loadinductance value. Fixing L and increasing IAS untilfailure occurs can accomplish a similar effect. Thefailure energy of each device is recorded and plotted

so that a failure distribution and EAS value can befound, as shown below in Figure 27.

Note that the statistically determined EAS valuecannot be used to design for actual avalancheconditions. It represents operation at a single set ofconditions that cannot be extrapolated to othercircumstances without providing more information.Additionally, the conditions at which statistically ratedEAS values are given most often are outside thenormal operation limits at which a part is qualified.

IR provides statistically based EAS mostly inconjunction with the Thermally Limited values and toidentify the product screening test numerical value.Other suppliers sometimes provide only a statisticallybased value.

0.18

109µs

.com 15AN-1005


BUYER BEWARE

Many suppliers rate power MOSFET avalanchecapability with only a single number in the datasheetand without providing full circuit or test conditiondetails. In such cases, buyer beware! It is notsufficient to merely compare the numeric values ofavalanche energy which appear in datasheet

tables. The following example will help illustrate onesuch pitfall.

Since avalanche energy depends on the inductorvalue and starting current, it is possible to have twopulses with the same energy but different shapeprovide two different junction temperatures. Thisphenomenon is illustrated in the following examples:

Example 1Pulse:

IAS = 32AL = 0.87mH

Result:

max

)(

2

145

120

/012.0

43

4452

1

JJ

TH

DSSAV

pk

av

ASAS

TCT

CT

WCZ

sV

ILt

mJILE

Example 2Pulse:

IAS = 16AL = 3.48mH

Result:

max

)(

2

129

104

/02.0

86

4452

1

JJ

TH

DSSAV

pk

av

ASAS

TCT

CT

WCZ

sV

ILt

mJILE

Examples 1 and 2 both have the same energy,however, since the inductor varies, so does thejunction temperature. While both junctiontemperatures are within the TJMAX, they are notequal.

Note as well that IR power MOSFETs which are“EAS” rated include graphs showing constantjunction temperature energy values. See forexample Figure 22, top curve. Which value ofenergy should be compared with anothersupplier’s power MOSFET?

Another common industry practice is to rateavalanche capability based on curves showingallowable time in avalanche as a trade-off withdrain current. At best, such curves are backedup with test to failure data as seen in Figure 12.However, sometimes these curves are based onstatistically determined limits without apparentregard for junction temperature. The result isthat a thermal TJ calculation (see examples 1 &2) for the rated allowed condition may show thatTJ exceeds TJMAX, without reliability qualificationdata at this higher than TJMAX condition. Again,buyer beware.

CONCLUSION

With over 20 years of evolving experience,International Rectifier designs, characterizes,and rates Power MOSFETs to assure ruggedand reliable operation while in avalanche. IRapplies 3 different classes of avalanche rating:

- The Thermal Approach allows single pulse and(where indicated) repetitive pulse avalancheoperation as long as neither IDMAX nor ratedTJMAX are exceeded. Energy losses due toavalanche operation can be analyzed as anyother source of power dissipation. Suchthermally rated parts are indicated by IR with arating of “EAS” and, more recently, with inclusionof repetitive avalanche SOA graph 9 (forexample see Figures 22 & 23).

- Statistically based avalanche ratings are set

based on sample failure statistics. At IR thisrating is labeled “EAS (tested)” and correspondsto a production test screening limit. While theStatistical Approach generally gives higherenergy value, it does not provide a practicalmethod for evaluating avalanche capability in


conditions that differ from the datasheet. Sincecircuit designers’ conditions usually differsignificantly, the Statistical Approach does notgive a clear idea on how to design foroccurrence of avalanche.

-Some legacy products were designed by IRwithout an avalanche rating. Devices without anavalanche rating on the datasheet should not beused In circuits which will see avalanchecondition during any mode of operation. Byspecial arrangement, most such designs can beavalanche guaranteed; contact factoryrepresentative for further information.

Power MOSFET users should take care tounderstand differences in avalanche ratingconditions between various suppliers. Devicesthat are not “avalanche Robust” can causeunexpected and seemingly unexplained circuitfailure. Some manufacturers do not rate theirMOSFETs for avalanche at all. Others use astatistical rating alone which does not offer thesame assurance for robust operation providedby a more complete characterization and ratingsuch as IR uses for “EAS rated” devices. In thisregard, “the devil is in the details”; merelycontrasting values of avalanche energy thatappear in datasheets tables is not an accuratemetric of device ruggedness.

application note an-1005 - international rectifier

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