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Stability in High Speed LDO Regulators An overview of the design relating to low drop out (LDO) regulators.

Design guidelines given for the selection of components based on performance and stability requirements.

Typical questions that generally need or get asked:

What are my input and output requirements?

Do I have transient response and magnitude requirements?

Can I use a regulator or do I need a controller?

What do I need for output capacitors?

If my regulator is oscillating, what do I change to stop it?

My regulator response is slow, so how do I speed it up without causing it to oscillate?

The following slides introduce the different componentsand block diagrams for LDO regulators.

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Block diagram showing dual LDO controller.

Startup, Over current, and Shutdown functions.

Band Gap reference for setting DC output voltage.

Error Amplifier for controlling external N-channel FET.

Second channel FET turn on for shorting input to output.

Example LDO Controller Block Diagram

MC33567 Dual LDO Controller

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LDO Regulator Block Diagram

Error Amplifier

Feedback Divider

Output Driver & Load

A(s)-

+Reference Input Supply

Output

Driver

Load

B(s)

C(s)

RV

1V

OV2V

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LDO Regulator Schematic

FeedbackDivider

Driver

OutputCapacitor

Load

Error Amp

Reference Input

OV

RV

2V

Circuit1

Project 1

tod

AJun 10, 2000

0001 1.0

1 1

Title:

Designed by:

Checked by:

Approved by:

SizeDate

Document N Revision

Sheet of

3 4 5 6 7 8

B

C

D

E

F

G

U1

Vref

Ro Q1

VCC

Co

Rs

R1

R2

CbCaRl

1V

LDO Controller

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Simplified Block Diagram and Transfer Function

D(s)N(s)

A

C(s)B(s)A(s)1

1

1C(s)1

VV

H(s) VR

O

AC

DC

or 1R2R1

1C(s)1

AV

A(s) B(s)

C(s)

+

-

RO VH(s)V 1V

2V

RV

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Error Amplifier Detail - A(s)

1ωoω - dominant error amp pole

- secondary error amp pole

oA - error amp open loop gain

aω

1ωs

1sω

1ωs1ω

sA

A(s)1

a

1o

o

- error amp gain bandwidth

Open loop gain greater than 60dB (for less than 0.1% DC output error).

Dominant pole usually set for device, although some devices allow adjusting via compensation pin.

Gain bandwidth usually specified:

Solve for gain bandwidth pole:

Error amp designed to have secondary pole greater than gain bandwidth and usually NOT specified. If not, let:

For stability analysis, assume frequency range:

ooa fA2πω

oo fA

a1 ωω

1o ωωω

Error Amplifier

A(s)-

+

RV

1V

2V)V-(VA(s)V 2R1

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Feedback Divider Detail - C(s)

Tba

VRTaO1b

V

2

RCCs1AVRsCVRsC1

A1

V

baT RRR 2

1V

RR

1A

Want to design divider for DC gain of Av and AC gain of 1.

Want V1 independent on reference input, Vr.

Need AC gain of 1 for frequencies greater than low frequency pole of error amp.

LDO controller with fixed output voltage has divider built-in and optimized.

If adding to existing internal divider, follow same guidelines.

Use following design guidelines to obtain these result.

Circuit1

Project 1

tod

AJun 11, 2000

0001 1.0

1 1

Title:

Designed by:

Checked by:

Approved by:

SizeDate

Document N Revision

Sheet of

3 4 5 6 7 8

C

D

E

F

G

R1

Cb

Ca R2

OV2V

RV

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Feedback Divider Detail - C(s) - Continued

Divider Design Guidelines:

aa

V1

C10ωA

R 1AR

RV

12

2ab

Rω100

C DCR

OV

VV

A

1R

VA

aC

OVRV

bC2R

aω

- output voltage (known).- reference voltage (known).- DC gain (solve for).- gain bandwidth (from error amp analysis).- error amp input capacitance (use 10pf if not specified).- first divider resistor (solve for).- second divider resistor (solve for).- divider compensation capacitor (solve for).

Final solution for divider transfer function - C(s):

O2 VC(s)V )()( ACDC 1A1

C(s)V

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Circuit1

Project 1

tod

AJun 11, 2000

0001 1.0

1 1

Designed by:

Checked by:

Approved by:

SizeDate

Document N Revision

Sheet of

6 7 8

C

D

E

F

G

gm

Cgd

Cgs

Rl

Rs

Co

VCC

Ro

Output Driver and Load Detail - B(s)

1V

OV

OutputCapacitor

Load

Driver

Error AmpOutput

1ωβ

Rg1

1ω1

sRg

1β

ωω1

s

1ωs

B(s)

fsmcsmfc

2

c

1O VB(s)V

osc

CR1

ω

oi

fRC

1ω

gdgsi CCC gdgs

gd

CCC

β

Transfer function for B(s) shown mainly for

reference.

Too complicated to deal with directly.

Will develop design guidelines combining

this with other functions to develop overall

closed loop transfer function.

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1ω1

ω1

sωβ

Rg1

1ω1

ωs

ωωs

Rg1

βωωω

sωβ

Rg1

1ω1

ωωs

Rg1

βωωωω

s

D(s)

cafsmca

2

a1

2

smfca

3

fsmca1

3

smfca1

4

LDO Closed Loop Transfer Function - H(s)Combining A(s), B(s), and C(s) into the expression for H(s) yields the following, which is ONLY shown for reference. AC1,A

D(s)N(s)

D(s)N(s)

AH(s) VV

The expression for H(s) contains 4 poles and one zero.

It is far too complicated to work from directly.

Stable response requires poles to be in left hand plane.

Analyze pole locations in terms of circuit parameters to make poles be critically or over-damped (no gain peaking in closed loop response).

1ωs

N(s)c

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LDO Closed Loop Transfer Function - H(s) - Continued

pacso

ω1

ω1

5ω1

RC

ma

ps

m

p

a g1

ωω3

Rg1

ω3ω

120

1

asmp ωRg1

ω1

τ

LDO Regulator Stability Design Guidelines:

1

f1p

ω1

ω1

ω

sR

fω

mg

pω1ω

τoC

- secondary pole for open loop (solve for).- error amp second pole (known or assumed).- driver pole frequency (if driver built in, let ).- gain bandwidth (from error amp analysis).- maximum driver transconductance gain (if driver built in, then is the output impedance of the regulator).- ESR resistance of output capacitor (solve for).- output capacitor (solve for).- overall loop response time (solve for).

aω1p ωω

mg1

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LDO Closed Loop Stability Analysis Conclusion

Following design guidelines for voltage divider and stability will yield stable LDO regulator.

Design can be optimized for speed with stable operation.

Little or no overshoot ringing for output transient currents.

Design guidelines can be used in reverse to find error amp gain bandwidth if output capacitor and ESR given.

Guidelines show designer which parameters to change to improve stability and/or loop response time for design and/or actual circuits.

Guidelines help designer to select proper controller/driver for application.

No need to solve for poles/zeros or graphically analyze Bode plots for unity gain phase margins.

All conditional guidelines must be met for stability.

Guidelines do not guarantee perfect operation due to unknown parasitics and unknowns.

Still need to simulate and prototype final design.

Following is a design example demonstrating use of guidelines.

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Example Design using GuidelinesExample LDO regulator design

demonstrating design guidelines.

Following graphs show closed loop

response for changes in circuit.

Circuit at left shows components

used for examples.

Design guidelines valid for other

circuit configurations as well.

These include PFET controllers and

bipolar (NPN and PNP).

Output stability necessary for steady

state and transient output currents.

Circuit parameters:MC33567 - 5MHz gain bandwidth 50 ohm output impedance Optimized internal dividerMTD3055 - 7 mhos transconductance gain 2200 pf input capacitanceLoad - 0.9A (2 ohms)

+

-InternalDivider

Error Amp

1.25V Ref

1.8VOutput

LoadOutput Cap

1/2-MC33567

LDO Controller

MTD3055NFET

3.3V

GndGnd

12V

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Frequency Response Analysis

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Changing the ESR (Rs) of the output capacitor beyond the recommended upper and lower limits tends towards instability (gain peaking).

Making the ESR larger speeds up the closed loop response but may increase the magnitude of the initial transient response due to fast changes in output current.

Waveform for varying ESR of output capacitor.

Rs = 30 milliohms appears optimal.(Co = 10,000uF).

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Waveform for varying output capacitance.

Output capacitance less than lower limit tends towards instability (gain peaking).

Output capacitance greater than lower limit yield same result (choose type and value to meet ESR requirements).

Co > 100uF yields same response.(Rs = 30 milliohms)

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Waveform for changing output driver - gm and Ci.

System optimized for using MTD3055.

Changing output driver FET can impact loop stability (as shown for this example).

If drivers need to be interchangeable, design for higher gain device (gm) and others will be stable (although loop will be slower).

MTD3055: gm = 7, Ci = 2200pf

MTD3302: gm = 28, Ci = 6600pf

(Co = 500uF, Rs = 30mohm)

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Waveform for varying gain bandwidth of controller

System optimized for gain bandwidth of MC33567 (5MHz).

Making gain bandwidth higher tends towards instability (gain peaking).

If designing with error amp compensation, can achieve stability by varying gain bandwidth.

Designed for (Af)o = 5MHz.

(MTD3055, Co=500uF, Rs=30mohm)

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Transient Response in Stable LDO regulators Transient response for changes in output currents becomes straight forward if LDO

regulator closed loop response is stable.

Magnitude of transient depends on rate/magnitude of change and ESR of output capacitor.

Worse case is step change in output current ( ).OΔI

OΔV

OΔIOI

OV

Typical Transient Response Time for transient to return

to nominal output is proportional to closed loop response time.

Following is example of previous regulator design transient response for stable and “less than stable” conditions.

τt 5s

sOO RΔIΔV

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sec1.5ts sec0.3τ (for optimized design)

(from graph)

Transient Response Example for Previous Design

From graph, optimized design is critically damped.

Over optimized designs slower but stable.

Designs outside of guidelines tend to oscillate.

Response time and transient amplitude agree with guidelines.

MTD3055: gm = 7, Ci = 2200pf

(Co = 500uF, Rs = 30mohm)

30mVΔVO

1AΔIO 30mRs

(from graph)

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Specify design output voltage and current (steady state and transient).

Follow design guidelines.

Select controller best suited.

Simulate and prototype circuit.

Adjust components for optimal performance.

Presentation Summary

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Reduces the total number of discrete & passive components thereby simplifying

and or reducing:

- System Cost - Procurement activity- Design Complexity - Overall size - Insertion cost - Component count - Performance inconsistencies - Solder reliability issues

A small-package-scale integration effort that combines multiple discrete, logic

and MOS devices, which may include passive devices (resistors, capacitors,

inductors).

MicroIntegrationTM

To TurnThis…

Into This…

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Customer benefits

Improve marketplace opportunities

- Performance improvement

- Size reduction

- Reliability improvements

- Component interaction reduction

Reduce overhead costs

- Inventory Purchase Management

- Floor and shelf space

- Inspection

- Component Obsolescence

Lower manufacturing costs

- Assembly line setup time

- Capital equipment utilization

- Equipment costs

- Assembled wrong part ( yield)

- Reduced insertion costs

Lower materials costs

- Component costs

- Board/substrate costs

- Eliminate parts (eg.: shields)

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Three types of products comprise the portfolio

+Vcc

I/O 1I/O 2

Transient Protection Arrays

Drive Circuits

Filter circuits

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MicroIntegrationTM Markets

Automotive

– 42/14v systems, in-car entertainment systems

Computing

– Power Supplies, Laptop, PC/ MTB PC, Server/ MTB Server, Work Station, Main Frame, Mid-range,

Storage, Disk Drives, Peripherals, Printers, Monitors, Scanners

Consumer

– Power Supplies, Set-Top Boxes, Game Consoles, Smartcards, MP3s, DVDs, VCRs, Camcorders,

Digital Cameras, Appliances, CD/ DVD Players, Handheld Game Boys

Wireless & Portable

– Power Supplies/chargers, Mobile Phones, Cordless Phones, Pagers, HH PC/PDA,Smartcards,.

Transient Voltage Suppression (TVS)

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Transient Protection Applications

IC Protection

IC CardI/OInput voltage

InputConnector

Filters

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Low Pass Pi filter with TVS Protection

Frequency(MHz)

Attenuation

Defines Cut off frequency

Transient Protection diodes

10 100 1000 3,000

30

27

24

21

18

15

12

9

6

3

0

Gai

n(dB

)1

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Filter Circuits

R

#1 #3

#6 #5 #4

1

2

3

NC

4

5

6

789101112

13

14

15

16

17

18

19 20 21 22 23 24

R

R

Drive Circuits

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Drive Circuits

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Analog DeviceMC33340, MC33342Battery Fast ChargeControllers

MicroIntegrationTM

Charge Controller Solution

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Today’s Solution For Lithium-Ion Battery Management

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Power Sequencer

Application:

3.3V/1.8V Power Sequence

Market Segment:

Computing

End Products:

Mother Board

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Lithium Battery Driver

V

R22.2k

R110K

R1110k

Q22N7002LT1

V R67.5

R310k

V

R7230k

V5

4.0Vdc

R8470k

0

R1047k

D12D1N5231V

C222pf

R9

330

Q5

Q2SD1819

V60.3Vdc

D1MBR130P

V79Vdc

Q1Q2SD1819

Q4Q2SA1182

U1ALM324/MC

3

2

411

1

+

-

V+V-

OUT

Sim ulates 12 m a load for IC supply current.

S im ulates the battery.

Application:

Lithium Battery Driver

Market Segment:

Wireless,Consumer

IC control

Battery charge

End Products:

Hand Helds

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Foldback Current Limiter

Q3Q2SC2712

D2D1N4148

Q1Q2SA1162

C11uf

D3D1N4148

R9 1k

R243k

R1210K

0

R114.3K

R101k

D4SMBJ10

12

R1 10

R3 10K

Q2Q2SA1162

9V

Output

Enable

Application:

Over Current Protection

Market Segment:

Consumer

End Products:

Set Top Box- 3 per box.

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uP to FET Driver - Automotive

Application:

Bias Driver Circuit

Market Segment:

Automotive

R8

1k

Q5

Q2N2907

Q4

Q2N2222

R6

1k

Q1

Q2N2222

R7

1k

0

R5

1k

R10

1k

<Doc> <RevCode>

<Title>

A

1 1Friday, October 26, 2001

Title

Size Document Number Rev

Date: Sheet of

R3

1k

R9

1k

Q3

Q2N2222

R21k

R1

1k

R4

1k

uP input

3.3v

12 V Bat

FETinput

End Products:

Engine Control Module

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MicroIntegrationTM Packages

MicroLeadless™

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MicroLeadless™ Series

.040 x .020 .040 x .025

.080 x .080

0402 Diode Package 04025 Transistor Package

0808 Multilead Package

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MicroLeadless™ Package Platform

80 mils80 mils

Can Package 4

RC filter/E

SD

circuits in 1

Device

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Need library for parasitics

Bump inductance

Bump inductance

Need library for parasitics

Bonding inductance

Ground inductance

Flip chip model vs MicroLeadlessTM model

MicroLeadlessTM

Flip chip

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Bumped flip chip S21 vs frequency

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MicroLeadlessTM S21 vs frequency

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Alex LaraApplications Engineer

• BSEE from University of Guadalajara

• 5 years experience in applications

• Motorola, ON Semiconductor

• Engineering Lab Manager

• Multiple articles and application notes

ON Semiconductor

STANDARD DESCRIPTIVE JOB TITLE FOR AN APPLICATIONS ENGINEER WITHIN THE SEMICONDUCTOR MARKET: Develop new product ideas and specifications; build hardware/software prototypes to verify new product feasibility; design and build new product evaluation and demo boards; develop SPICE macro models and perform system simulations of new products and applications; assist in evaluating and debugging new products; evaluate and build comparative matrices of Competitive products; generate product briefs, data sheets and application notes; conduct on-site design programs of new products with market leading Alpha site companies; and interface with customers and sales staff and provide technical training to Sales and FAE's.

• Develop new applications concepts• New designs implementation• Technical Reports• Simulation of applications circuits• Design-ins• Applications Notes Development• Troubleshooting Customer Application needs• SPICE simulations Development

Applications Engineering Key ActivitiesApplications Engineering Key Activities

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Universal Serial Bus

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ctor

ON Semiconductor Applications Engineering Activities for USB Port Applications

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Background

USB, or Universal Serial Bus, is a peripheral bus connectivity standard which was conceived, developed and is supported by a

group of leading companies in the computer and telecommunication industries – Compaq, DEC, IBM, Intel, Microsoft, NEC

and Northern Telecom. The current standard published and implemented on most of the USB devices is version 1.1,

nevertheless, the good news is, USB is getting even faster, USB 2.0 promises even higher data transfer rates, up to 480 Mbps.

The higher bandwidth of USB 2.0 will allow high performance peripherals, such as monitors, video conferencing cameras,

next-generation printers, and faster storage devices to be easily connected to the computer via USB. The higher data rate of

USB 2.0 will also open up the possibilities of new and exciting peripherals. USB 2.0 will be a significant step towards providing

additional I/O bandwidth and broadening the range of peripherals that may be attached to the PC.

USB 2.0 is expected to be both forward and backward compatible with USB 1.1. Existing USB peripherals will operate with no

change in a USB 2.0 system. Devices such as mice, keyboards and game pads, will not require the additional performance that

USB 2.0 offers and will operate as USB 1.1 devices. All USB devices are expected to co-exist in a USB 2.0 system. The higher

speed of USB 2.0 will greatly broaden the range of peripherals that may be attached to the PC. This increased performance will

also allow a greater number of USB devices to share the available bus bandwidth, up to the architectural limits of USB.

USB 1.1 devices operate at two different levels of speed:• Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)• Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)

USB 2.0 devices operate are compatible to operate at three different levels of speed:• Low speed, 1.8Mb/s equivalent to 900KHz (ENCODE, NRZI – Non Return Zero Inverter)• Full speed, 12Mb/s equivalent to 6MHz (ENCODE, NRZI – Non Return Zero Inverter)• High speed, 480Mb/s equivalent to 240MHz (ENCODE, NRZI – Non Return Zero Inverter)

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USB allows for multiple peripheral connectivity with one (1) Host 1 PC.

Host PC-USB Hub Connection

D. Cameras

ScannersAdd other HUBs

Printers

PDAs

CellPhones

USB Connectivity

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1) ESD Protection and surge protection• Devices must comply with the IEC 61000-4-2• Comply with Telcordia (formerly Bellcore) GR1089 on Surge 8x20usec waveform• USB 2.0 now requires Transmission Speeds up to 480Mbits/sec (240MHz), that forces to get lower capacitances (<5pF)

3) EMI Filtering / Termination – Detection • Pi Filters (RC), T Filters (LC)• Pull up & Pull down resistors for speed detection (Rpu, Rpd)• Impedance matching resistors (Zhsdrv)

2) Power Management• 5V – 3.3V Regulators• Features• Power switch (pending to research)

USB Device/Circuit/ComponentUSB Device/Circuit/ComponentProtectionProtection

USB Power Management USB Power Management forforHost and PeripheralsHost and Peripherals

USB Signal IntegrityUSB Signal Integrity

USB Opportunities Areas

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Considerations for the USB ESD and TVS Protection

• IEC 61000-4-2 Contact and Air Discharge compliance for ESD Protection.• Obtaining the lowest insertion loss in the transmission line over a specific operating bandwidth.• Lower capacitances (less than 5pF5pF) to support USB 2.0USB 2.0 transmission speeds up to 480Mbits/sec (240MHz).480Mbits/sec (240MHz).

[example… ESD/TVS from connection your PDA to your computer]

USB ESD Applications

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Typical USB ApplicationTypical USB ApplicationDual USB port protection

Single USB port protection

HOSTHOSTPCPC

D. D. CamerasCameras

PDAsPDAsPrintersPrintersScannersScanners

etc.etc.

USB ESD Applications (cont’d)

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Compliance with IEC 61000–4–2, ESD International Standard This International Standard relates to the immunity requirements and test methods for electrical and electronic equipment subjected to static electricity discharges, from operators directly, and to adjacent objects. It additionally defines ranges of test levels which relate to different environmental and installation conditions and establishes test procedures. The object of this standard is to establish a common and reproducible basis for evaluating the performance of electrical and electronic equipment when subjected to electrostatic discharges. In addition, it includes electrostatic discharges which may occur from personnel to objects near vital equipment.IEC 61000-4-2 Test Levels

This figure shows a real8KV contact waveform taken from the ESD generator.

This figure shows how the TVS clamps the ESD condition from 8KV to 8.7V, this is the way in which protection against ESD conditions is achieved by using TVS

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Low capacitance (less than 5pf) for High speed I/O Data lines (USB 2.0) “Low capacitance (< 5.0 pf)” is one of the most important characteristics that any device intended to be used in USB applications must have in order to minimize the signal attenuation at high speed data rate (480 Mbs, USB 2.0). This characteristic is critical, otherwise, the functionality of the USB system could be affected dramatically during high speed operation. Actually, the USB2.0 spec establishes that the capacitance between I/O data lines lines must no be higher than 5pf.

Junction capacitance ModelSimplified Junction capacitance Model

Theoretical principle used to predict the capacitance between I/O lines for the NUP4201DR2 device

C=4.52pf

Real Lab measurementsThe total devices characterized showedan average capacitance value of around 4.45 pf between I/O lines whichcomplies with the USB 2.0 specification (5.0 pf maximum) and reflects the resultsobtained from the pspice model.

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USB EMI Filtering/TerminationEMI Filtering for USB 2.0 EMI Filtering for USB 2.0 Applications.Applications.

UpstreaUpstreamm

DownstreaDownstreamm

Common Common mode chokemode choke

inductorsinductors

For USB 2.0 applications, the usage of common mode choke inductors is very common for EMI filtering purposes since no extra capacitance is added between the I/O data lines.

ON Semiconductor


The equivalent PSPICE circuit for a TDK Choke model ACM2012-900-2P is shown below and also, its configurations for common and differential mode operation:

R1_3

14

C2_2

0.02p

R121G

TX1

C1_3

0.84p

Input1

0

C2

0.02p

R545

L1_4

3.1n

1 2

R1

14

R745

V4

TD =

TF = 500psPW = 1.58nsPER = 4.1666ns

V1 = 0

TR = 500ps

V2 = 300mVC12

0.95p

V

R3_2

0.065

Output1

R1_2

14

V

R3

0.065

R1_4

14

R3_4

0.065

L1

3.1n

1 2

R2_2

880

C12_20.95p

C1_2

0.84p

C1

0.84p

R6 45

R2

880

L1_3

3.1n

1 2

C1_4

0.84p

R4 45

R12_21G

R3_3

0.065

L1_2

3.1n

1 2

C1

0.84p

R2

880

R3

0.065

Input1

0

C1_2

0.84p

V4

TD =

TF = 500psPW = 1.58nsPER = 4.1666ns

V1 = 0

TR = 500ps

V2 = 300mV

L1_4

3.1n

1 2

R3_2

0.065C2_2

0.02p

R545

C12_20.95p

R1_2

14

TX1

R2_2

880

R1_3

14V

Output1

C1_4

0.84p

R3_4

0.065

C2

0.02p

L1_3

3.1n

1 2

R4 45

C1_3

0.84p

R1_4

14

V

R121G

L1_2

3.1n

1 2

L1

3.1n

1 2

R1

14

R12_21G

R745R6 45

C120.95p

R3_3

0.065

Common Mode

Differential Mode

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USB EMI Filtering/TerminationEMI Filtering for USB 2.0 EMI Filtering for USB 2.0 Applications.Applications.Common and Differential mode response of the TDK Choke model ACM2012-900-

2P: Common Mode.In common mode operation, the Chokewill have very high attenuation and willnot allow the noise to go into the system. As shown in the graph (Common Mode), it starts havinghigh attenuation (-10dB or higher) when the frequency is around 50MHz.shows a high loss characteristics.

Fr e que nc y

1 . 0MHz 10MHz 100MHz 1. 0GHz 10GHz20*LOG10( V( R5: 2) / V( R4: 2) )

- 30

- 20

- 10

0

Fr e que nc y

1 . 0MHz 10MHz 100MHz 1. 0GHz 10GHz20* LOG10( V( R5: 2) / V( R4: 2) )

- 15

- 10

- 5

0

Differential Mode.In differential mode operation, the choke will not have high attenuation unless the noise signal is very high frequency (5GHz or higher). As shown in the graph, it starts having high attenuation (-10dB or higher) when the frequency is around 5GHz.

ON Semiconductor


R6 45

R545

C1_4

0.84p

Output1

C12_20.95p

R745

L1_2

3.1n

1 2

R2_2

880

0

R1_2

14V-

L1_4

3.1n

1 2

R12_21G

C2

0.02p

C1

0.84p

V2

TD =

TF = 10psPW = 0.09nsPER = 0.2ns

V1 = 0

TR = 10ps

V2 = 100mV

Input1

V+

C120.95p

V1

TD =

TF = 500psPW = 1.583nsPER = 4.166ns

V1 = 0

TR = 500ps

V2 = 300mV

R4 45

V+

R1_3

14

R3_2

0.065

R121G

R3_3

0.065

R1

14

R3

0.065

R1_4

14

L1_3

3.1n

1 2

C1_3

0.84p

TX1

L1

3.1n

1 2

R2

880

V-C2_2

0.02p

C1_2

0.84p

R3_4

0.065

Ti me

0s 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns 10nsV( R5: 2 , R7: 1) V( R4: 2 , R6: 2)

0V

50mV

100mV

150mV

200mV

TDK Choke Filtering response(Differential mode)

V1= USB 2.0 signal applied (240MHz)V2 = Noise signal (5GHz)

ON Semiconductor


C13pf

V+

C33pf

R5 45

0

R2 7

V2

TD =

TF = 500psPW = 1.58nsPER = 4.166ns

V1 = 0

TR = 500ps

V2 = 300mV

R1 7

V+R645

V-

R445

V-

C23pf

L2 7nH1 2

L1 7nH1 2

R3 45

V1

TD =

TF = 10psPW = 90psPER = 200ps

V1 = 0

TR = 10ps

V2 = 100mV

C43pf

Ti me

0s 1ns 2ns 3ns 4ns 5ns 6ns 7ns 8ns 9ns 10nsV( R3: 1 , R5: 2) V( R6: 2 , R4: 1)

0V

50mV

100mV

150mV

200mV

V1= USB 2.0 signal applied (240MHz)V2 = Noise signal (5GHz)

LC Filter,Filtering response(Differential mode)

ON Semiconductor

CONCLUSION:

• Applications Engineers are key in the definition and understanding of the guide lines

for New Products Development.

• Applications Engineers are key to increase the business of the companies because

most of the time they represent an added value for the customers which allows to

create a relation-ship between the company and the designers, thereby, creation of

new business opportunities.

• Applications Engineers are key to promote the companies’ products by educating the

sales department, supporting trade-shows and developing demo-kits.

• Applications Engineers are key to win design-ins because they can help in

suggesting the most proper device for any particular application and also they can

show and explain the capability of the companies’ products.

ON Semiconductor

applications engineering. on semiconductor page 2 doing what we said we would do… or why customers...

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