ARCHITECTURE.ARCHITECTURE.

PRR November 2003

2 x 32 PADs

Up to 26 or 3 x 17 MANU BOARD.

PATCH BUS

TranslatorBoard.

FEE

FEE

DETECTOR

Up to 100 PATCH BUSper detector.

MANU

CROCUS CrateUp to 50 PATCH BUS connected.

SOFTWARE

FRT CRT

Optical link:DDL

100 meter.

PC

DAQ

LOW VOLTAGE

HIGH VOLTAGE

SLOW CONTROL

Link to download: Pedestals. DSP code.

Optical link:DDL

100 meter.

10 Meter max

Rib

bon

cabl

e

Ribbon cable40 meter

MANU: MANAS Numérique.

PATCH: Protocol for Alice Tracking Chamber.

CROCUS: Concentrator Read Out

Cluster Unit System.

FRT: Frontal.

CRT: ConcentRaTeur.

TCI: Trigger Crocus Interface.

From CTPTrigger information:

L0, L1…..

TCI One crate for all

CROCUS.

FFT

FTD

ETHERNET:- Monitoring.- Stand alone DAQ.- Test configuration.

TTCrx

Tra

nsl

at

or

Patch Bus

2 *3

2 ce

lls

FRONT

BOARD

FRONT

BOARD

FRONT

BOARD

CONCENTRTOR

BOARD

FRONT

BOARD

FRONT

BOARD

FRONT

BOARD

CONCENTRTOR

BOARD

40 meters LVDSLINKPORTS TRIGGER

BUSY, and L0

DDLLDC

GDC

CROCUS

FEEs-Chain

Total no of cells : 221184Total no of Modules : 481 module = 4608 cells.

1 CROCUS - 50 Patch Buses6 CROCUS – 300 Patch Buses

PMD Readout ArchitecturePMD Readout Architecture

From CTPTrigger information:

L0, L1…..

TCI One crate for all

CROCUS.

FFT

FTD

ETHERNET:- Monitoring.- Stand alone DAQ.- Test configuration.

TTCrx

PMD(Two planes)

6 CROCUS 6 DDL (4 PRESHOWER, 2 CPV)

Preshower24 modules12 long type12 short type

CPV24 modules12 long type12 short type

PRESHOWER

CROCUS#0 48 chains

CROCUS#1 48 chains

CHAIN CONFIGURATION

The No. of FEEs has been decided considering the occupancy in that zone

PRESHOWER

CROCUS#2 48 chains

CROCUS#3 48 chains

CHAIN CONFIGURATION

CPV

CROCUS#4 45 chains

CROCUS#5 45 chains

CHAIN CONFIGURATION

Base Header

Sub-event:

(Header extension)

Event Fragment

Event Fragment

LDC

Equipment Header

Event fragment:

Equipment payload =

Common data header

+ raw data

DDL

GDC

Sub-event

Sub-event

Sub-event

Sub-event

Base Header

Event:

(Header extension)

Event Logic StructureEvent Logic Structure

T1

FRT-DSP 1PATCH bus

Link-port

Link-port

Link-port

Link-port

Link-port

FRT-DSP 2

FRT-DSP 3

FRT-DSP 4

FRT-DSP 5

PATCH busPATCH bus

PATCH busPATCH bus

Serial port FRT-CRT-DSP2

T1

T2

SIU interfaceParallel bus

T4T4

structDdlHeader

Note: :

T3 from FRT-CRT-DSP2

T3 from FRT-CRT-DSP3T3

stPatchHeader

Raw data

Raw data

T2

stFrtEvntHeader

T1 * [0..5]

stFrtCrtEvntHeader

T2 * [0..5]

T3

struct StPatchHeader { ui32 fuiPatchDataKey;//0xB000000B ui32 fuiTotalLength; ui32 fuiRawDataLength; ui32 fuiPATCHID;}

struct StFrtEventHeader { ui32 fuiFrtDataKey; // 0xF000000F ui32 fuiTotalLength; ui32 fuiRawDataLength; ui32 fuiDspID; ui32 fuiCrt1L1aTriggerCounter; ui32 fuiMiniEvntIdBunchCrossing; ui32 fuiFrtL1aTriggerCounter; ui32 fuiFrtL1rTriggerCounter; bool fbEvenPadded; ui32 fuiErr; }

struct StFrtCrtEventHeader {

ui32 fuiFrtCrtDataKey; //0xFC0000FC Filled by FrtCrtEventDumper ( Frt-Crt 2&3 )

ui32 fuiTotalLength; // Filled by FrtCrtEventDumper ( Frt-Crt 2&3 )

ui32 fuiRawDataLength; // Filled by FrtCrtEventDumper ( Frt-Crt 2&3 )

ui32 fuiFrtCrtDspID; // Filled by FrtCrtEventDumper ( Frt-Crt 2&3 )

ui32 fuiCrt1L0TriggerCounter; // Filled by DdlDumpingManager (Crt1)

ui32 fuiMiniEvntIdBunchCrossing; // Filled by DdlDumpingManager (Crt1)

ui32 fuiEvntId1BunchCrossing; // Filled by DdlDumpingManager (Crt1)

ui32 fuiEvntId2OrbitNumber; // Filled by DdlDumpingManager (Crt1)

// ui32 fuiEvenPadding; // Filled by FrtCrtEventDumper ( Frt-Crt 2&3 )

};

struct StDdlHeader { ui32 fui32BlockLengthInBytes;//--------------------------------------------- ui32 fui8FormatVersion :8; ui32 fui8L1TriggerType :8; ui32 fui4Reserved1 :4; ui32 fui12EvntId1BunchCrossing

:12;//--------------------------------------------- ui32 fui8Reserved2

:8; ui32 fui24EvntId2OrbitNumber

:24;//--------------------------------------------- ui32 fui8BlockAttributes :8; ui32 fui24ParticipSubDetectors

:24; //--------------------------------------------- ui32 fui4Reserved3

:4; ui32 fui16StatusErrBits :16; ui32 fui12MiniEvntIdBunchCrossing :12;//--------------------------------------------- ui32 fui32TriggerClassesLow;//--------------------------------------------- ui32 fui4RoiLow

:4; ui32 fui10Reserved4

:10; ui32 fui18TriggerClassesHigh :18;//--------------------------------------------- ui32 fui12RoiHigh

;}

DDL TRAILERS 2 Words : 0xD000000D If (bEvenPadded=true T3 block

will terminate by junk32 bit word

m_uiEvenPadding is just used to makestructFrtCrtEvntHeader header size evenm_uiEvenPadding=0xDEADBEEF

Note:

DDL Data Format DDL Data Format

12 3 4567 8910111213141516 17 18 19202123 22242526272829303132

P 0 0

0 0

0 1

1 0

1 1

MANAS Adr. 0 P = Parity bit ( 1 bit) M = FEE board address ( 11 bits )

G = MANAS address ( 2 bits )

C = Channel number ( 4 bits )

D = Data ( 12 bits )

DATA WORD ( FEE) DATA WORD ( FEE)

Output Word

D D D D D D D D D D D DC C C CG GM M M M M M M M M M M

MANAS Adr. 1

MANAS Adr. 2

MANAS Adr. 3

typedef struct { unsigned adc :12; unsigned channel :6; unsigned fee :11; unsigned unused :2; unsigned parity :1; }PmdRawDataWord;

Detector Id

Detector Name

DDL Offset

# of DDL

DDL Index

Connected to

Equipment Id

9 PMD

2304 6

0 CROCUS#0 2304

1 CROCUS#1 2305

2 CROCUS#2 2306

3 CROCUS#3 2307

4 CROCUS#4 2308

5 CROCUS#5 2309

DDL / Equipment ID scheme

Hardware mapping

Done in 2 steps

Idea is to convert DDL No., patch Bus No., FEE No., Channel No. to the (x,y) coordinate

1. DDL No., PATCH Bus No., FEE address give the physical locationOf the FEE Board

2. FEE Board, Channel No give the (x,y) coordinate of the cell

Hardware Mapping : Step 1. Module # 0

0 8 15 23 31 39 47

0

15

31

47

63

79

95

•There are six mapping file for six DDLs.

•PMD_Mapping_ddl*.dat contains this mapping.

•Once the FEE Board physical loacation within a module is identified, Step-2 is applied

Channel Number to (x,y) : Step 2.

This conversion is doneInside the program

Status :

Hardware Mapping : done ( Committed to CVS)

Raw data reconstruction : in place (CVS), to be tested in this test beam

Raw data format : in place (CVS), to be tested in this test beam

Removal of gAlice : by 31st October, 2006

Raw2(s)Digits : by 31st October, 2006

DDL / Equipment ID scheme

FEE BOARD CONFIGURATION

DETECTOR

MANAS

MANAS

MANAS

MANAS

T/H

CLR

CLK-1

CLK-2

Analog Out

Analog Out

ADC 0

ADC 1

CS

CLK-ADC

12 Bit ADC

12 Bit ADC

AD 7476

AD7476

KM 4110

KM4110

MARC

CAL

TO

KE

N-I

NT

OK

EN

-OU

T

CO

NT

RO

L S

IGN

AL

S

DIGITAL BUS-LVTTL

DA

TA

SIG

NA

LS

, LP

CL

K

LIN

K P

OR

T

Main Components: 1. MANAS (Multiplexed-Analog-Signal- processor )2. MARC ( Muon-Arm-Readout-Chip )3. ADC (Analog to Digital Converter )

FEE board

CROCUS SYSTEM MAIN SIGNALS & I/O PORTS

FRT-DSP 1PATCH bus

IRQ

1 : L

1 re

ject

IRQ

2 : L

1 ac

cept

IRQ

0 : T

oke

n

FRT-CRT-DSP2 Parallel busLink-port

Link-port

Link-port

Link-port

Link-port

CRT1-DSPParallel bus

IRQ

0 :

L0

FRT-DSP 2

FRT-DSP 3

FRT-DSP 4

FRT-DSP 5

FRT-CRT-DSP3 Parallel busFRT-DSP 8

FRT-DSP 9

FRT-DSP 10

PATCH busPATCH bus

PATCH busPATCH bus

Pa

ralle

l bus

LCA trigger

Link-port trigger

Link-port

SIU interfaceParallel bus

Serial port FRT-CRT-DSP2

Link-port

Link-port

Link-port

Link-port

Link-port

Serial port

FTD

FRT-DSP 7

FRT-DSP 6

LDC

VIR

PT

inte

rrup

tV

IRP

T in

terr

upt

Chain to FEE board connection

FEE boards

Translator board

Bridge board

L V

FEE board arrangement in short type module Patch bus

FEE board arrangement in long type module

12 3 4567 8910111213141516 17 18 19202123 22242526272829303132

P 0 0 M M M M M M M M M M M

D D D D D D D D D D D DC C C C G G

0 0

0 1

1 0

1 1

MANAS Adr. 0P = Parity bit / M = MANU Address ( 11 Bit )

G = MANAS Address

C= Channel number / D = Data ( 12 Bit )

DATA WORDDATA WORD

MANAS Adr. 1

MANAS Adr. 2

MANAS Adr. 3

Output Word