arithmetic in computers. 2301274chapter 4 arithmetic in computers2 outline data representation...
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Arithmetic in Computers
2301274 Chapter 4 Arithmetic in Computers 2
Outline
• Data representation• integers
• Unsigned integers• Signed integers
• Floating-points
• Addition and subtraction• Multiplication• Division• Floating-point operations
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Unsigned integers• Binary representation in a word (4-bytes)• Byte Ordering
• 200000000 is represented as follows
0000 1011 1110 1011 1100 0010 0000 0000• How to store it in memory addressed N
• Big Endian (big end is stored first)
• Little Endian (little end is stored first)
0000 1011 1110 1011 1100 0010 0000 0000Address:N N+1 N+2 N+3
0000 0000 1100 0010 1110 1011 0000 1011Address:N N+1 N+2 N+3
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Signed Integers• Sign and magnitude
representation
• Problems• 2 representations of zero
• +0: 00000…000• -0: 10000…000
• More complex adder
• 2’s complement representation• Example: 4-bit representation
0000 0 1000 -80001 1 1001 -70010 2 1010 -60011 3 1011 -50100 4 1100 -40101 5 1101 -30110 6 1110 -20111 7 1111 -1
• Problems• The sizes of largest positive
and smallest negative are different by 1.
Sign bit magnitude
Same as sign and magnitude representation
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Converting 2’s complement binary
• What is the 2’s complement representation of -3?• Using 8-bit representation, 3 is 0000 0011.• To get 2’s complement representation of -3
0000 0011 (3)
bitwise complement
1111 1100
add 1
1111 1101
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Calculate value from 2’s complement• For n-bit 2’s complement bn-
1 bn-2 … b1 b0
• Value: -bn-12n-1 + ∑ 0
n-2 bi2i
Ex: 1110 0111 represents the value -1000 0000 + 110 0111
= -128 + 103
= -25
• If bn-1=0, the value 0
(i.e. ∑ 0
n-2 bi2i )
• If bn-1=1, the value <0
(i.e. ∑ 0
n-2 bi2i – 2n-1)
• For n-bit 2’s complement bn-1 bn-2 … b1 b0
Value:
• if bn-1=0
• (bn-2 … b1 b0)2
• if bn-1=1
• Negative of the value of 2’s complement of (bn-2 … b1 b0)2
Ex: Consider 1110 0111.
2’s complement of 110 0111 is (001 1000 + 1) = 001 1001, which is 25.
1110 0111 represents -25.
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Advantages of 2’s complement representation
• Only one representation of zero.
• Most significant bit acts as sign bit.
• 2’s complement of 2’s complement of x is x.
• Simple for hardware design.
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Sign ExtensionIn machine code, addi $t0, $t0, -3 is
• To copy -3 (FFFD) to be added to $t0, -3 needed to be extended to 32 bits (4 bytes).
• It is not possible to put 0’s in the upper 2 bytes
• Put 1’s in the upper 2 bytes
31 26
25 21
20 16
15 0
op rs rt Const/addr
0 0 1 0 0 0
1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
2 2 1 1 F F F D
F DF FF DF F? ?? ?
F DF FF DF F0 00 0
F DF FF DF FF FF F
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Sign Extension
• Other operations which require sign extension.• Load /store byte• Load/store halfword
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Addition & Subtraction Binary addition/subtraction
0110 1100 1080011 1101 + 61 +1010 1001 1690110 1100 1080011 1101 - 61 -0010 1111 47
0011 1101 610110 1100 - 108 -
1101 0001 -47
2’s complement addition/subtraction
0110 1100 1080011 1101 + 61 +1010 1001 169
0110 1100 1081100 0011 + -61 +0010 1111 47
0011 1101 611001 0100 + -108 +
1101 0001 -47
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n-bit adder n-bit subtractor
n-bit adder
…
…
xn-1 xn-2 x1 x0
zn-1 zn-2 z1 z0
CinCout
…
yn-1 yn-2 y1 y0
0 n-bit adder
…
xn-1 xn-2 x1 x0
CinCout
…yn-1 yn-2 y1 y0
1
…zn-1 zn-2 z1 z0
x y x y
0 0 0
0 1 1
1 0 1
1 1 0
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Adder/ subtractor
yn-1 yn-2 y1 y0
n-bit adder
…
…
xn-1 xn-2 x1 x0 sub
zn-1 zn-2 z1 z0
CinCout
x y x y
0 0 0
0 1 1
1 0 1
1 1 0
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Overflow
Operation Operand A Operand BOverflow if result is …
A+B + + -A+B - - +A-B + - -A-B - + +
Overflow occurs when the result of an operation is too large to fit in a word.
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Multiplication
01011001 5916
00101011 x 2B16 x
01011001 3D3 01011001 B2 00000000 EF3 01011001 00000000 01011001 0111011110011
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Multiplication AlgorithmSTART
Multiplier0=0?
Add Multiplicand to Result
Result=0; loop=0
Shift left Multiplicand once; Shift right Multiplier once; Increment loop
loop<32?
STOP
F
T
F
T
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Hardware: Sequential Multiplication
Multiplicand(64-bit shift-left register)
Multiplier(32-bit shift-right register)
Result(64-bit register)
test 32 loops
64-bit ALU
test Multiplier0
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Hardware: Parallel Multiplication
32-bit adder
32-bit adder
32-bit adder
32-bit adder
32-bit adder
. . .
Mplier0 ·Mcand
Mplier3 ·Mcand
Mplier1 ·Mcand
Mplier30 ·Mcand
Mplier31 ·Mcand
Mplier2 ·Mcand
prdt0
prdt2
prdt3
prdt1
prdt30
prdt63-31
1 bit
1 bit
1 bit
1 bit
1 bit
32 bit
32 bit
32 bit
32 bit
32 bit 01011001(Mcand) 00101011(Mplier)x 01011001 01011001 00000000 01011001 0000000001011001 0111011110011
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Division 11101 1010 )100100101 1010 10000 1010 1101 1010 110 000 1101 1010 11
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Division AlgorithmSTART
Remainder<0?
Shift left Quotient and set rightmost bit to 1
Remainder = Remainder – Divisor
Shift right divisor once; Increment Loop
loop<33?
STOP
F T
F
T
Shift left Quotient and set rightmost bit to 0 Restore Remainder
Initialization:Quotient = 0Remainder = DividenDivisor = Divisor<<32Loop = 1
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Execution
0111 0000 1111 0000 1111 0000 1111 0000
remainder
1100 1100 1100 1100 0000 0000 0000 0000
divisor
0000 1010 1000 1010 1111 0000 1111 0000
0110 0110 0110 0110 0000 0000 0000 0000
0000 0000 0000 0000
quotient
0000 0000 0000 0001
Round 12
0011 0011 0011 0011 0000 0000 0000 0000
3
0001 1001 1001 1001 1000 0000 0000 0000
0000 0000 0000 0010
4
0000 1100 1100 1100 1100 0000 0000 0000
0000 0000 0000 0100
5
0000 0110 0110 0110 0110 0000 0000 0000
0000 0000 0000 1000
6
0000 0100 0010 0100 1001 0000 1111 0000
0000 0011 0011 0011 0011 0000 0000 0000
0000 0000 0001 0001
7
0000 0000 1111 0001 0110 0000 1111 0000
0000 0001 1001 1001 1001 1000 0000 0000
0000 0000 0010 0011
8
0000 0000 1100 1100 1100 1100 0000 0000
0000 0000 0100 0110
Sol: 1000110100101101
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Hardware: Division
Divisor(64-bit shift-right register)
Quotient(32-bit shift-left register)
Remainder(64-bit register)
test 33 loops
64-bit ALU
test Remainder
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Improved Hardware: Division
Divisor(32-bit shift-right register)
Remainder(64-bit register)
test
32-bit ALU
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Floating-point Representation
exponent fraction
sign
(-1)s F 2E
Normalization is needed.
F=1.xxxxxxxxx2
Normalized number
E = exponent – biasIf bias=127.000…0 represents -12700…01 represents -1011…1 represents 0100…0 represents 111…10 represents 127
Why can’t 2’s complement be used?
What does 111…1 represents?
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IEEE 754 floating point standard
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
exponent fraction
sign
(-1)s F 2E
Single precision (bias=127)
Double precision (bias=1023)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
exponent fractionsign
31 0
fraction
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Floating-point value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
exponent fraction
sign
Value=(-1)sign (1.b22b21…b0)2 2((b30b29…b23)2 -bias)
Single precision
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Normalization
• If a floating-point is in the form of 0.xxx 2yyy, it is denormalized.
• To normalized F 2E
Repeat
{ F=F<<1
E=E-1
} until the MSB of F is 1
F=F<<1
E=E-1
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Special Cases for Floating-point• Range
• Max. number, min. number
• Precision• The last digit represented in
the number
• Special values (IEEE standard)
• exponent =(1…1)2 reserved
• Fraction = 0
• NaN (Not a Number)• exponent =(1…1)2 reserved
• Fraction 0
• Overflow occurs when the positive exponent is too large.
• Underflow occurs when the negative exponent is too large.
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Floating-Point AdditionLet X= F2B and Y= G2D , where F=1.A, G= 1.C• To add X and Y• If B<D
• find G’=G2D-B and Y= G2D =G’2B.• Z = (F+G’) 2B.
• If B>D• find F’=F2B-D and X= F2B =F’2D.• Z = (F’+G) 2D.
• If B=D• Z = (F+G) 2B.
• Finally, normalized Z.
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Floating-Point Multiplication
Let X= F2B and Y= G2D , where F=1.A, G= 1.C
Let Z= X Y = F2BG2D = (FG) 2B+D .
• To multiply X and Y• find FG, and B+D.• Z = (F+G) 2B+D.• Finally, normalized Z.
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Floating point operand in MIPS
• 32 floating-point registers• $f0, $f1, …, $f31
• Size of each register = 32 bits• 1 single-precision data can be stored in 1 floating-
point register.• 1 double-precision data must be stored in a pair of
floating-point registers.• For double-precision data, $f0 refers to the pair $f0,$f1.
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Floating-point ArithmeticInstruction Example Meaning
FP add single add.s $f2,$f4,$f6 $f2 = $f4 + $f6
FP subtract single
sub.s $f2,$f4,$f6 $f2 = $f4 - $f6
FP multiply single mul.s $f2,$f4,$f6 $f2 = $f4 * $f6
FP divide single div.s $f2,$f4,$f6 $f2 = $f4 / $f6
FP add double add.d $f2,$f4,$f6 $f2 = $f4 + $f6
FP subtract double
sub.d $f2,$f4,$f6 $f2 = $f4 - $f6
FP multiply double
mul.d $f2,$f4,$f6 $f2 = $f4 * $f6
FP divide double div.d $f2,$f4,$f6 $f2 = $f4 / $f6
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Floating-point Data TransferInstruction Example Meaning
load wordcoprocessor
1
lwc1 $f1,100($2) $f1 = Memory[$2+100]
store wordcoprocessor
1
swc1 $f1,100($2) Memory[$2+100] = $f1
load double l.d $f0,100($2) $f0 = Memory[$2+100]
$f1 = Memory[$2+104]
store double s.d $f0,100($2) Memory[$2+100] = $f0
Memory[$2+104] = $f1
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Floating-point ComparisonInstruction Example Meaning
branch on FP true
bc1t 100 if (cond == 1) go to PC+4+100
branch on FP false
bc1f 100 if (cond == 0) go to PC+4+100
FP compare single (eq,ne,lt,le,gt,ge)
c.lt.s $f2,$f4 if ($f2 < $f4) cond=1; else cond=0
FP compare double (eq,ne,lt,le,gt,ge)
c.lt.d $f2,$f4 if ($f2 < $f4) cond=1; else cond=0
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Note
• Data and program are stored in memory.• How to interpret what a bit sequence means
depends on what it represents• An assembly instruction
• See Instruction formats, fields, op codes
• Data• Unsigned integers: binary numbers• Signed integers : 2’s complement numbers• Floating-points:
• Exponent
• Fraction
• Sign
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