arithmetic process in computer systems
TRANSCRIPT
Arithmetic OperationsArithmetic Operations
Ir. SNMP Simamora, MT.Ir. SNMP Simamora, MT.
Arithmetic Unit OperationArithmetic Unit Operation
The arithmetic unit of a digital The arithmetic unit of a digital computer contains the logic computer contains the logic circuitry for performing circuitry for performing additions, substractions, additions, substractions, multiplications, and divisionsmultiplications, and divisions
Information to be processed by Information to be processed by the computer is generally placed the computer is generally placed in memory first taken into the in memory first taken into the arithmetic unit at some later timearithmetic unit at some later time
Computer Systems General Computer Systems General SchemeScheme
Arithmetic Unit OperationArithmetic Unit Operation
The arithmetic operations The arithmetic operations performed need only be those of performed need only be those of addition and substractionaddition and substraction
Ex: Ex: 5 X 2 5 + 5 + 5
12 2÷
12 2 = 10
10 2 = 8
8 2 = 6
6 2 = 4= 6
4 2 = 2
2 2 = 0
Serial Adder – Serial Adder – simplified block diagramsimplified block diagram
BRegister
ARegister
MSB LSB
Inputdata
Shift-pulses(SP)
Inputdata MSB LSB
MostSignificant
BitLeast
SignificantBit
Full Adder
SP
C0C1
Carry flip-flop(cleared at
start)
A
BC
Register
LSBMSB
Sum
Shift-pulses(SP)
Serial Adder – Serial Adder – Data at startData at start
1 0 1 1 1 0 1 1 0 0 0 1 0
0 0 1 0 1 1 0 1 1 0 1 1 0
- - - - - - - - - - - - -
1 1 0
0 1 1
- - -
FullAdder
0
1
C register
MSBLSB
C 0C 1
0
1
0
A
B
Sum
1
C 0
0
MSB
MSB
LSB
LSB
B register
A register
Serial Adder – Serial Adder – After first shift pulseAfter first shift pulse
- 1 0 1 1 1 0 1 1 0 0 0 1
- 0 0 1 0 1 1 0 1 1 0 1 1
1 - - - - - - - - - - - -
0 1 1
0 0 1
- - -
FullAdder
0
0
C register
MSBLSB
C 0C 1
0
1
1
A
B
Sum
0
C 0
1
MSB
MSB
LSB
LSB
B register
A register
1
0
Serial AdderSerial Adder
Input data is shift into the input Input data is shift into the input registerregister
This input number can then be This input number can then be serially added to the serially added to the Accumulator value stored in a Accumulator value stored in a second shift register; using one second shift register; using one of the full adder circuitsof the full adder circuits
Parallel Adder – Parallel Adder – logic diagramlogic diagram
AR
1A
R0
ExecuteSTACS2
MIR
FA FA FA FA FA
Data to MIR
Memory unit
ArithmeticunitMIR0
Input lines from MIR
MIR1
carrycarrycarrycarry
CS5
(CLA + ADD)
Execute
Accumulator Register(AR)
Clear accumulator
CLA Execute
CS1
MSB LSBAR1 AR0
Output
0
Parallel AdderParallel Adder
The logic circuitry is simpler, since The logic circuitry is simpler, since only an add signal is required to only an add signal is required to obtain parallel addition.obtain parallel addition.
A Full Adder (FA) circuit is required A Full Adder (FA) circuit is required for each bit positionfor each bit position
On an ADD instruction the data read On an ADD instruction the data read into the MIR is added to that in the into the MIR is added to that in the accumulator on CS5; the resulting accumulator on CS5; the resulting sum being transferred into the AR.sum being transferred into the AR.
Complement TechniqueComplement Technique
Utilizing the 1 or 0 bit to specify Utilizing the 1 or 0 bit to specify the plus or minus signthe plus or minus sign
This procedure specifically This procedure specifically requires using 1 for negative requires using 1 for negative sign and 0 for positive signsign and 0 for positive sign
Positive numbers are written Positive numbers are written with the 0 sign in the most with the 0 sign in the most significant position with the significant position with the positive absolute valuepositive absolute value
Complement TechniqueComplement Technique
Negative numbers are written with Negative numbers are written with the 1 sign in the ost significant the 1 sign in the ost significant position and the complement form of position and the complement form of the number.the number.
Both number, positive and negative, Both number, positive and negative, should be written with equal digits should be written with equal digits and sufficient number to include the and sufficient number to include the sum number without mixing up the sum number without mixing up the sign with the number part.sign with the number part.
Complement TechniqueComplement Technique
Ex: -Write the following numbers Ex: -Write the following numbers in signed form:in signed form: +7+7 +12+12 -3-3 -9-9 -20-20
Solution:Solution:
Number Absolute magnitude Signed (1’s complement)
Signed (2’s complement)
+7 001111
0 001111
0 001111
+12 001100 0 001100 0 001100
–3 000011 1 111100 1 111101
–9 001001 1 110110 1 110111
–20 010100 1 101011 1 101100
sign sign
Description Solution:Description Solution:Binary Decimal
4100 0 0 100 0 0
by-complemented 1, will be: (inverted/by-NOT)
1 1 1 011 1 1 1's Complement
by-complemented 2, will be: (ADD with 110 )
1 1 1 011 1 1
0 0 0 000 0 1
1 1 1 111 0 0 2's Complement
Ex: Ex: (00011001)(00011001)22 + (00010011) + (00010011)22 = (…) = (…)22
Solution:Solution:1 1 = 0
=0 1 0
=0 0 1
carry 1
=1 0 1
=1 1 0
=0 0 1
=0 0 0
=0 0 00 0 1 0 1 1 0 0
carry 1
1
1
1
carry 1
Ex: Ex: (00011001)(00011001)22 - (00010011) - (00010011)22 = (…) = (…)22
Solution:Solution:
1 - 1 = 0
=0 - 1 1
=0 - 0 - 1 1
borrow 1
borrow 1
- 1 =1 - 0 0
=1 - 1 0
=0 - 0 0
=0 - 0 0
=0 - 0 00 0 0 0 0 1 1 0