arithmetic.2015

1UUEA4653 May 2015

Arithmetic for Computers

UEEA4653: Computer Architecture

Copyright Dr. Lai An Chow Arithmetic for Computers

2Major Goals

Introduce 2's complement numbers and their addition & subtraction

Explain the construction of a 32-bit arithmetic logic unit (ALU)

Show algorithms and implementations of multiplication and division


3Base, Representation and Value

Numbers can be represented in any base

Human: decimal (base 10); Computer: binary (base 2)

The value of the ith digit d is d x Basei

10012 = (1 x 23) + ( 0 x 22 ) + ( 0 x 21 ) + ( 1 x 20 ) 10 = 910

Bits are numbered 0, 1, 2, 3 from right to the left in a word

A MIPS word can represent 232 different 32-bit patterns (values)

Value of the 32-bit binary numbers =

(b31 x 231) + (b30 x 2

30) + + (b1 x 21) + (b0 x 2

0)

. . .28293031 0123

least significant bit (LSb)most significant bit (MSb)

. . .

2Copyright Dr. Lai An Chow Arithmetic for Computers

4Hexadecimal Representation

Why hexadecimal?

To avoid reading and writing long binary numbers

Hexadecimal (base 16) numbers are commonly used

Conversion to hexadecimal

Since base 16 is a power of 2, we can simply convert by replacing each group of four bits by a single hexadecimal digit, and vice versa

Example of hexadecimal-to-binary conversion: 0hex - 9hex for 00002 - 10012 ahex - fhex for 10102 11112

i.e. 0000 1010 0000 0101 0000 1100 0000 01102

= 0 a 0 5 0 c 0 6hex

= 0x0a050c06 # 0x to indicate it is a hexadecimal

= 16810291810


52's Complement Representation

All computers use 2's complement representation for signed numbers

Bit 31 is called the sign bit: (0 for non-negative, 1 for negative)

The positive half uses the same representation as before

The negative half uses conversion illustrated below:

Largest integer represented by a MIPS word:0111 1111 1111 1111 1111 1111 1111 11112 = (2

31 1)10 = 2,147,483,64710

Smallest integer represented by a MIPS word:1000 0000 0000 0000 0000 0000 0000 00002 = -2

3110 = -2,147,483,64810

Immediate part for lw, sw & addi are represented in 2s complement

0000 0000 0000 0000 0000 0000 0000 01102 = 610

1111 1111 1111 1111 1111 1111 1111 10012 = -710

1111 1111 1111 1111 1111 1111 1111 10102 = -610

i) Invert bits to get 1s complement

ii) Add 1 to get 2s complement


6Signed and Unsigned Numbers

Signed numbers

negative or non-negative integers, e.g. int in C/C++

Unsigned numbers

non-negative integers, e.g. unsigned int in C/C++

Operations for unsigned numbers

Comparison:

sltu (set on less than unsigned), sltiu

Arithmetic:

addu, subu (add/subtract unsigned)

Treat values of all registers as non-negative

addiu (add unsigned immediate)

The 16-bit immediate is treated as unsigned

(range: 0 > (216 1) = 65535)

addi (add signed immediate); range: -32768 -> +32767

Load:

lbu (load byte unsigned), lhu (load half unsigned)


7Signed vs. Unsigned Comparison

$s0 1111 1111 1111 1111 1111 1111 1111 11112

$s1 0000 0000 0000 0000 0000 0000 0000 00012

What are the values in registers $t0 and $t1 in the examples below?

slt $t0, $s0, $s1 # signed comparison

$s0 = -110, $s1 = 110, $t0 = 1

sltu $t1, $s0, $s1 # unsigned comparison

$s0 = 429496729510, $s1 = 110, $t1 = 0


8Sign Extension

Why sign extension?

e.g. lb $t0, 0($s0) # load a 8-bit signed number to 32-bit register

Bits 0~7 of $t0 will contain the byte value stored at 0($s0)

If the byte is a negative number, what happens to bits 8~24 of $t0?

Conversion of n-bit binary signed numbers into m-bit numbers (m > n)

Done by filling the leftmost bits (n-th ~ (m-1)-th) with the sign bit

For example:

2 (16 bits -> 32 bits):0000 0000 0000 0010 -> 0000 0000 0000 0000 0000 0000 0000 0010

-2 (16 bits -> 32 bits): 1111 1111 1111 1110 -> 1111 1111 1111 1111 1111 1111 1111 1110

If the immediate in the addi instruction = 1111 1111 1111 1110, the sign is extended as shown above before the ALU starts addition

For unsigned addition operation addiu, sign is not extended and 65534 (why this value?) is used in the addition


9Addition and Subtraction

Addition

Digits are added bit by bit from right to left, with carriespassed to the next digit to the left

Subtraction

Subtraction uses addition

The appropriate operand is negated before being added to the other operand

Overflow

The result is too large to fit into a word


10Examples

Addition (7 + 6 = 13):

0000 0000 0000 0000 0000 0000 0000 01112

= 710

+ 0000 0000 0000 0000 0000 0000 0000 01102

= 610

= 0000 0000 0000 0000 0000 0000 0000 11012

= 1310

Subtraction (7 - 6 = 1):

0000 0000 0000 0000 0000 0000 0000 01112

= 710

+ 1111 1111 1111 1111 1111 1111 1111 10102

= -610

= 0000 0000 0000 0000 0000 0000 0000 00012

= 110

1


11Examples

Addition (1073741824 + 1073741824 = 2147483648):

0100 0000 0000 0000 0000 0000 0000 00002

= 107374182410

+ 0100 0000 0000 0000 0000 0000 0000 00002

= 107374182410

= 1000 0000 0000 0000 0000 0000 0000 00002

214748364810

if considering MSb a sign bit

but, it means -214748364810


12

Overflow condition

Detecting Overflow

Addition (X + Y)

No overflow occurs when:

X and Y are of different signs

Overflow occurs when:

X and Y are of the same sign

But, X + Y is represented in a different sign

Subtraction (X - Y)

No overflow occurs when:

X and Y are of the same sign

Overflow occurs when:

X and Y are of different signs

But, X - Y is represented in a different sign from X

Operation Sign Bit of X Sign Bit of Y Sign Bit of Result

X + Y 0 0 1

X + Y 1 1 0

X Y 0 1 1

X Y 1 0 0


13Effects of Overflow

MIPS detects overflow with an exception (also called an interrupt)

Exceptions occur when unscheduled events disrupt program execution

Some instructions are designed to cause exceptions on overflow

e.g. add, addi and sub cause exceptions on overflow

But, addu, addiu and subu do not cause exception on overflow;

programmers are responsible for using them correctly

When an overflow exception occurs

Control jumps to a predefined address (code) to handle the exception

The interrupted address is saved to EPC for possible resumption

EPC = exception program counter; a special register

MIPS software return to the offending instruction via jump register


14

2. Arithmetic Logic Unit


15Constructing an Arithmetic Logic Unit

The arithmetic logic unit (ALU) of a computer is the hardware component that performs:

Arithmetic operations (like addition and subtraction)

Logical operations (like AND and OR)

Control Unit

Registers& Cache

ALU

Processor


16Universal Representation

Knowing what is exactly inside a 32-bits ALU, from now on we will use the universal symbol for a complete ALU as follows:

ALU

a

b

ALU operation

CarryOu

ResultZero

Overflow

t

AND000

OR001

ADD010

SUB110

SLT111

OperationALU Control lines


17Constructing an Arithmetic Logic Unit (contd)

Since a word in MIPS is 32 bits wide, we need a 32-bit ALU

Ideally, can build a 32-bit ALU by connecting 32 1-bit ALUs together

1-bit logical unit for AND and OR:

A multiplexor selects the appropriate result depending on the operation specified

b

0

1

Result

Operation

a


181-Bit Full Adder

An adder must have

Two inputs (bits) for the operands

A single-bit output for the sum

Also, must be a second output to pass on the carry, called carry-out

Carry-out becomes the carry-in to the neighbouring adder

1-bit full adder is also called a (3, 2) adder (3 inputs and 2 outputs)

(1) (1) (0) (carries)

0 1 1 1

0 1 1 0_____

1 (1)1 (1)0 (0)1

Sum

CarryIn

CarryOut

a

b


19Truth Table and Logic Equations for 1-Bit Adder

Truth table:

Logic equations:

Inputs OutputsComments

a b CarryIn CarryOut SumOut0 0 0 0 0 0 + 0 + 0 = 0020 0 1 0 1 0 + 0 + 1 = 0120 1 0 0 1 0 + 1 + 0 = 0120 1 1 1 0 0 + 1 + 1 = 1021 0 0 0 1 1 + 0 + 0 = 0121 0 1 1 0 1 + 0 + 1 = 1021 1 0 1 0 1 + 1 + 0 = 1021 1 1 1 1 1 + 1 + 1 = 112

)ba()CarryIna()CarryInb(

)CarryInba()ba()CarryIna()CarryInb(CarryOut

)CarryInba(

)CarryInba()CarryInba()CarryInba(SumOut


20Hardware Implementation of 1-Bit Adder

SumOut bit: (It is left as an exercise)

)ba()CarryIna()CarryInb(

)CarryInba()ba()CarryIna()CarryInb(CarryOut

b

CarryOut

a

CarryIn


211-Bit ALU (AND, OR, and Addition)

3 in 1 building block

Use the Operation bits to decide what to carry out

Operation = 0, do AND

Operation = 1, do OR

Operation = 2, do addition

b

0

2

Result

Operation

a

1

CarryIn

CarryOut


2232-Bit ALU

Ripple carry organization of a 32-bit ALU constructed from 32 1-bit ALUs:

A single carry out of the least significant bit (Result0) could ripple all the way through the adders, causing a carry out of the most significant bit (Result31)

There exist more efficient implementations (based on the carry lookahead idea to be explained later)

Result31

a31

b31

Result0

CarryIn

a0

b0

Result1

a1

b1

Result2

a2

b2

Operation

ALU0

CarryIn

CarryOut

ALU1

CarryIn

CarryOut

ALU2

CarryIn

CarryOut

ALU31

CarryIn


23Subtraction

Subtraction is the same as adding the negated operand

By doing so, an adder can be used for both addition and subtraction

A 2:1 multiplexor is used to choose between

an operand (for addition) and

its negative version (for subtraction)

Shortcut for negating a 2's complement number:

Invert each bit (to get the 1's complement representation)

Obtain the 2s complement by setting the ALU0s carry bit to 1


241-Bit ALU (AND, OR, Addition, and Subtraction)

Binvert: the selector input of a multiplexor to choose between addition and subtraction

To form a 32-bit ALU, connect 32 of these 1-bit ALUs

Set CarryIn input of the least significant bit (ALU0) to 1 for subtraction

0

2

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b


25Tailoring the ALU for MIPS

The 32-bit ALU being designed so far can perform add, sub, and, oroperations which constitute a large portion of MIPS instruction set

Two instructions not yet supported are: slt and beq

When we need to compare Rs to Rt

By definition of slt, if Rs < Rt

LSb of the output is set to 1

Otherwise, it is set to 0

How to implement it?

The comparison above is equivalent to testing if (Rs Rt) < 0

If (Rs Rt) is smaller than 0

MSb of the subtraction (Rs Rt) equals to 1 (means negative)

Otherwise, MSb of the subtraction equals to 0 Notice that the outcome of MSb is similar to the result of slt

We can copy the MSb of the subtraction to the LSb of slts output

slt can be done using two types of 1-bit ALUs in next slide


26Tailoring the ALU for MIPS (contd)

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection Overflow

1-bit ALU for bits 0 to 30 1-bit ALU for the MSB


2732-Bit ALU with (add, sub, AND, OR, slt)

The set signal is the MSb of the result of the subtraction, A B

It is passed to LSB

Result0 will equal to this set signal when operation = 3 (which means slt

instruction is being executed)

S e t

a 3 1

0

A L U 0 R e s u l t0

C a r ry In

a 0

R e s u l t1

a 1

0

R e s u l t2

a 2

0

O p e ra t io n

b 3 1

b 0

b 1

b 2

R e s u l t3 1

O v e r f lo w

B in v e r t

C a r r y In

L e s s

C a r ry In

C a r r yO u t

A L U 1

L e s s

C a r ry In

C a r r yO u t

A L U 2

L e s s

C a r ry In

C a r r yO u t

A L U 3 1

L e s s

C a r ry In

10


2832-Bit ALU with (add, sub, AND, OR, slt)

Finally, this adds a zero detector

For addition and AND/OR operations both Bnegate and CarryIn are 0 and for

subtract, they are both 1 so we combine them into a single line

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn


29Put All Together

ALU

a

b

ALU operation

CarryOu

ResultZero

Overflow

t

Set

a31

0

Result0a0

Result1a1

0

Result2a2

0

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0

Less

CarryIn

CarryOut

ALU1

Less

CarryIn

CarryOut

ALU2

Less

CarryIn

CarryOut

ALU31

Less

CarryIn

ALU operation

a

b

Result


30Comparing Two Unsigned Numbers

We can subtract as usual, but use the CarryOut31 to tell the result

If A < B

Example: A = 0111, B = 1000

A B = A + B = 0111 + 1000 (0111+1)

= 0 1111

If A > B

Example: A = 0111, B = 0110

A B = A + B = 0111 + 1010 (1001+1)

= 1 0001

If A = B

Example: A = 0111, B = 0111

A B = A + B = 0111 + 1001 (1000+1)

= 1 0000

If CarryOut31 is 0 then A < B, otherwise A >= B; slt is achieved

11


31Carry Lookahead

Using the ripple carry adder, the carry has to propagate from the LSb to the MSb in a sequential manner, passing through all the 32 1-bit adders one at a time. SLOW for time-critical hardware!

Key idea behind fast carry schemes without the ripple effect:

Substituting the latter into the former, we have:

All other CarryIn bits can also be expressed using CarryIn0

)0b0a()0CarryIn0a()0CarryIn0b(1CarryIn

)1b1a()1CarryIn1a()1CarryIn1b(2CarryIn

)1b1a(

)0CarryIn0b1b()0CarryIn0a1b()0b0a1b(

)0CarryIn0b1a()0CarryIn0a1a()0b0a1a(2CarryIn


32

3. Multiplication


33Multiplication

Multiplication is much more complicated than addition and subtraction

Paper-and-pencil example (100010 x 100110):

Multiplicand 1000

Multiplier 1001

1000

0000

0000

1000

Product 1001000

Observation:

Suppose we limit ourselves to using only digits 0 and 1

If we ignore the sign bits (i.e., unsigned numbers), multiplying an N-bit multiplicand with an M-bit multiplier gives a product that is at most N+M bits long

12


34Signed Multiplication

If the multiplicand or multiplier is negative, we first negate it to get a positive number

Use any one of the above methods to compute the product of two positive numbers

The product should be negated if the original signs of the operands disagree

Booths algorithm: a more efficient and elegant algorithm for the multiplication of signed numbers


35Motivation behind Booth Algorithm

Lets consider multiplying 00102 and 01102

Convention Booth

Multiplicand 0010 0010

Multiplier x 0110 0110

+ 0000 + 0000

+ 0010 - 0010

+ 0010 + 0000

+ 0000 + 0010

Product = 0001100 = 0001100

Keys

Shifts are much faster than adds

Algorithm looks at two bits of multiplier at a time from right to left

Take action only when the two-bit pair is either 01 or 10

Avoiding unnecessary additions to speed up the calculation

shift

subtract

shift

add


36Example to Explain the Math

Multiplier = 00111100

i.e. b1 = 2, b2 = 5

M x 00111100 = 22 *M + 23 *M + 24 *M + 25 *M

= 22 * (20 + 21 + 22 + 23) *M

= 22 * (24 - 1) *M

= (26 - 22) *M

Running the Booths algorithm by scanning multiplier from right to left

Iteration 0, pattern = 00







13


37Booths Algorithm

To find out why, do the math:

Consider a series of ones in the multiplier (from bit b1 to bit b2)

M: multiplicand; multiplying M with this series of ones results in

Prod = (2b1)* M + (2b1+1)* M + + (2b2)* M

= (2b2+12b1)* M

Number of additions, (b2-b1), in revised algorithm is reduced to one addition and one subtraction in Booths algorithm

Detailed algorithm:

We look at 2 bits at a time (current bit and previous one):

00: middle of a string of 0s; no arithmetic operation

01: end of a string of 1s; add M to the left half of product

10: start of a string of 1s; subtract M from the left half of product

11: middle of a string of 1s- no arithmetic operations

Previous bit is set to 0 for the first iteration to form a two-bit pattern


38Multiply in MIPS

Separate pair of 32-bit registers to contain 64-bit product, Hi and Lo

mult (multiply) and multu (multiply unsigned)

mult $s2, $s3 # Hi, Lo = $s2 x $s3

multu $s2, $s3 # Hi, Lo = $s2 x $s3

Both MIPS multiply instructions ignore overflow

No overflow if Hi is 0 for multu or the replicated sign of Lo for mult

Fetch the integer 32-bit product

mflo (move from lo) mflo $s1 # $s1 = Lo

mfhi (move from hi) mfhi $s1 # $s1 = Hi

mfhi can transfer Hi to a general-purpose register to test for overflow


39

4. Division

14


40Division

Division is the reciprocal operation of multiplication

Paper-and-pencil example (1001010ten / 1000ten):

1001 Quotient

Divisor 1000 1001010 Dividend

-1000000

0001010

0001010

0001010

-1000

10 Remainder

Dividend = Quotient x Divisor + Remainder

1001 Quotient


-1000000

0001010

0001010


41

1

Paper-and-pencil example (00001112 / 00102):

Quotient


00001110

-0010

00011100

-0010

00111000

-0010

00011000

00110000

-0010

0001 Remainder

Example

001


42Division Hardware

32-bit ALU

Two registers:

Divisor register: 32 bits

Remainder register: 64 bits

(right half also used for storing quotient)

Operations:

32-bit divisor is always subtracted from the left half of remainder register

The result is written back to the left half of the remainder register

The right half of the remainder register is initialized with the dividend

Left shift remainder register by one before starting

The new order of the operations in the loop is that the remainder register will be shifted left one time to many

Thus, final correction step: must right shift back only the remainder in the left half of the remainder register

Write

32 bits

64 bits

Shift left

Shift right

Remainder

32-bit ALU

Divisor

Control

test

15


43Division Algorithm Improved Version

Done. Shift left half of Remainder right 1 bit

Test Remainder

3a. Shift the Remainder register to the

left, setting the new rightmost bit to 1

32nd repetition?

Start

Remainder < 0

No: < 32 repetitions

Yes: 32 repetitions

3b. Restore the original value by adding

the Divisor register to the left half of the

Remainder register and place the sum

in the left half of the Remainder register.

Also shift the Remainder register to the

left, setting the new rightmost bit to 0

2. Subtract the Divisor register from the

left half of the Remainder register and

place the result in the left half of the

Remainder register

Remainder 0

1. Shift the Remainder register left 1 bit

>


44Example

Division of a 4-bit unsigned number (0111) by another one (0011)

Iteration Divisor (D) Remainder (R) Remark

0

0011

0000 0111 Initial state

0000 1110 R = R

16


46Divide in MIPS

div ('divide')

divu ('divide unsigned')

Examples:

div $s1, $s2 # Lo = $s1 / $s2; Hi = $s1 mod $s2

divu $s1, $s2 # Lo = $s1 / $s2; Hi = $s1 mod $s2


47MIPS Instructions for Floating-Point Operations

MIPS supports IEEE 754 single-precision and double-precision formats

Addition:

add.s ('addition, single'), add.d ('addition, double')

Subtraction:

sub.s ('subtraction, single'), sub.d ('subtraction, double')

Multiplication:

mul.s ('multiplication, single'), mul.d ('multiplication, double')

Division:

div.s ('division, single'), div.d ('division, double')

Comparison:

c.x.s ('comparison, single'), c.x.d ('comparison, double')

where x may be eq, neq, lt, le, gt, ge

Branch:

bclt ('branch, true'), bclf ('branch, false')


48Key Concepts to Remember

2's complement representation for signed numbers

A 32-bit ALU can be built by connecting 32 1-bit ALUs together

Subtraction makes use of addition

SLT makes use of subtraction

A multiplexor is used in an ALU to select appropriate result

Carry lookahead adders better than ripple carry adders

Multiplication: through a series of addition and shift operations

Division: through a series of subtraction and shift operations

Make sure you understand how the hardware algorithms work

Overflow (a type of exception)

A result of addition or subtraction

Detected by checking the signs of the operands and result

arithmetic.2015

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