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ARM and AVR32ARM and AVR32: Which one is better? : Which one is better?

SAMSUNG Software MembershipSAMSUNG Software MembershipSuwonSuwon

ChangChang--yeon, Cho. <[email protected]>yeon, Cho. <[email protected]>

Copyright Copyright ⓒⓒ 2007 by iprinceps2007 by iprincepsNo parts of this document may be reproduced in any form, in an eNo parts of this document may be reproduced in any form, in an electroniclectronicretrieval system or otherwise, without the prior written permissretrieval system or otherwise, without the prior written permission of the publisher.ion of the publisher.

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AbstractIntroductionARMAVR32ARM vs. AVR32References


AbstractAbstract

ARMBrief history of ARMThe characteristic of ARM

ArchitectureProgrammer’s Model

Why is ARM the most popular embedded microprocessor in the market?

AVR32What is the AVR32?The characteristic of AVR32

ArchitectureProgrammer’s Model

What are advantages when you choose AVR32?

ARM vs. AVR32Which one is better, ARM or AVR32?


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IntroductionIntroduction

ARMThe industry’s leading provider of 32-bit embedded RISC microprocessors with almost 75% of market. : It’s the most popular embedded microprocessor!There are many processors those implement ARM core in the Market.

PXA255, PXA270, S3C2440A, AT91 Series, TI TMS Series, etc.Since last year, processors those implement ARM11 core have appeared.

ARM has convenient develop environments and build tools.Were there any competitors?

AVR32Introduced to the Market just last year.Atmel’s first their own 32-bit processor.AVR32 has really many features those are interesting.Open-source support available.

Operating systems.Develop Environment.


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ARMARM

HistoryARM was introduced in the middle of 1980’s

1985. Acorn Computer Group develops the world’s first commercial RISC processor1991. the first embeddable RISC core: ARM61993. TI, Cirrus and Samsung license ARM, ARM7 core1995. Thumb architecture, StrongARM1996. ARM9TDMI family announced2002. ARM11 family announced

Architecture (Instruction set) Progression


ARMARM

The ARM Instruction Set ArchitectureThe ARM architecture provides support for the 32-bit ARM and 16-bit Thumb Instruction Set Architectures along with architecture extensions.

Extensions: Java acceleration, security, Intelligent Energy Manager, SIMD, and NEON technologies.ARMv5TE: In 1999, the ARMv5TE introduced along with ARM ‘Enhanced’ DSP instruction set extensions.ARMv5TEJ: In 2000, the ARMv5TEJ added the Jazelle extension to support Java acceleration.ARMv6: The ARMv6 architecture, announced in 2001, features improvements in many areas covering the memory system, improved exception handling and better support for multiprocessing environments. And the ARMv6 also includes media instructions to support Single Instruction Multiple Data (SIMD).ARMv7: the ARMv7 architecture includes Thumb-2 technology and the NEON technology.NEON: Media Acceleration Technology – designed to address the demands of next generation mobile handheld devices.Thumb-2: defining a new set of 32-bit instructions that execute alongside traditional 16-bit instructions in Thumb state – reduce the need for balancing ARM and Thumb codes.


ARMARM

Programmer’s ModelPipelines

ARM7 Pipelines

ARM9TDMI Pipelines

– Memory: Access memory area– Write: Store the result of processing to register

FETCH DECODE EXECUTE




ARMARM

Operating Modes

User and System mode share one bank of registersException mode: use their own registers

– FIQ mode has private R8 ~ R14.– the other modes have private R13 and R14.

Mode Description ID Comments

User Normal program execution mode usr restriction

System Privileged mode for operating system sys OS task

FIQ When a fast interrupt fiq High-speed ch.

IRQ When a normal interrupt irq

Supervisor Exception mode for operating system svc SWI

Abort When data or instruction prefetch abort abt Vir. Mem, MPro

Undef When an undefined instruction und HW Emulation


ARMARM

Registers – Total 37 registers exist.


ARMARM

Registers (Cont’d)Unbanked Registers: R0 ~ R7

– Same to all modesBanked Registers: R8 ~ R14

– R8 ~ R12: If simple interrupts FIQ can be very fast using only R8 ~ R12.

– R13 ~ R14R13: Usually used for Stack Pointer (SP)R14: Usually used for Link Register (LR)

Program Counter: R15Program Status Register


ARMARM

ExceptionsException Type Priority Mode Vector High Vector

0x00000000 0xFFFF00000xFFFF00040xFFFF00080xFFFF000C0xFFFF0010

Reserved 0x00000014 0xFFFF00140xFFFF00180xFFFF001C

0x000000040x000000080x0000000C

Data Abort 2 Abort 0x00000010

IRQ 4 IRQ 0x00000018FIQ 3 FIQ 0x0000001C

SupervisorUndefinedSupervisor

Abort

Reset 1Undefined Instruction 6

SWI 6Prefetch Abort 5

R14_<mode> = return addressSPSR_<mode> = CPSRCPSR[4:0] = exception mode

numberCPSR[5] = 0 // in ARM stateIf <mode> == reset or FIQ

CPSR[6] = 1 // disable FIQCPSR[7] = 1 // disable IRQPC = vector address

CPSR = SPSR_<mode>PC = R14_<mode>

ByMOVS|SUBS PC, XX orLDM with Restore CPSR

When an exception occurs To return from exception


ARMARM

Why is ARM the most popular embedded microprocessor in the market?

Low power consumptionIn the case of embedded system or handheld device, power consumption is very important problem.ARM microprocessor solutions offer the industries lowest power consumption and MIPS per watt.For example, STR7 family with ARM7TDMI: 10uA in the Stand-by mode

Low cost of siliconARM processors and other IP products make efficient use of silicon and memory to align with the economics of wireless devices.

Core performance1MHz to 1GHz with architectural performance

Wide supportA wide range of OS, Middleware and tools support an extensive choice of multimedia codec solutions optimized for ARM processors, are available from the ARM Connected Community.


ARMARM

Develop Environments and SupportsDevelop Environments

Embedded-ICE debugRVDS, ADS, Keil, IAR, etc.GNU Toolchain for ARM

SupportsOpen source: Linux, eCos, etc.

Were there any competitors?Alchemy AU1200

iStation V43


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AVR32AVR32

What is the AVR3232-bit load/store AVR32 RISC architecture15 general-purpose 32bit registers32-bit stack pointer, Program Counter and Link Register reside in register fileFully orthogonal instruction setPipelined architecture allows one instruction per clock cycle for most instructionsShadowed interrupt context for INT3 and multiple interrupt priority levelsPrivileged and unprivileged modes enabling efficient and secure Operating SystemsFull MMU allows for operating systems with memory protectionInstruction and data caches


AVR32AVR32

AVR32Architecture

NOT binary compatible with earlier AVR architectureIn order to achieve high code density, the instruction format is flexible providing both compact instructions with 16 bits length and extended 32-bit instructionsCompact and extended instruction can be FREELY mixed in the instruction streamIn order to reduce code size to a minimum, some instructions have multiple addressing modes.Frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands.

– The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle

Load/Store instructions have several different formats in order to reduce code size and speed up execution

– Load/store to an address specified by a pointer register– Load/store to an address specified by a pointer register with postincrement,

predecrement, and displacement– Load/store to an address specified by a small immediate (direct addressing within a

small page)– Load/store to an address specified by a pointer register and an index register


AVR32AVR32

Architecture (Cont’d)Event handling

– The different event sources have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously.

– Pending events of a higher priority class may preempt handling of ongoing events of a lower priority class

– Each priority class has dedicated registers to keep the return address and status register thereby removing the need to perform time-consuming memory operations to save information

– 4 level external interruptsMicroarchitectures

– AVR32A: be targeted at cost-sensitive, lower-end applications like smaller microcontrollers.

– Does not provide dedicated hardware registers for shadowing of register file registers in interrupt context and hardware registers for the return registers and return status register

All information are stored on the system stack– AVR32B: be targeted at applications where interrupt latency is important.– Implements dedicated registers to hold the status register and return address for

interrupts, exceptions and supervisor calls this information does not need to be written to the stack, and latency is therefore reduced

– The INT0 to INT3 contexts may have dedicated versions of the registers in the register file


AVR32AVR32

Programmer’s ModelRegister file configuration

The AVR32B architecture specifies that the exception contexts may have a different number of shadowed registers in different implementations. The following shadow model is used in AVR32 AP.


AVR32AVR32

Status register configurationThe Status Register (SR) is splitted into two halfwords, one upper and one lower. The lower word contains the C, Z, N, V and Q condition code flags and the R, T and L bits, while the upper halfword contains information about the mode and state the processor executes in.


AVR32AVR32

Status register configuration (Cont’d)D: Debug state

– The processor is in debug state when this bit is set. The bit is cleared at reset and should only be modified by debug hardware.

M2, M1, M0: Execution Mode

R: Java Register Remap– When this bit is set, the addresses of the registers in the register file is dynamically

changed.T: Scratch bit

– Not used by any instruction, but can be manipulated by application as a scratchpad bit. This bit is not cleared by reset.


AVR32AVR32

Status register configuration (Cont’d)Q: Saturation flag

– The saturation flag indicates that a saturating arithmetic operation overflowed. The flag is sticky and once set it has to be manually cleared by a csrf instruction after the desired action has been taken.

L: Lock flag– Used by the conditional store instruction. Used to support atomical memory access.

Automatically cleared by rete. This bit is cleared after reset.

Configuration RegistersConfiguration registers are used to inform applications and operating systems about the setup and configuration of the processor on which it is running.


AVR32AVR32

PipelineOverview

– AVR32 AP is pipelined processor with 7 pipeline stages. The pipeline has 3 sub pipes, namely the Multiply pipe, the Execute pipe and the Data pipe. These pipelines may execute different instructions in parallel. Instructions are issued in order, but may complete out of order since the sub pipes may be stalled individually, and certain operations may use a sub pipe for several clock cycles.

– IF1, IF2: Instruction Fetch 1 and 2– ID: Instruction Decode, IS: Instruction Issue– A1, A2: ALU stage 1 and 2, M1, M2: Multiply stage 1 and 2– DA: Data Address calculation stage, D: Data cache access– WB: Write back


AVR32AVR32

PipelinePrefetch Unit

– responsible for feeding instructions to the decode unit.– fetches 32 bits at a time from the instruction cache and places them in a FIFO prefetch

bufferDecode Unit

– generates the necessary signals in order for the instruction to execute correctly– ID stage: accepts one instruction each clock cycle from the prefetch unit

If the instruction cannot be decoded, an illegal instruction or unimplemented instructionexception is issued

– IS stage: performs register file reads and keeps track of data hazards in the pipelineIf hazards exist, pipelines are frozen as needed in order to resolve the hazard

ALU Pipeline– performs most of the data manipulation instructions, like arithmetical and logical

operations– A1 Stage: target address calculation and condition check, condition code checking for

conditional instructions, address calculation for indexed memory accesses, write back address calculation for LS pipeline and all flag setting for arithmetical and logical instructions.

– A2 Stage: the saturation needed by satadd and satsub and the operation and flag setting needed by satrnds, satrndu, sats and satu.


AVR32AVR32

Pipeline (Cont’d)Multiply Pipeline

– All multiply instructions execute in the multiply pipeline. – contains a 32 by 16 multiplier array, and 16x16 and 32x16 multiplications therefore

have an issue latency of one cycle.– Multiplication of 32 by 32 bits require two iterations through the multiplier array, and

therefore needs several cycles to complete. – Additional cycles may be needed if an accumulation is to be performed. This will stall

the multiply pipeline until the instruction is complete.Load-store Pipeline

– can read or write up to two registers per clock cycle, if the data is 64-bit aligned. – contains hardware for performing load and store multiple instructions decoupled from

the rest of the core.


AVR32AVR32

Event HandlingAn event can be either an interrupt or an exception.Each pipeline stage has a pipeline register that holds the exception requests associated with the instruction in that pipeline stage.Detect

– D stage: all data-address related exceptions– All other exceptions and interrupts are detected in the A1 stage

Event priority– If several instructions trigger events, the instruction furthest down the pipeline is

serviced first, even if upstream instructions have pending events of higher priority.– If this instruction has several pending events, the event with the highest priority is

serviced first. After this event has been serviced, all pending events are cleared and the instruction is restarted.

Entry points for events– Several different event handler entry points exists. For AVR32B, the reset routine

entry address is always fixed to 0xA000_0000. This address resides in unmapped, uncached space in order to ensure well-defined resets.

– If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented next page.

– If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction.


AVR32AVR32

Event Handling (Cont’d)Priority and handler addresses for events


AVR32AVR32

Develop Environments and SupportsDevelopment Environments

IAR Embedded Work bench

Atmel JTAGICEmkIIGNU Compiler Collection

– deb http://www.atmel.no/beta_ware/avr32/ubuntu/breezy binary/– development environment for AVR32 standalone and AVR32 Linux

SupportsOpen source: U-Boot, Linux 2.6.18 or later, eCos, etc.Development Kit

http://www.atmel.no/beta_ware/avr32/ubuntu/breezy binary/


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ARM vs. AVR32ARM vs. AVR32

ARM vs. AVR32AVR32 Block Diagram



AVR32 AP multimedia Benchmarks

QVGA@30fps MPEG4 Decode: 75MHz CPU frequencyMP3 Audio: 15MHz CPU frequencyOutperforms ARM9 3 times

– video decode



EEMBC – Generic BenchmarksEmbedded Microcontroller Benchmarks ConsortiumBenchmark of architectures, not devices



EEMBC – Generic Benchmarks (Cont’d)Code density

– Lower power consumption– Lower RAM requirement



AP7000 ARM9 Competitive Overview



ARM11?

Microsoft ZUNEiMx.31 needs 0.65mm via it cannot be made by drill.Cost increase

Which one is better, ARM or AVR32?


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ReferencesReferences

DocumentsFrom Atmel website (http://www.atmel.com)

AVR32 AP Technical Reference ManualAVR32 Architecture DocumentAP32AP7000 DatasheetATSTK1000 User’s GuideAVR32 ASIA 2006 DRAFT

From CD included in STK1000AVR32 BSP User’s GuideLinuxTool-chain