ARM Introduction

Alberto Bosiobosio@lirmm.fr

Univeristé de Montpellier

October 23, 2017

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Processor

Instruction set architecture (ISA): is the set of processordesign techniques used to implement the instruction work flowon hardware. In more practical words, ISA tells you that howyour processor going to process your program instructions.

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RISC VS CISC

CISC: A complex instruction set computer, is a computerwhere single instructions can execute several low-leveloperations (such as a load from memory, an arithmeticoperation, and a memory store) or are capable of multi-stepoperations or addressing modes within single instructions.RISC: A reduced instruction set computer is a computer whichonly use simple instructions that can be divide into multipleinstructions which perform low-level operation within singleclock cycle.

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RISC VS CISC

CISC: A complex instruction set computer, is a computerwhere single instructions can execute several low-leveloperations (such as a load from memory, an arithmeticoperation, and a memory store) or are capable of multi-stepoperations or addressing modes within single instructions.RISC: A reduced instruction set computer is a computer whichonly use simple instructions that can be divide into multipleinstructions which perform low-level operation within singleclock cycle.

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RISC VS CISC

Example

Let we take an example of multiplying two numbers:I A = A * B; /* this is C statement */

CISC solution:I MULT A,B /* this is assembly statement */

RISC solution:I LOAD R1, A /* this is assembly statement */I LOAD R2,B /* this is assembly statement */I PROD A, B /* this is assembly statement */I STORE R3, A /* this is assembly statement */

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ARM

Advanced RISC Machines

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ARM

Advanced RISC Machines

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Case Study

STM32 Cortex-M4

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Case Study

Programmer Model

Processor Modes:I Thread mode: Used to execute application software (default

mode)I Handler mode: Used to handle exceptions (returns to Thread

mode when it has finished exception processing)Privilege Levels:

I Unprivileged: Some Limitations (not all theregisters/instructions are accessible)

I Privileged: all instructions and all resources are accessible.

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Registers Bank

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Registers Bank

General-purpose registers:I R0-R12 are 32-bit general-purpose registers for data operationsI Only low level registers can be use immediate values

The stack pointer, SP or R13:I The stack is typically used to store temporary values.I It is normal to store the contents of any registers a function is

going to use on the stack on entry to a subroutine. This leavesthe register free for use during the function. The routine canthen recover the register values from the stack

The Link Register, LR or R14I The Link Register, LR or R14

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Registers Bank

Program status register

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Programmer Model

Memory Model

The processor has a fixed memory map that provides up to 4GB of addressable memory.The 4GB are divided into sub-regions:

I Each region is given for a particular usageI Easy for portability

Data Type:I 32-bit wordsI 16-bit halfwordsI 8-bit bytes

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Programmer Model

Memory Model

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Programmer Model

Memory Model

Code: program instructions;SRAM: global variables;Peripheral: on-hip peripheral like AHB, APB peripheralsExternal RAM: mainly used for DDR or FLASH externalmemoryExternal device: example SD card or USB portPrivate Peripheral: example interrupt vector table

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Programming In Assembler

Prerequisites: C language!

#inc lude <s t r i n g . h>#inc lude <s t d i o . h>void main ( i n t argc , char ∗∗ a rgv ) {

i n t count =0;i n t i ;fo r ( i =1; i<argc ; i++)

i f ( s t r l e n ( a rgv [ i ])> argc )count++;

p r i n t f ( "%d" , count ) ;}

What does the program prints as a function of the programarguments?