Embedded System Design Center

Sai Kumar Devulapalli

ARM7TDMI MicroprocessorARM7TDMI Microprocessor

Branching and Exception HandlingBranching and Exception Handling

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ObjectivesObjectives

• To understand different operating modes of ARM Processor.• To understand how exceptions are handled in ARM Processor

and how to return from exception• To know exception priority and vector addresses.• To learn direct manipulation of status registers.• To understand branch instruction, subroutine handling and

changing between ARM and THUMB mode with branching.• To learn how high-level constructs like if, switch and for

statements can be implemented in ARM assembly code.

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ARM ExceptionsExceptions are used to handle unexpected events which may arise

due to • Externally generated interrupts • An attempt by the processor to execute an undefined instruction• Accessing privileged operating system functions

ARM Exceptions Classification Exception generated as direct effect of instruction execution

• SWI, Undefined, prefetch aborts Exception generated as a side-effect of an instruction

• Data aborts Exception generated externally, unrelated to program execution

• Reset, IRQ and FIQ

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Processor Modes

The ARM has six operating modes:• User (unprivileged mode under which most tasks run)• Fast interrupt request Mode-FIQ (entered when a high

priority (fast) interrupt is raised)• Interrupt Mode-IRQ (entered when a low priority (normal)

interrupt is raised)• Supervisor Mode-SVC (entered on reset and when a

Software Interrupt instruction is executed)• Abort Mode- ABT (used to handle memory access violations)• Undefined Mode-UND (used to handle undefined

instructions)

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Processor Modes

• All modes except User mode are referred to as privileged modes. They have full access to system resources and can change mode freely.

• Modes other than User mode are entered to service exceptions, or to access privileged resources. Five of them are known as Exception modes:

IRQ, FIQ, Supervisor, Abort, Undefined Modes• Applications that require task protection usually execute in

User mode.• Some embedded applications might run entirely in Supervisor

or System modes. It is intended for use by Operating system with the Exception Mode.

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Use of modes and registers by exceptions

Typically,an application runs in user mode,but servicing exception requires privileged(i.e., non-user mode) operation.

An exception changes the processor mode and this in turn means that each exception handler has access to a certain subset of the banked registers:

• Its own r13 or stack pointer(sp_mode)• Its own r14 or Link Register(lr_mode)• Its own Saved Program Status Register(spsr_mode).In case of a FIQ,each exception handler has to five more general

purpose registers(r8_FIQ to r12_FIQ).

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Exception Priorities

Vector address Exception Type Exception mode Priority(1=high,6=low)

0x0 Reset Supervisor(SVC) 1

0x4 Undefined Instruction

Undef 6

0x8 Software Interrupt(SWI)

Supervisor(SVC) 6

0xC Prefetch Abort Abort 5

0x10 Data Abort Abort 2

0x14 Reserved Not applicable Not applicable

0x18 Interrupt(IRQ) Interrupt(IRQ) 4

0x1C Fast Interrupt(FIQ)

Fast Interrupt(FIQ)

3

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Operating modes

CPSR[4:0]

Mode Use Registers

10000 User Normal user code user

10001 FIQ Processing faster interrupts _fiq

10010 IRQ Processing standard interrupts _irq

10011 SVC Processing software interrupts _svc

10111 Abort Processing memory faults _abt

11011 Undef Handling undefined instructions _und

11111 System Running privileged operating system tasks user

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The Current Program Status Register(CPSR)

• The CPSR holds:– copies of the Arithmetic Logic Unit (ALU) status flags– the current processor mode– interrupt disable flags.

• The ALU status flags in the CPSR are used to determine whether conditional instructions are executed or not. On Thumb-capable processors, the CPSR also holds the current processor state (ARM or Thumb).

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Saved Program Status Registers (SPSRs)

• The SPSRs are used to store the CPSR when an exception is taken.One SPSR is accessible in each of the exception-handling modes.

• User mode and System mode do not have an SPSR because they are not exception handling modes.

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ARM Register OrganisationARM General registers and Program Counter

ARM Program Status Registers

r15 (pc)

r14 (lr)

r13 (sp)

r14_svc

r13_svc

r14_irq

r13_irq

r14_abt

r13_abt

r14_undef

r13_undef

User32 / System FIQ32 Supervisor32 Abort32 IRQ32 Undefined32

cpsr

sprsr_fiqsprsr_fiqsprsr_fiq spsr_abtspsr_svcsprsr_fiqsprsr_fiqspsr_fiq sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_irq

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc)

cpsrcpsrcpsrcpsrcpsr

r14_fiq

r13_fiq

r12_fiq

r10_fiq

r11_fiq

r9_fiq

r8_fiq

sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_undef

* Shaded indicates Banked Registers

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THUMB Register Organisation

Thumb General registers and Program Counter

Thumb Program Status Registers

User / System FIQ Supervisor Abort IRQ Undefined

CPSR

sprsr_fiqsprsr_fiqsprsr_fiq SPSR_ABTSPSR_SVCsprsr_fiqsprsr_fiqSPSR_FIQ sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqSPSR_IRQ

CPSRCPSRCPSRCPSRCPSR

sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqSPSR _UND

PC

LR

SP

r7

r4

r5

r2

r1

r0

r3

r6

PC_ FIQ

r7

r4

r5

r2

r1

r0

r3

r6

LR_ FIQ

SP_FIQ

PC_ SVC

r7

r4

r5

r2

r1

r0

r3

r6

LR_ SVC

SP_SVC

PC_ ABT

r7

r4

r5

r2

r1

r0

r3

r6

LR_ ABT

SP_ABT

PC_ IRQ

r7

r4

r5

r2

r1

r0

r3

r6

LR_ IRQ

SP_IRQ

PC_ UND

r7

r4

r5

r2

r1

r0

r3

r6

LR_ UND

SP_UND

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Handling the Exception

Save CPU & Register state

Restore CPU & register state

Handle the exception

Thumb codedapplication

ARM coded veneers

Switch to ARM state

Switch to ThumbState and return

Switch toThumb state

Switch toARM state

Entry Veneer

Exit veneer

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When an exception occurs, the core:• Copies CPSR into SPSR_<mode>• Sets appropriate CPSR bits

If core implements ARM Architecture 4T and is currently in Thumb state, then

ARM state is entered. Mode field bits are changed to indicate new mode. Disables IRQ and in case of FIQ disables further fast

interrupts.• Maps in appropriate banked registers• Stores the “return address” in LR_<mode>• Sets PC to vector address

Processor response to an Exception

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To return, exception handler needs to:• Restore CPSR from SPSR_<mode>• Restore PC from LR_<mode>

Above two operations cannot be carried out simultaneously.• If CPSR is restored first – mode gets changed – r14 is no

longer accessible.• If PC is restored first – exception handler looses control

and cannot do restoration of CPSR.

Returning from an Exception Handler

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With return address in R14

To return from a SWI or undefined instruction trap use:• MOVS PC, R14

To return from an IRQ, FIQ or prefetch abort use:• SUBS PC, R14, #4

To return from a data abort to retry the data access use:• SUBS PC, R14, #8

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Adjustment to return address • IRQ and FIQ must return one instruction early in order to

execute the instruction that was “usurped” for the exception entry.

• Prefetch abort must return one instruction early to execute the instruction that had caused a memory fault when first requested.

• Data abort must return two instructions early to retry the data transfer instruction, which was the instruction before the one usurped for exception entry.

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Return address in Stack

• Handler can save all registers along with return address on to stack

STMFD sp!,{r0-r12, lr} ; stack all registers........ ; and the return address........

• In that case the restoration of user registers and PC can be implemented with a single multiple register transfer instruction such as:

LDMFD sp!,{r0-r12, pc}^ ; load all the registers; and return automatically

• However in order to adjust the return mechanism r14 must be adjusted before being saved onto the stack.

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FIQ MODE

• supports data transfer or channel process.• externally generated by taking the nFIQ input LOW.• FIQ may be disabled by setting the CPSR’s F flag

ABORT MODE• indicates that the current memory access cannot be completed.• There are two types of abort:

Prefetch abort -occurs during an instruction prefetch.Data abort -occurs during a data access.

The exception will not be taken until the instruction reaches the head of the pipeline.

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Supervisor Mode

The Supervisor Mode is entered in following situations.• Power on Reset• On reset• When SWI (Software Interrupt) instruction is executed

Undefined Mode• used to extend either the THUMB or ARM instruction

set by software emulation.• After emulating the failed instruction, the trap handler-

restores the CPSR and returns to the instruction following the undefined instruction.

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The Program Status Registers (CPSR and SPSRs)

Condition Code FlagsN = Negative result from ALU flag.Z = Zero result from ALU flag.C = ALU operation Carried outV = ALU operation oVerflowed

Mode Bits M[4:0] define the processor mode.

Interrupt Disable bits. I = 1, disables the IRQ. F = 1, disables the FIQ.

T Bit (Architecture v4T only) T = 0, Processor in ARM state T = 1, Processor in Thumb state

Copies of the ALU status flags (latched if theinstruction has the "S" bit set).

ModeN Z C V

2831 8 4 0

I F T

Condition bits

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Condition Flags

Flag Logical Instruction Arithmetic Instruction

Negative (N=‘1’)

No meaning Bit 31 of the result has been set. Indicates a negative number in signed operations

Zero (Z=‘1’)

Result is all zeroes Result of operation was zero

Carry (C=‘1’)

After Shift operation ‘1’ was left in carry flag

Result was greater than 32 bits

oVerflow (V=‘1’)

No meaning Result was greater than 31 bits Indicates a possible corruption of the sign bit in signed numbers

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PSR Transfer Instructions

MRS and MSR allow contents of CPSR/SPSR to be transferred from appropriate status register to a general purpose register.

• All of status register, or just the flags, can be transferred.Syntax:

• MRS{<cond>} Rd,<psr> ; Rd = <psr>• MSR{<cond>} <psr>,Rm ; <psr> = Rm• MSR{<cond>} <psrf>,Rm ; <psrf> = Rm

where• <psr> = CPSR, CPSR_all, SPSR or SPSR_all• <psrf> = CPSR_flg or SPSR_flg

Also an immediate form• MSR{<cond>} <psrf>,#Immediate• This immediate must be a 32-bit immediate, of which the 4

most significant bits are written to the flag bits.

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Using MRS and MSRCurrently reserved bits, may be used in future, therefore:

• they must be preserved when altering PSR• the value they return must not be relied upon when testing other bits.

Thus read-modify-write strategy must be followed when modifying any PSR:

• Transfer PSR to register using MRS• Modify relevant bits• Transfer updated value back to PSR using MSR

* Note:• In User Mode, all bits can be read but only the flag bits can be written

to.

ModeN Z C V

2831 8 4 0

I F T

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PSR Bit Sections

Format: MSR {<cond>} CPSR_f |SPSR_f, Rm|immediate _f could be f, s, e, c which apply field mask

Note: status field and extension fields are unused on current ARMs.

31 28 25 24 16 15 8 7 5 0N Z C V I F T mode

flags field (f) status field (s) extension field (e) control field(c)

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Conditional Execution

• Most instruction sets only allow branches to be executed conditionally.

• However by reusing the condition evaluation hardware, ARM effectively increases number of instructions.

• All instructions contain a condition field which determines whether the CPU will execute them.

• Non-executed instructions soak up 1 cycle.– Still have to complete cycle so as to allow fetching and

decoding of following instructions.• This removes the need for many branches, which stall the pipeline

(3 cycles to refill).• Allows very dense in-line code, without branches.• The Time penalty of not executing several conditional

instructions is frequently less than overhead of the branch or subroutine call that would otherwise be needed.

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The Condition Field

0000 = EQ - Z set (equal)

0001 = NE - Z clear (not equal)

0010 = HS / CS - C set (unsigned higher or same)

0011 = LO / CC - C clear (unsigned lower)

0100 = MI -N set (negative)

0101 = PL - N clear (positive or zero)

0110 = VS - V set (overflow)

0111 = VC - V clear (no overflow)

1000 = HI - C set and Z clear (unsigned higher)

1001 = LS - C clear or Z (set unsigned lower or same)

1010 = GE - N set and V set, or N clear and V clear (>or =)

1011 = LT - N set and V clear, or N clear and V set (>)

1100 = GT - Z clear, and either N set and V set, or N clear and V set (>)

1101 = LE - Z set, or N set and V clear,or N clear and V set (<, or =)

1110 = AL - always

1111 = NV - reserved.

2831 24 20 16 12 8 4 0

Cond

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Branch : B{<cond>} labelBranch with Link : BL{<cond>} sub_routine_label

The offset for branch instructions is calculated by the assembler:• By taking the difference between the branch instruction and

the target address minus 8 (to allow for the pipeline).• This gives a 26 bit offset which is right shifted 2 bits (as the

bottom two bits are always zero as instructions are word – aligned) and stored into the instruction encoding.

• This gives a range of ± 32 Mbytes.

Branch instructions

2831 24 0

Cond 1 0 1 L Offset

Condition field

Link bit 0 = Branch1 = Branch with link

232527

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Branch instructions• When executing the instruction, the processor:

• shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.

• Execution then continues from the new PC, once the pipeline has been refilled.

• The "Branch with link" instruction implements a subroutine call by writing PC-4 into the LR of the current bank.

• i.e. the address of the next instruction following the branch with link (allowing for the pipeline).

• To return from subroutine, simply need to restore the PC from the LR:• MOV pc, lr• Again, pipeline has to refill before execution continues.

• The "Branch" instruction does not affect LR.• Note: Architecture 4T offers a further ARM branch instruction, BX

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BX Instruction

BX : Branch and Exchange• Instruction branches to an address held in register Rm with an

optional switch to Thumb execution. • Branch target address is the value of register Rm, with bit[0]

forced to zero• Mode of branch target is chosen by setting the CPSR T bit to

bit[0] of ARM.

Syntax: BX { <cond>} <Rm>

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BX Instruction

SBO : Should be 0 (Zero) OnlyRm : Register [31 : 1] which will be transferred to PC. It

is essential that the address should be word aligned.

31 28 27 20 19 16 15 12 11 8 7 4 3 0 Cond 0 0 0 1 0 0 1 0 SBO SBO SBO 0 0 0 1 Rm

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Example: if statement

C: if (a < b) { x = 5; y = c + d; } else x = c - d;

Assembler:; compute and test condition

ADR r4,a ; get address for aLDR r0,[r4] ; get value of aADR r4,b ; get address for bLDR r1,[r4] ; get value for bCMP r0,r1 ; compare a < bBGE fblock ; if a >= b, branch to false block

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If statement, cont’d.

; true blockMOV r0,#5 ; generate value for xADR r4,x ; get address for xSTR r0,[r4] ; store xADR r4,c ; get address for cLDR r0,[r4] ; get value of cADR r4,d ; get address for dLDR r1,[r4] ; get value of dADD r0,r0,r1; compute yADR r4,y ; get address for ySTR r0,[r4] ; store yB after ; branch around false block

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If statement, cont’d.

; false blockfblock ADR r4,c ; get address for c

LDR r0,[r4] ; get value of cADR r4,d ; get address for dLDR r1,[r4] ; get value for dSUB r0,r0,r1 ; compute a-bADR r4,x ; get address for xSTR r0,[r4] ; store value of x

after ...

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Example: Conditional instruction implementation

; true blockMOVLT r0,#5 ; generate value for xADRLT r4,x ; get address for xSTRLT r0,[r4] ; store xADRLT r4,c ; get address for cLDRLT r0,[r4] ; get value of cADRLT r4,d ; get address for dLDRLT r1,[r4] ; get value of dADDLT r0,r0,r1 ; compute yADRLT r4,y ; get address for ySTRLT r0,[r4] ; store y

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Conditional instruction implementation, cont’d.

; false blockADRGE r4,c ; get address for cLDRGE r0,[r4] ; get value of cADRGE r4,d ; get address for dLDRGE r1,[r4] ; get value for dSUBGE r0,r0,r1 ; compute a-bADRGE r4,x ; get address for xSTRGE r0,[r4] ; store value of x

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Example: switch statement

C: switch (test) { case 0: … break; case 1: … }

Assembler:ADR r2,test ; get address for testLDR r0,[r2] ; load value for testADR r1,switch tab ; load address for switch tableLDR r1,[r1,r0,LSL #2] ; index switch table

switch tab DCD case0DCD case1

...

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Subroutine calling

AREA Example, CODE, READONLY ; name this blk of codeENTRY ; mark I instruction to execute

startMOV r0, #15 ; Set up parametersMOV r1, #20BL firstfunc ; Call subroutineSWI 0x11 ; terminate

firstfunc ; Subroutine firstfuncADD r0, r0, r1 ; r0 = r0 + r1MOV pc, lr ; Return from subroutine

; with result in r0END ; mark end of file

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Switch statement with subroutinesAREA ArithGate, CODE ; name this block of codeENTRY ; mark the first instruction to call

mainMOV r0, #2 ; set up three parametersMOV r1, #5MOV r2, #15BL arithfunc ; call the functionSWI 0x11 ; terminate

arithfunc ; label the functionCMP r0, #4 ; Treat code as unsigned integerBHI ReturnA1 ; If code > 4 then return first argumentADR r3, JumpTable ; Load address of the jump tableLDR pc,[r3,r0,LSL #2] ; Jump to appropriate routine

JumpTableDCD ReturnA1DCD ReturnA2DCD DoAddDCD DoSubDCD DoRsb

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Continued…..ReturnA1

MOV r0, r1 ; Operation 0, >4MOV pc,lr

ReturnA2MOV r0, r2 ; Operation 1MOV pc,lr

DoAddADD r0, r1, r2 ; Operation 2MOV pc,lr

DoSubSUB r0, r1, r2 ; Operation 3MOV pc,lr

DoRsbRSB r0, r1, r2 ; Operation 4MOV pc,lrEND ; mark the end of this file

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Summary

• 7 operating modes: User, FIQ, IRQ, SVC, ABT, UND, SYS• Mode indications in CPSR/SPSR: CPSR[4:0]• Exception handling in ARM Processor: LR, Stack, Vector

addresses, Priority• Working with CPSR/SPSR: MSR, MRS• 16 Conditional execution on all instructions• Branch Instruction: B, BL• Branch with mode change: BX• Implementation of high level constructs

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Thank You, Any Questions ?