arm.armv7 m.arm.ddi0403c

ARM v7-M Architecture Reference Manual

Copyright 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 (ID021910)

ARMv7-M Architecture Reference ManualCopyright 2006-2010 ARM Limited. All rights reserved.Release Information The following changes have been made to this document.Change history Date June 2006 July 2007 September 2008 Issue A B C Confidentiality Non-confidential Non-confidential Non-confidential, Restricted Access Change Initial release Second release, errata and changes documented separately Options for additional watchpoint based trace in the DWT, plus errata updates and clarifications. Marked-up errata PDF, see page iii for more information. Additional marked-up errata PDF, see page iii for more information.

July 2009 February 2010

C_errata C_errata_v3

Non-confidential Non-confidential

Proprietary Notice This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture Reference Manual. Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture infringe any third party patents. This ARM Architecture Reference Manual is provided as is. ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or that any practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third party patents, copyrights, trade secrets, or other rights. This ARM Architecture Reference Manual may include technical inaccuracies or typographical errors. To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this ARM Architecture Reference Manual, even if ARM has been advised of the possibility of such damages. Words and logos marked with or are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. Copyright 2006-2010 ARM Limited 110 Fulbourn Road Cambridge, England CB1 9NJ

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Copyright 2006-2010 ARM Limited. All rights reserved. Non-Confidential, Unrestricted Access

ARM DDI 0403C_errata_v3 ID021910

Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out above.

In this document, where the term ARM is used to refer to the company it means ARM or any of its subsidiaries as appropriate.

NoteThe term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way.

Note This errata PDF is regenerated from the source files of issue C of this document, but: Some pseudocode examples, that are imported into the document, have been updated. Markups highlight significant changes in these pseudocode inserts. Other pseudocode updates are made using the standard Acrobat editing tools. Pages ii and iii of the PDF have been replaced, by an edit to the PDF, to include an updated Proprietary Notice.

With these exceptions, this PDF corresponds to the released PDF of issue C of the document, with errata indicated by markups to the PDF: the original errata markups, issued June 2009, are identified as ARM_2009_Q2 additional errata markups, issued February 2010, are identified as ARM_2009_Q4.

In the revised pseudocode, the function BadReg(x) is replaced by a new construct, x IN {13,15}, that can be used in other contexts. This is a format change only. From February 2010, issue C of the ARMv7-M ARM is superseded by issue D of the document. ARM strongly recommends you to use issue D of the document in preference to using this errata PDF.



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iv



Contents ARMv7-M Architecture Reference Manual

PrefaceAbout this manual .............................................................................. xviii Using this manual ............................................................................... xix Conventions ....................................................................................... xxii Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv

Part AChapter A1 Chapter A2

Application Level ArchitectureIntroductionA1.1 The ARM Architecture M profile .................................................... A1-2

Application Level Programmers ModelA2.1 A2.2 A2.3 A2.4 A2.5 About the Application level programmers model ............................. A2-2 ARM core data types and arithmetic ................................................ A2-3 Registers and execution state ........................................................ A2-11 Exceptions, faults and interrupts .................................................... A2-15 Coprocessor support ...................................................................... A2-16

Chapter A3

ARM Architecture Memory ModelA3.1 Address space ................................................................................. A3-2

ARM DDI 0403CRestricted Access

Copyright 2006-2008 ARM Limited. All rights reserved. Non-Confidential

v

Contents

A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8

Alignment support ............................................................................ A3-3 Endian support ................................................................................. A3-5 Synchronization and semaphores .................................................... A3-8 Memory types and attributes and the memory order model .......... A3-18 Access rights .................................................................................. A3-28 Memory access order .................................................................... A3-30 Caches and memory hierarchy ...................................................... A3-38

Chapter A4

The ARMv7-M Instruction SetA4.1 A4.2 A4.3 A4.4 A4.5 A4.6 A4.7 A4.8 A4.9 A4.10 About the instruction set .................................................................. A4-2 Unified Assembler Language ........................................................... A4-4 Branch instructions .......................................................................... A4-7 Data-processing instructions ............................................................ A4-8 Status register access instructions ................................................ A4-15 Load and store instructions ............................................................ A4-16 Load/store multiple instructions ..................................................... A4-19 Miscellaneous instructions ............................................................. A4-20 Exception-generating instructions .................................................. A4-21 Coprocessor instructions ............................................................... A4-22

Chapter A5

Thumb Instruction Set EncodingA5.1 A5.2 A5.3 Thumb instruction set encoding ....................................................... A5-2 16-bit Thumb instruction encoding ................................................... A5-5 32-bit Thumb instruction encoding ................................................. A5-13

Chapter A6

Thumb Instruction DetailsA6.1 A6.2 A6.3 A6.4 A6.5 A6.6 A6.7 Format of instruction descriptions .................................................... A6-2 Standard assembler syntax fields .................................................... A6-7 Conditional execution ....................................................................... A6-8 Shifts applied to a register ............................................................. A6-12 Memory accesses .......................................................................... A6-15 Hint Instructions ............................................................................. A6-16 Alphabetical list of ARMv7-M Thumb instructions .......................... A6-17

Part BChapter B1

System Level ArchitectureSystem Level Programmers ModelB1.1 B1.2 B1.3 B1.4 B1.5 Introduction to the system level ....................................................... B1-2 ARMv7-M: a memory mapped architecture ..................................... B1-3 System level operation and terminology overview ........................... B1-4 Registers .......................................................................................... B1-8 Exception model ............................................................................ B1-14

Chapter B2

System Memory ModelB2.1 Introduction ...................................................................................... B2-2

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Contents

B2.2

Pseudocode details of general memory system operations ............. B2-3

Chapter B3

System Address MapB3.1 B3.2 B3.3 B3.4 B3.5 The system address map ................................................................. B3-2 System Control Space (SCS) ........................................................... B3-6 System timer - SysTick .................................................................. B3-24 Nested Vectored Interrupt Controller (NVIC) ................................. B3-28 Protected Memory System Architecture (PMSAv7) ....................... B3-35

Chapter B4

ARMv7-M System InstructionsB4.1 Alphabetical list of ARMv7-M system instructions ............................ B4-2

Part CChapter C1

Debug ArchitectureARMv7-M DebugC1.1 C1.2 C1.3 C1.4 C1.5 C1.6 C1.7 C1.8 C1.9 C1.10 C1.11 Introduction to debug ....................................................................... C1-2 The Debug Access Port (DAP) ........................................................ C1-4 Overview of the ARMv7-M debug features ...................................... C1-8 Debug and reset ............................................................................ C1-13 Debug event behavior .................................................................... C1-14 Debug register support in the SCS ................................................ C1-19 Instrumentation Trace Macrocell (ITM) support ............................. C1-27 Data Watchpoint and Trace (DWT) support ................................... C1-33 Embedded Trace (ETM) support .................................................... C1-56 Trace Port Interface Unit (TPIU) .................................................... C1-57 Flash Patch and Breakpoint (FPB) support .................................... C1-61

Appendix A

CPUIDA.1 A.2 A.3 A.4 A.5 A.6 A.7 A.8 Core Feature ID Registers ......................................................... AppxA-2 Processor Feature register0 (ID_PFR0) .................................... AppxA-4 Processor Feature register1 (ID_PFR1) .................................... AppxA-5 Debug Features register0 (ID_DFR0) ........................................ AppxA-6 Auxiliary Features register0 (ID_AFR0) ..................................... AppxA-7 Memory Model Feature registers ............................................... AppxA-8 Instruction Set Attribute registers background information ... AppxA-10 Instruction Set Attribute registers details ............................... AppxA-12

Appendix B Appendix C

ARMv7-M infrastructure IDs Legacy Instruction MnemonicsC.1 C.2 Thumb instruction mnemonics ................................................... AppxC-2 Pre-UAL pseudo-instruction NOP .............................................. AppxC-6



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Contents

Appendix D Appendix E

Deprecated Features in ARMv7-M Debug ITM and DWT packet protocolE.1 E.2 Packet Types ............................................................................. AppxE-2 DWT packet formats .................................................................. AppxE-8

Appendix F

ARMv7-R differencesF.1 F.2 F.3 F.4 Endian support ........................................................................... Application level support ............................................................ System level support .................................................................. Debug support ........................................................................... AppxF-2 AppxF-3 AppxF-4 AppxF-5

Appendix G

Pseudocode definitionG.1 G.2 G.3 G.4 G.5 G.6 G.7 Instruction encoding diagrams and pseudocode ...................... AppxG-2 Limitations of pseudocode ........................................................ AppxG-4 Data Types ................................................................................ AppxG-5 Expressions .............................................................................. AppxG-9 Operators and built-in functions .............................................. AppxG-11 Statements and program structure ......................................... AppxG-17 Miscellaneous helper procedures and functions ..................... AppxG-22

Appendix H

Pseudocode IndexH.1 H.2 Pseudocode operators and keywords ........................................ AppxH-2 Pseudocode functions and procedures ...................................... AppxH-5

Appendix I

Register IndexI.1 I.2 I.3 ARM core registers ..................................................................... AppxI-2 Memory mapped system registers .............................................. AppxI-3 Memory mapped debug registers ............................................... AppxI-5

Glossary

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List of Tables ARMv7-M Architecture Reference Manual

Table A3-1 Table A3-2 Table A3-3 Table A3-4 Table A3-5 Table A3-6 Table A3-7 Table A3-8 Table A4-1 Table A4-2 Table A4-3 Table A4-4 Table A4-5 Table A4-6 Table A4-7 Table A4-8 Table A4-9 Table A4-10 Table A4-11 Table A4-12 Table A5-1 Table A5-2

Change History .................................................................................................... ii Little-endian byte format ................................................................................. A3-5 Big-endian byte format ................................................................................... A3-5 Little-endian memory system ......................................................................... A3-6 Big-endian memory system ............................................................................ A3-6 Load-store and element size association ....................................................... A3-7 Effect of Exclusive instructions and write operations on local monitor ......... A3-10 Effect of load/store operations on global monitor for processor(n) ............... A3-14 Memory attribute summary .......................................................................... A3-19 Branch instructions ......................................................................................... A4-7 Standard data-processing instructions ........................................................... A4-9 Shift instructions ........................................................................................... A4-10 General multiply instructions ........................................................................ A4-11 Signed multiply instructions .......................................................................... A4-11 Unsigned multiply instructions ...................................................................... A4-11 Core saturating instructions ......................................................................... A4-12 Packing and unpacking instructions ............................................................. A4-13 Miscellaneous data-processing instructions ................................................. A4-14 Load and store instructions .......................................................................... A4-16 Load/store multiple instructions .................................................................... A4-19 Miscellaneous instructions ........................................................................... A4-20 16-bit Thumb instruction encoding ................................................................. A5-5 16-bit shift(immediate), add, subtract, move and compare encoding ............. A5-6



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List of Tables

Table A5-3 Table A5-4 Table A5-5 Table A5-6 Table A5-7 Table A5-8 Table A5-9 Table A5-10 Table A5-11 Table A5-12 Table A5-13 Table A5-14 Table A5-15 Table A5-16 Table A5-17 Table A5-18 Table A5-19 Table A5-20 Table A5-21 Table A5-22 Table A5-23 Table A5-24 Table A5-25 Table A5-26 Table A5-27 Table A5-28 Table A6-1 Table A6-2 Table A6-3 Table A6-4 Table B1-1 Table B1-2 Table B1-3 Table B1-4 Table B1-5 Table B1-6 Table B1-7 Table B1-8 Table B1-9 Table B1-10 Table B3-1 Table B3-2 Table B3-3 Table B3-4 Table B3-5 Table B3-6 Table B3-7

16-bit data processing instructions ................................................................. A5-7 Special data instructions and branch and exchange ...................................... A5-8 16-bit Load/store instructions ......................................................................... A5-9 Miscellaneous 16-bit instructions ................................................................. A5-10 If-Then and hint instructions ......................................................................... A5-11 Branch and supervisor call instructions ........................................................ A5-12 32-bit Thumb encoding ................................................................................ A5-13 32-bit modified immediate data processing instructions .............................. A5-14 Encoding of modified immediates in Thumb data-processing instructions .. A5-15 32-bit unmodified immediate data processing instructions .......................... A5-17 Branches and miscellaneous control instructions ........................................ A5-18 Change Processor State, and hint instructions ............................................ A5-19 Miscellaneous control instructions ............................................................... A5-19 Load/store multiple instructions .................................................................... A5-20 Load/store dual or exclusive, table branch ................................................... A5-21 Load word .................................................................................................... A5-22 Load halfword ............................................................................................... A5-23 Load byte, preload ....................................................................................... A5-24 Store single data item .................................................................................. A5-25 Data-processing (shifted register) ................................................................ A5-26 Move register and immediate shifts ............................................................. A5-27 Data processing (register) ............................................................................ A5-28 Miscellaneous operations ............................................................................. A5-29 Multiply, and multiply accumulate operations ............................................... A5-30 Long multiply, long multiply accumulate, and divide operations .................. A5-31 Coprocessor instructions .............................................................................. A5-32 Condition codes ............................................................................................. A6-8 Effect of IT execution state bits .................................................................... A6-11 Determination of mask field ......................................................................... A6-79 MOV (shift, register shift) equivalences) .................................................... A6-152 Mode, privilege and stack relationship ........................................................... B1-4 The xPSR register layout ............................................................................... B1-9 ICI/IT bit allocation in the EPSR .................................................................. B1-10 The special-purpose mask registers ............................................................ B1-10 Exception numbers ...................................................................................... B1-16 Vector table format ....................................................................................... B1-16 Priority grouping ........................................................................................... B1-18 Exception return behavior ............................................................................ B1-26 List of supported faults ................................................................................. B1-40 Behavior of faults which occur during NMI or HardFault execution ............. B1-45 ARMv7-M address map ................................................................................. B3-3 SCS address space regions ........................................................................... B3-6 System control and ID registers ..................................................................... B3-7 Auxiliary Control Register (0xE000E008) .................................................... B3-9 CPUID Base Register (CPUID, 0xE000ED00) .......................................... B3-10 Interrupt Control and State Register (0xE000ED04) ................................. B3-12 Vector Table Offset Register (0xE000ED08) ............................................ B3-13

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List of Tables

Table B3-8 Table B3-9 Table B3-10 Table B3-11 Table B3-12 Table B3-13 Table B3-14 Table B3-15 Table B3-16 Table B3-17 Table B3-18 Table B3-19 Table B3-20 Table B3-21 Table B3-22 Table B3-23 Table B3-24 Table B3-25 Table B3-26 Table B3-27 Table B3-28 Table B3-29 Table B3-30 Table B3-31 Table B3-32 Table B3-33 Table B3-35 Table B3-36 Table B3-34 Table B3-37 Table B3-38 Table B3-39 Table B3-40 Table B3-41 Table B3-42 Table B3-43 Table B3-44 Table B3-45 Table B3-47 Table B3-48 Table B3-46 Table C1-1 Table C1-2 Table C1-3 Table C1-4 Table C1-5 Table C1-6

Application Interrupt and Reset Control Register (0xE000ED0C) ............. B3-14 System Control Register (0xE000ED10) ...................................................... B3-15 Configuration and Control Register (0xE000ED14) ..................................... B3-16 System Handler Priority Register 1 (0xE000ED18) ................................... B3-17 System Handler Priority Register 2 (0xE000ED1C) .................................. B3-17 System Handler Priority Register 3 (0xE000ED20) ................................... B3-17 System Handler Control and State Register (0xE000ED24) ..................... B3-18 Configurable Fault Status Registers (CFSR, 0xE000ED28) ........................ B3-19 MemManage Status Register (MMFSR, 0xE000D28) ................................. B3-19 BusFault Status Register (BFSR, 0xE000ED29) ......................................... B3-20 UsageFault Status Register (UFSR, 0xE000ED2A) ..................................... B3-20 HardFault Status Register (0xE000ED2C) ................................................... B3-21 MemManage Address Register (0xE000ED34) ........................................... B3-22 BusFault Address Register (0xE000ED38) .................................................. B3-22 Coprocessor Access Control Register (0xE000ED88) ............................... B3-22 Software Trigger Interrupt Register (0xE000EF00) ................................... B3-23 SysTick register support in the SCS ............................................................ B3-25 SysTick Control and Status Register (0xE000E010) ................................ B3-26 SysTick Reload Value Register (0xE000E014) ......................................... B3-26 SysTick Current Value Register (0xE000E018) ........................................ B3-27 SysTick Calibration Value Register (0xE000E01C) .................................. B3-27 NVIC register support in the SCS ................................................................ B3-30 Interrupt Controller Type Register (0xE000E004) ..................................... B3-32 Interrupt Set-Enable Registers (0xE000E100-E17C) ................................ B3-33 Interrupt Clear-Enable Registers (0xE000E180-E1FC) ............................ B3-33 Interrupt Set-Pending Registers (0xE000E200-E27C) .............................. B3-33 Interrupt Active Bit Registers (0xE000E300-E37C) .................................. B3-34 Interrupt Priority Registers (0xE000E400-E7F8) ....................................... B3-34 Interrupt Clear-Pending Registers (0xE000E280-E2FC) .......................... B3-34 MPU register support in the SCS ................................................................. B3-39 MPU Type Register (0xE000ED90) .......................................................... B3-39 MPU Control Register (0xE000ED94) ....................................................... B3-40 MPU Region Number Register (0xE000ED98) ......................................... B3-41 MPU Region Base Address Register (0xE000ED9C) ............................... B3-41 MPU Region Attribute and Size Register (0xE000EDA0) ......................... B3-42 Region Size Encoding .................................................................................. B3-42 Region attribute fields .................................................................................. B3-43 TEX/CB/S Encoding ..................................................................................... B3-44 AP encoding ................................................................................................. B3-45 XN encoding ................................................................................................. B3-45 Cache policy encoding ................................................................................. B3-45 PPB debug related regions ............................................................................ C1-3 ROM table entry format .................................................................................. C1-4 ARMv7-M DAP accessible ROM table ........................................................... C1-4 ARMv7 debug authentication signals ............................................................. C1-9 Debug related faults ..................................................................................... C1-15 Debug stepping control using the DHCSR ................................................... C1-16



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List of Tables

Table C1-7 Table C1-8 Table C1-9 Table C1-10 Table C1-11 Table C1-12 Table C1-13 Table C1-14 Table C1-15 Table C1-16 Table C1-17 Table C1-18 Table C1-19 Table C1-20 Table C1-21 Table C1-22 Table C1-23 Table C1-24 Table C1-25 Table C1-26 Table C1-27 Table C1-28 Table C1-29 Table C1-30 Table C1-31 Table C1-32 Table C1-33 Table C1-34 Table C1-35 Table C1-36 Table C1-37 Table C1-38 Table C1-39 Table C1-40 Table C1-41 Table C1-42 Table C1-43 Table C1-44 Table A-1 Table B-1 Table B-2 Table C-1 Table E-1 Table E-2 Table E-3 Table E-4 Table E-5

Debug register region of the SCS ................................................................ C1-19 Debug Fault Status Register (0xE000ED30) ............................................... C1-19 Debug Halting Control and Status Register (0xE000EDF0) ..................... C1-20 Debug Core Register Selector Register (0xE000EDF4) ........................... C1-22 Debug Core Register Data Register (0xE000EDF8) ................................. C1-23 Debug Exception and Monitor Control Register (0xE000EDFC) .............. C1-24 ITM registers ................................................................................................ C1-29 Stimulus Port Register: STIMx ..................................................................... C1-30 Transfer Enable Register: TER .................................................................... C1-30 Trace Privilege Register: TPR ...................................................................... C1-31 Trace Control Register: TCR ........................................................................ C1-31 Cycle count event generation ....................................................................... C1-35 DWT register set feature summary .............................................................. C1-38 General DWT function support ..................................................................... C1-39 DWT comparator support for CYCCNT ........................................................ C1-41 DWT comparator support for data matching ................................................ C1-42 DWT register summary ................................................................................ C1-47 DWT_CTRL (0xE0001000) .......................................................................... C1-48 DWT_CYCCNT (0xE0001004) .................................................................... C1-49 DWT_CPICNT (0xE0001008) ...................................................................... C1-50 DWT_INTCNT (0xE000100C) ...................................................................... C1-50 DWT_SLEEPCNT (0xE0001010) ................................................................ C1-51 DWT_LSUCNT (0xE0001014) ..................................................................... C1-51 DWT_FOLDCNT (0xE0001018) .................................................................. C1-52 DWT_PCSR (0xE000101C) ......................................................................... C1-52 DWT_COMPx .............................................................................................. C1-53 DWT_MASKx ............................................................................................... C1-53 DWT_FUNCTIONx ....................................................................................... C1-54 TPIU programmers model overview ............................................................ C1-58 Supported Synchronous Port Sizes Register (0xE0040000) ....................... C1-58 Asynchronous Clock Prescaler Register (0xE0040010) .............................. C1-59 Selected Pin Protocol Register (0xE00400F0) ............................................. C1-59 TPIU Type Register (0xE0040FC8) ............................................................. C1-60 Flash Patch and Breakpoint register summary ............................................ C1-62 FP_CTRL ..................................................................................................... C1-64 FP_REMAP .................................................................................................. C1-64 FP_COMPx instruction comparison ............................................................. C1-65 FP_COMPx literal comparison ..................................................................... C1-66 Core Feature ID register support in the SCS ........................................... AppxA-2 Component and Peripheral ID register formats ........................................ AppxB-2 ARMv7-M and CoreSight management registers .................................... AppxB-3 Pre-UAL assembly syntax ........................................................................ AppxC-2 ITM and DWT general packet formats ..................................................... AppxE-2 Sync packet (matches ETM format) ......................................................... AppxE-3 Overflow packet format ............................................................................ AppxE-3 Timestamp packet format 1 ...................................................................... AppxE-4 Timestamp packet format 2 ...................................................................... AppxE-5

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List of Tables

Table E-6 Table E-7 Table E-8 Table E-9 Table E-10 Table E-11 Table E-12 Table E-13 Table E-14 Table E-15 Table E-16 Table E-17 Table H-1 Table H-2 Table I-1 Table I-2 Table I-3

Software instrumentation packet format ................................................... AppxE-5 Hardware source packet format ............................................................... AppxE-6 Extension packet format ........................................................................... AppxE-6 Reserved packet encodings ..................................................................... AppxE-7 Event packet (discriminator ID0) format ................................................... AppxE-8 Event flag support .................................................................................... AppxE-8 Event packet (discriminator ID1) format ................................................... AppxE-9 Event packet (discriminator ID2) format ................................................... AppxE-9 Sleep packet format ............................................................................... AppxE-10 Event packet (discriminator ID16 to ID23) format .................................. AppxE-10 Event packet (discriminator ID8, ID10, ID12, ID14) format .................... AppxE-11 Event packet (discriminator ID9, ID11, ID13, ID15) format .................... AppxE-11 Pseudocode operators and keywords ...................................................... AppxH-2 Pseudocode functions and procedures .................................................... AppxH-5 ARM core register index ............................................................................ AppxI-2 Memory-mapped control register index ..................................................... AppxI-3 Memory-mapped debug register index ..................................................... AppxI-5



xiii

List of Tables

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List of Figures ARMv7-M Architecture Reference Manual

Figure A3-1 Figure A3-2 Figure A3-3 Figure A3-4 Figure C1-1

Instruction byte order in memory .................................................................... A3-7 Local monitor state machine diagram .......................................................... A3-10 Global monitor state machine diagram for processor(n) in a multiprocessor system A3-13 Memory ordering restrictions ........................................................................ A3-34 DBGRESTART / DBGRESTARTED handshake .......................................... C1-10



xv

List of Figures

xvi



Preface

This preface describes the contents of this manual, then lists the conventions and terminology it uses. About this manual on page xviii Using this manual on page xix Conventions on page xxii Further reading on page xxiii Feedback on page xxiv.



xvii

Preface

About this manualThis manual documents the Microcontroller profile associated with version 7 of the ARM Architecture (ARMv7-M). For short-form definitions of all the ARMv7 profiles see page A1-1. The manual consists of three parts: Part A The application level programming model and memory model information along with the instruction set as visible to the application programmer. This is the information required to program applications or to develop the toolchain components (compiler, linker, assembler and disassembler) excluding the debugger. For ARMv7-M, this is almost entirely a subset of material common to the other two profiles. Instruction set details which differ between profiles are clearly stated.

NoteAll ARMv7 profiles support a common procedure calling standard, the ARM Architecture Procedure Calling Standard (AAPCS). Part B The system level programming model and system level support instructions required for system correctness. The system level supports the ARMv7-M exception model. It also provides features for configuration and control of processor resources and management of memory access rights. This is the information in addition to Part A required for an operating system (OS) and/or system support software. It includes details of register banking, the exception model, memory protection (management of access rights) and cache support. Part B is profile specific. ARMv7-M introduces a new programmers model and as such has some fundamental differences at the system level from the other profiles. As ARMv7-M is a memory-mapped architecture, the system memory map is documented here. Part C The debug features to support the ARMv7-M debug architecture and the programmers interface to the debug environment. This is the information required in addition to Parts A and B to write a debugger. Part C covers details of the different types of debug: halting debug and the related Debug state exception-based monitor debug non-invasive support for event generation and signalling of the events to an external agent.

This part is profile specific and includes several debug features unique within the ARMv7 architecture to this profile.

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Preface

Using this manualThe information in this manual is organized into four parts as described below.

Part A, Application level architecturePart A describes the application level view of the architecture. It contains the following chapters: Chapter A1 Introduction ARMv7 overview, the different architecture profiles and the background to the Microcontroller (M) profile. Chapter A2 Application Level Programmers Model Details on the registers and status bits available at the application level along with a summary of the exception support. Chapter A3 ARM Architecture Memory Model Details of the ARM architecture memory attributes and memory order model. Chapter A4 The ARMv7-M Instruction Set General information on the Thumb instruction set. Chapter A5 Thumb Instruction Set EncodingUNDEFINED

Encoding diagrams for the Thumb instruction set along with information on bit field usage, and UNPREDICTABLE terminology.

Chapter A6 Thumb Instruction Details Contains detailed reference material on each Thumb instruction, arranged alphabetically by instruction mnemonic. Summary information for system instructions is included and referenced for detailed definition in Part B.

Part B, system level architecturePart B describes the system level view of the architecture. It contains the following chapters: Chapter B1 System Level Programmers Model Details of the registers, status and control mechanisms available at the system level. Chapter B2 System Memory Model Details of the pseudocode used to support memory accesses to the ARM architecture memory model. Chapter B3 System Address Map Overview of the system address map and details of the architecturally defined features within the Private Peripheral Bus region. This chapter includes details of the memory-mapped support for a protected memory system.



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Preface

Chapter B4 ARMv7-M System Instructions Contains detailed reference material on the system level instructions.

Part C, debug architecturePart C describes the debug architecture. It contains the following chapter: Chapter C1 ARMv7-M Debug ARMv7-M debug support.

Part D, appendicesThis manual contains a glossary and the following appendices: Appendix A CPUID The revised format for ARM architecture CPUID registers including the description and associated values of all attribute fields relevant to the ARMv7-M architecture. Attribute values are used to describe instruction set and memory model support of an architecture variant. Some attribute values reflect architectural choice for an implementation. Appendix B ARMv7-M infrastructure IDs A summary of the ARM CoreSight compatible ID registers used for ARM architecture infrastructure identification. Appendix C Legacy Instruction Mnemonics A cross reference of Unified Assembler Language forms of the instruction syntax to the Thumb format used in earlier versions of the ARM architecture. Appendix D Deprecated Features in ARMv7-M Deprecated features that software is advised to avoid for future proofing. ARM intends to remove this functionality in a future version of the ARM architecture. Appendix E Debug ITM and DWT packet protocol The debug trace packet protocol used to export ITM and DWT sourced information. Appendix F ARMv7-R differences A summary of differences between the ARMv7-R and ARMv7-M profiles. Appendix G Pseudocode definition Definition of terms, format and helper functions used by the pseudocode to describe the memory model and instruction operations. Appendix H Pseudocode Index Index to definitions of pseudocode operators, keywords, functions, and procedures.

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Preface

Appendix I Register Index Index to register descriptions in the manual Glossary Glossary of terms - does not include terms associated with pseudocode.



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Preface

ConventionsThis manual employs typographic and other conventions intended to improve its ease of use.

General typographic conventionstypewriter

Is used for assembler syntax descriptions, pseudocode descriptions of instructions, and source code examples. For more details of the conventions used in assembler syntax descriptions see Assembler syntax on page A6-4. For more details of pseudocode conventions see Appendix G Pseudocode definition. The typewriter font is also used in the main text for instruction mnemonics and for references to other items appearing in assembler syntax descriptions, pseudocode descriptions of instructions and source code examples.

italic boldSMALL CAPITALS

Highlights important notes, introduces special terminology, and denotes internal cross-references and citations. Is used for emphasis in descriptive lists and elsewhere, where appropriate. Are used for a few terms which have specific technical meanings.

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Preface

Further readingThis section lists publications that provide additional information on the ARM architecture and ARM family of processors. This manual provides architecture information, the contract between hardware and software for development of ARM compliant cores, compiler and debug tools development and software to run on the ARM targets. The Technical Reference Manual (TRM) for the implementation of interest provides details of the IMPLEMENTATION DEFINED architecture features in the ARM compliant core. The silicon partners device specification should be used for additional system details. ARM periodically provides updates and corrections to its documentation. For the latest information and errata, some materials are published at http://www.arm.com. Alternatively, contact your distributor, or silicon partner who will have access to the latest published ARM information, as well as information specific to the device of interest. Your local ARM office has access to the latest published ARM information.

ARM publicationsThis document is specific to the ARMv7-M architecture. Other relevant publications relating to ARMv7-M implementations and ARMs debug architecture are: Cortex-M3 Technical Reference Manual (ARM DDI 0337) Procedure Call Standard for the ARM Architecture (ARM GENC 003534) ARM Debug Interface v5 Architecture Specification (ARM IHI 0031) CoreSight Architecture Specification (ARM IHI 0029) Embedded Trace Macrocell Architecture Specification (ARM DDI 0014). For information on ARMv6-M, see the ARMv6-M Architecture Reference Manual (ARM DDI 0419). For information on the ARMv7-A and -R profiles, see the ARM Architecture Reference Manual (ARM DDI 0406).



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Preface

FeedbackARM welcomes feedback on its documentation.

Feedback on this bookIf you notice any errors or omissions in this book, send email to [email protected] giving: the document title the document number the page number(s) to which your comments apply a concise explanation of the problem. General suggestions for additions and improvements are also welcome.

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Part AApplication Level Architecture

Chapter A1 Introduction

ARMv7 is documented as a set of architecture profiles. Three profiles have been defined as follows: ARMv7-A ARMv7-R ARMv7-M the application profile for systems supporting the ARM and Thumb instruction sets, and requiring virtual address support in the memory management model. the realtime profile for systems supporting the ARM and Thumb instruction sets, and requiring physical address only support in the memory management model the microcontroller profile for systems supporting only the Thumb instruction set, and where overall size and deterministic operation for an implementation are more important than absolute performance.

While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have implicitly existed in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA) respectively. Instruction Set Architecture (ISA) ARMv7-M only supports execution of Thumb instructions. For a detailed list of the instructions supported, see Chapter A6 Thumb Instruction Details.



A1-1

Introduction

A1.1

The ARM Architecture M profileThe ARM architecture has evolved through several major revisions to a point where it supports implementations across a wide spectrum of performance points, with over a billion parts per annum being produced. The latest version (ARMv7) has seen the diversity formally recognized in a set of architecture profiles, the profiles used to tailor the architecture to different market requirements. A key factor is that the application level is consistent across all profiles, and the bulk of the variation is at the system level. The introduction of Thumb-2 technology in ARMv6T2 provided a balance to the ARM and Thumb instruction sets, and the opportunity for the ARM architecture to be extended into new markets, in particular the microcontroller marketplace. To take maximum advantage of this opportunity a Thumb-only profile with a new programmers model (a system level consideration) has been introduced as a unique profile, complementing ARMs strengths in the high performance and real-time embedded markets.

Key criteria for ARMv7-M implementations are as follows: Enable implementations with industry leading power, performance and area constraints Opportunities for simple pipeline designs offering leading edge system performance levels in a broad range of markets and applications

Highly deterministic operation Single/low cycle execution Minimal interrupt latency (short pipelines) Cacheless operation

Excellent C/C++ target aligns with ARMs programming standards in this area Exception handlers are standard C/C++ functions, entered using standard calling conventions

Designed for deeply embedded systems Low pincount devices Enable new entry level opportunities for the ARM architecture

Debug and software profiling support for event driven systems

This manual is specific to the ARMv7-M profile.

A1-2



Chapter A2 Application Level Programmers Model

This chapter provides an application level view of the programmers model. This is the information necessary for application development, as distinct from the system information required to service and support application execution under an operating system. It contains the following sections: About the Application level programmers model on page A2-2 ARM core data types and arithmetic on page A2-3 Registers and execution state on page A2-11 Exceptions, faults and interrupts on page A2-15 Coprocessor support on page A2-16 System related information is provided in overview form and/or with references to the system information part of the architecture specification as appropriate.



A2-1

Application Level Programmers Model

A2.1

About the Application level programmers modelThis chapter contains the programmers model information required for application development. The information in this chapter is distinct from the system information required to service and support application execution under an operating system. That information is given in Chapter B1 System Level Programmers Model.

A2.1.1

Privileged executionSystem level support requires access to all features and facilities of the architecture, a level of access generally referred to as privileged operation. System code determines whether an application runs in a privileged or unprivileged manner. When an operating system supports both privileged and unprivileged operation, an application usually runs unprivileged. This: permits the operating system to allocate system resources to it in a unique or shared manner provides a degree of protection from other processes and tasks, and so helps protect the operating system from malfunctioning applications.

A2.1.2

System level architectureThread mode is the fundamental mode for application execution in ARMv7-M and is selected on reset. Thread mode can raise a supervisor call using the SVC instruction or handle system access and control directly. All exceptions execute in Handler mode. Supervisor call (SVCall) handlers manage resources on behalf of the application such as interaction with peripherals, memory allocation and management of software stacks. This chapter only provides a limited amount of system level information. Where appropriate it: gives an overview of the system level information gives references to the system level descriptions in Chapter B1 System Level Programmers Model and elsewhere.

A2-2




A2.2

ARM core data types and arithmeticARMv7-M processors support the following data types in memory: Byte 8 bits Halfword 16 bits Word 32 bits Processor registers are 32 bits in size. The instruction set contains instructions supporting the following data types held in registers: 32-bit pointers unsigned or signed 32-bit integers unsigned 16-bit or 8-bit integers, held in zero-extended form signed 16-bit or 8-bit integers, held in sign-extended form unsigned or signed 64-bit integers held in two registers. Load and store operations can transfer bytes, halfwords, or words to and from memory. Loads of bytes or halfwords zero-extend or sign-extend the data as it is loaded, as specified in the appropriate load instruction. The instruction sets include load and store operations that transfer two or more words to and from memory. You can load and store 64-bit integers using these instructions. When any of the data types is described as unsigned, the N-bit data value represents a non-negative integer in the range 0 to 2N-1, using normal binary format. When any of these types is described as signed, the N-bit data value represents an integer in the range -2N-1 to +2N-1-1, using two's complement format. Direct instruction support for 64-bit integers is limited, and most 64-bit operations require sequences of two or more instructions to synthesize them.



A2-3


A2.2.1

Integer arithmeticThe instruction set provides a wide variety of operations on the values in registers, including bitwise logical operations, shifts, additions, subtractions, multiplications, and many others. These operations are defined using the pseudocode described in Appendix G Pseudocode definition, usually in one of three ways: By direct use of the pseudocode operators and built-in functions defined in Operators and built-in functions on page AppxG-11. By use of pseudocode helper functions defined in the main text. By a sequence of the form: 1. Use of the SInt(), UInt(), and Int() built-in functions defined in Converting bitstrings to integers on page AppxG-14 to convert the bitstring contents of the instruction operands to the unbounded integers that they represent as two's complement or unsigned integers. Use of mathematical operators, built-in functions and helper functions on those unbounded integers to calculate other such integers. Use of either the bitstring extraction operator defined in Bitstring extraction on page AppxG-12 or of the saturation helper functions described in Pseudocode details of saturation on page A2-9 to convert an unbounded integer result into a bitstring result that can be written to a register.

2. 3.

A2-4




Shift and rotate operationsThe following types of shift and rotate operations are used in instructions: Logical Shift Left (LSL) moves each bit of a bitstring left by a specified number of bits. Zeros are shifted in at the right end of the bitstring. Bits that are shifted off the left end of the bitstring are discarded, except that the last such bit can be produced as a carry output. Logical Shift Right (LSR) moves each bit of a bitstring right by a specified number of bits. Zeros are shifted in at the left end of the bitstring. Bits that are shifted off the right end of the bitstring are discarded, except that the last such bit can be produced as a carry output. Arithmetic Shift Right (ASR) moves each bit of a bitstring right by a specified number of bits. Copies of the leftmost bit are shifted in at the left end of the bitstring. Bits that are shifted off the right end of the bitstring are discarded, except that the last such bit can be produced as a carry output. Rotate Right (ROR) moves each bit of a bitstring right by a specified number of bits. Each bit that is shifted off the right end of the bitstring is re-introduced at the left end. The last bit shifted off the the right end of the bitstring can be produced as a carry output. Rotate Right with Extend (RRX) moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. The bit shifted off the right end of the bitstring can be produced as a carry output. Pseudocode details of shift and rotate operations These shift and rotate operations are supported in pseudocode by the following functions:// LSL_C() // ======= (bits(N), bit) LSL_C(bits(N) x, integer shift) assert shift > 0; extended_x = x : Zeros(shift); result = extended_x

arm.armv7 m.arm.ddi0403c

Documents

source code

detailed reference

system address

application

thumb instruction

memory order

assembler

endian memory