ARMhttp://cis.k.hosei.ac.jp/~nakata/lectureMachine/202u_w32_v1.zip
S. Furber/ARMCQ
(2) DevKitAdv

Options -> Directories...
LDR R1, Y ; R1 = Y;
ADD R0, R0, R1 ; R0 = R0 + R1;
STR R0, Z ; STR: Store Register, Z = R0
X DCD 15 ; Define Constant, D: 32-bit integer
Y DCD 21
Z DCD 0
Building...

Build Complete.
Execution Window8008
bl 0x8040
Execute -> Step
bl test
test
View -> Memory...
LDR R0, X

r10x150x24r0Z8098
XYZMemory8080
View -> Low Level Symbols
0x0000000f
do {
i = i + 1; // R3 = R3 + 4;
} while (R0 != R2)
test2.apjtest2.s
AREA test2, CODE
L1 ;
str R0, [R3] ; R3(Out[0],...)
ADD R3, R3, #4 ; R3 = address of Out[i]i=1,2,3,...
CMP R0, R2 ; compare R0 and R2; compute R0 - R2 and set CC
BNE L1 ; if (Z != 1 R0 != R2) go to L1;
SWI 0x11 ; Software Interrupt (Supervisor Call): Halt
M0 DCD 0 ; define constant double word(32bits);
M1 DCD 1 ;
M10 DCD 10 ;
AREA block, DATA, READWRITE
Out % 40 ; "%":
AREA test3, CODE
L1 ADD R1, R1, #1 ; R1 = R1 + 1;
ADD R0, R1, #0x30 ; 1=0000000100110001
SWI WriteC ; WriteC(R0);
CMP R1,#10 ; compute R1 - 10 and set Condition Code
BNE L1 ; if (Z==0 R1 != 10) go to L1;
SWI 0x11
RISCCPUCISC(Complex Instruction Set Computer)CPURISC
ADD R0, R0, R1 ; R0 = R0 + R1
CISC
LDR R0, M0 ; R0 = M0
ADD R0, M1 ; R0 = R0 + M1
CISCRISC

half-word4
word16
0
1
2
3
4
5
6
7
8
9
10
1
1
byte0
byte
12
13
14
15
16
17
18
19
20
21
22
23
byte1
byte2
half-word14
byte3
byte6
half-word6
word16
3
2
1
0
7
6
5
4
1
1
10
9
8
byte3
byte
15
14
13
12
19
18
17
16
23
22
21
20
byte2
byte1
half-word12
byte0
byte5
address
address
N (Negative)

ARM
[]WSwhite spaceWS

ADD R0,R1,#0x30 ; 1

WS EQU
EQUequate
Abc EQU 100

DCW6 DCW 'a', 0xff, 5, 0, 12345, 0xffff
DCD5 DCD 'a', 0xff, 12345, 0xffff, 0xffffff

0x00000005 ; big endian 0x00050000
0xffff3039 ; big endian 0x3039ffff
0x000000ff ; big endian 0x000000ff
0x00003039 ; big endian 0x00003039
0x0000ffff ; big endian 0x0000ffff
0x00ffffff ; big endian 0x00ffffff

ASCII codeISO codeJIS



ADDSUBADCSBCRSBRSCARMARM
add r0, r1, r2 ; r0 = r1 + r2
sub r0, r1, r2 ; r0 = r1 - r2

AND
0
1
0
0
0
1
0
1
01010101 EOR 00001111 = 01011010
r2r1
AND
0
1
0
0
0
1
1
0
MOV r0, r2 ; r0 = r2
MVN r0, r2 ; r0 = not r2

CMPCMNTSTTEQ
CMP r1, r2 ; compare: set cc on r1 - r2
CMN r1, r2 ; compare negative: set cc on r1 + r2ARM
TST r1, r2 ; bit test: set cc on r1 and r2r2
TEQ r1, r2 ; bit test equal: set cc on r1 xor r2
cc: condition code
immediate operand
0x2000000
ADD r3, r3, #1 ; r3 = r3 + 1
MOV r4, #9 ; r4 = 9
AND r8,r7,#0xff ; r8 = r7
MOV r4, #0xff*4
ARM
operand2

0xe28210ff = 1110 00 1 0100 0 0010 0001 0000 11111111
0xe2821fff = 1110 00 1 0100 0 0010 0001 1111 11111111
0xe2821eff = 1110 00 1 0100 0 0010 0001 1110 11111111
0xe2821dff = 1110 00 1 0100 0 0010 0001 1101 11111111
r2r1
-#rot#rot××


LSL: Logical Shift Left0310
LSR: Logical Shift Right0310
ASL: Arithmetic Shift LeftLSL: Logical Shift Left
ASR: Arithmetic Shift Right
RRX: Rotate Right Extended1
Arithmetic Shift LeftARMLogical Shift LeftArithmetic Shift LeftARMArithmetic Shift LeftLogical Shift LeftArithmetic Shift Left
operand2
ADD r3, r2, r1, LSL #3 ; r3 = r2 + r1*23
ADD r5, r5, r3, LSL r2 ; r5 = r5 + r3*2r2

0xe0823181 = 1110 00 0 0100 0 0010 0011 00011 00 0 0001
0xe0855213 = 1110 00 0 0100 0 0101 0101 0010 0 00 1 0011

4
024244
1110 0000 1001 0000 0011 0000 0101 0000

arithmetic shift
m2m
4

1110 0000 0000 0000 0000 0000 0000 0000 -231+230+229

1100 0000 0000 0000 0000 0000 0000 0000 -231+230=-232+231+230=(-231+230+229)*2
1000 0000 0000 0000 0000 0000 0000 0000 -231=-232+231=(-231+230)*2
0000 0000 0000 0000 0000 0000 0000 0000 0≡(-231)*2 (mod 232)


1

MOV r0, r1, LSL #2 ; r0 = r1 * 4
MOV r0, r1, LSL #16 ; r0 = r1 * 65536
ADD r0, r1, r1, LSL #2 ; r0 = r1 * 5 => r0 = r1 + (r1 * 4)
RSB r0, r1, r1, LSL #3 ; r0 = r1 * 7 => r0 = (r1 * 8) - r1


ARM7ALUArithmetic logic unit
ALU 1 ADD, SUB, MOV; +2 if Rd is pc
B, BL 3
STR 2
LDM 2+N N is the number of words to transfer
MUL 1+M M = 14
ARMSH
/


STR r0, [r1] ; mem32[r1] = r0

PC
...
AREA block, DATA, READWRITE
LDR/STRPC
test2.s

0xe59f2020 = 1110 0101 1001 1111 0010 0000 0010 0000
#=0, U=1, Rn=15, Rd=2, offset=0x20=32
0x0080880x200x0080b00x008090PC
(1)(fetch)
AREA block, DATA, READWRITE

LDR R4, =0xffff
LDR r0, [r1,#4] ; r0 = mem32[r1 + 4]
r1ARMpre-indexedpost-indexed
mem32[r1 + 4]mem32[r1 + 8]mem32[r1 + 12]auto-indexing
LDR r0, [r1,#4]! ; r0 = mem32[r1 + 4]
; r1 = r1 + 4
LDR r0, [r1], #4 ; r0 = mem32[r1]
; r1 = r1 + 4
TABLE1TABLE2
Java
i++; j++;
LOOP LDR r0, [r1] ; get a word from TABLE1
STR r0, [r2] ; copy into TABLE2
ADD r1, r1, #4 ; step r1 on 1 word
ADD r2, r2, #4 ; step r2 on 1 word
CMP r0, #0 ; check for data end
BNE LOOP ; loop back
LDR r1, =TABLE1 ; r1 points to TABLE1
LDR r2, =TABLE2 ; r2 points to TABLE2
LOOP LDR r0, [r1], #4 ; get a word from TABLE1 and step r1 on 1 word
STR r0, [r2], #4 ; copy into TABLE2 and step r2 on 1 word
CMP r0, #0 ; check for data end
BNE LOOP ; loop back
i = 0;
i++;
MOV r3, #0 ; i = 0;
loop LDR r0, [r1, r3, LSL #2] ; r0 = [r1 + r3*4] = TABLE1[i]
STR r0, [r2, r3, LSL #2] ; [r2 + r3*4] = r0
ADD r3, r3, #1 ; i++;
CMP r0, #0
ARM"B"
LDRB r0, [r1] ; r0 = mem8[r1]
r1r0
start LDR r1, =srcstr ; pointer to first string
LDR r0, =dststr ; pointer to second string
strcopy ; copy first string over second
LDRB r2, [r1], #1 ; load byte and update address
STRB r2, [r0], #1 ; store byte and update address;
CMP r2, #0 ; check for zero terminator
BNE strcopy ; keep going if not
stop
END

B LABEL
BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC
BLO
Unsigned comparison gave lower
BVC Overflow clear Signed integer operation; no overflow occurred
BVS Overflow set Signed integer operation; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same


BL SUBR ; branch to SUBR
… ; return to here
ARM
ADD r1, r1, r0 ; r1 = r1 + r0;
SUB r1, r1, r2 ; r1 = r1 – r2; }
BYPASS …
ADDNE r1, r1, r0 ; r1 = r1 + r0;
SUBNE r1, r1, r2 ; r1 = r1 – r2; }
BYPASS …

BNE L1 ; goto L1;
BNE L1 ; goto L1;
ADD r4, r4, #1
CMPEQ r2, r3
001 MLA Multiply-accumulate (32-bit result) Rd := (Rm * Rs + Rn) [31:0]
100 UMULL Unsigned multiply long RdHi:RdLo := Rm * Rs
101 UMLAL Unsigned multiply-accumulate long RdHi:RdLo += Rm * Rs
110 SMULL Signed multiply long RdHi:RdLo := Rm * Rs
111 SMLAL Signed multiply-accumulate long RdHi:RdLo += Rm * Rs

r0 + (232 - r1) = 232 + (r0 - r1)
(r0 - r1) >= 0 232CS/HSr0r1
N=1,V=1N=0r0>=r1N=0,V=0r0>=r1N=Vr0>=r1
SWI: software interrupt
ARM Software Development Toolkit ARM
SWI_WriteC (SWI 0)
SWI_ReadC (SWI 4)
SWI_Close (SWI 0x68)
r0r0
SWI_Write (SWI 0x69)
SWI_Read (SWI 0x6a)
Hello World
LOOP LDRB r0, [r1], #1 ; get the next byte
CMP r0, #0 ; check for text end
SWINE SWI_WriteC ; if not end print the byte
BNE LOOP ; if not end loop back
SWI SWI_Exit ; end of execution
TEXT DCB "Hello World", 0x0d, 0x0a, 0
END
Hello World
;
SWI_Exit EQU 0x11
SWI_Clock EQU 0x61
SWI_Open EQU 0x66
SWI_Close EQU 0x68
SWI_Write EQU 0x69
ENTRY ; mark first instruction to execute
start LDR r0, =filename ; r0 points to string
MOV r1, #write_only
MOV r2, #14 ; 14 characters long
SWI SWI_Write ; write to file
MOV r0, r5
SWI SWI_Exit
while (a != b) {
if (a > b)
a = a - b;
BEQ end
BLT less
B gcd
B gcd
BNE gcd
LinuxgccARMARM Software Development Toolkit

Linux
AREA dots,CODE
mov r3, #0x06000000 ; Set VRAM frame buffer address
ldr r4, =0x7FFF ; RGB = 1F/1F/1F --> white
str r4, [ r3 ] ; Put first white dot and black dot
str r4, [ r3, #4 ] ; Then put second white dot and black dot
str r4, [ r3, #8 ] ; Third dot
str r4, [ r3, #12 ] ; Fourth dot
loop
VRAM
GBA
; Draw RGB bands
IOBASE EQU 0x04000000
VIDEO_MODE3 EQU 0x0F03
VRAM_START EQU 0x06000000
AREA rgb,CODE
str r2, [ r1 ]
; R3 VRAM pointer
; R4 color code
; R5 loop counter
ldr r4, =COLOR_RED ; RGB = 0/0/1F RED *2
ldr r5, =LOOP_COUNT ; Reset counter
display_red
add r3, r3, #4 ; Forward VRAM pointer (2*2 bytes)
subs r5, r5, #1 ; Decrement counter
bne display_red ; If NOT EQUAL to zero, then repeat
ldr r4, =COLOR_GREEN ; RGB = 0/1F/0 GREEN *2
ldr r5, =LOOP_COUNT ; Reset counter
display_green
add r3, r3, #4 ; Forward VRAM pointer (2*2 bytes)
subs r5, r5, #1 ; Decrement counter
bne display_green ; If NOT EQUAL to zero, then repeat
ldr r4, =COLOR_BLUE ; RGB = 1F/0/0 BLUE *2
ldr r5, =LOOP_COUNT ; Reset counter
display_blue
add r3, r3, #4 ; Forward VRAM pointer (2*2 bytes)
subs r5, r5, #1 ; Decrement counter
bne display_blue ; If NOT EQUAL to zero, then repeat
loop
add r3, r3, #4 ; Forward VRAM pointer (2 bytes)

str r4, [ r3 ], #4 ; Change the dot color and forward pointer


BLBranch with LinkARMBranch and Link
BL m
BL m"r14"Link Register"lr""LR"

MOV r1, #20
MOV r1, #54
MOV pc, lr ; Return from subroutine
; with result in r0
: gcd
MOV r1, #4
; r0 = gcd(r0, r1)
SWI 0x11 ; terminate
gcd ; subroutine gcd
SUBGT r0, r0, r1 ; when (r0 > r1) r0 -= r1
SUBLT r1, r1, r0 ; when (r0 < r1) r1 -= r0
BNE gcd ; if (r0 != r1) loop back
MOV pc,lr ; return : r0 = gcd(r0, r1)
END
LDR r1, =dststr ; pointer to second string
BL strcopy ; copy the first into second
SWI 0x11 ; and exit
ALIGN ; realign address to word boundary
strcopy
CMP r2, #0 ; check for zero terminator
BNE strcopy ; keep going if not
MOV pc, lr ; return
MOV r1, #20
MOV pc, lr ; Return from subroutine
END

MOV r1, #20
BL secondfunc ; Call second subroutine
RA1 MOV pc, lr ; Return from first subroutine
secondfunc ; Subroutine secondfunc
END

return n * factorial(n-1);
STR R0, [sp], #4 ; n
SUBS R0, R0, #1 ; n - 1R0
BEQ fact1 ; if (n == 1) goto fact1
BL fact ; else fact(n - 1)
factn LDR R1, [sp, #-4]! ; nR1
MUL R0, R1, R0 ; R0 = n * fact(n - 1)
LDR pc, [sp, #-4]! ;
fact1 LDR R0, [sp, #-4]! ; 1=fact(1)R0
LDR pc, [sp, #-4]! ;

BL fact ; fact(3)
SWI 0x11
factBL fact
3BL fact
R0R0factR01LDR pc, [sp, #-4]!(3)
LDRfactnR0 = 1*2 = 2(2)
factnR0 = 2*3 = 6(1)R0fact(3)6
lrr0calling convention
r0:
ARMregister variablecaller save registercallee save registerABABABBBBAcallersaveABABcalleesaveA
factorialr0r4
STMIAST(STore) M(Multiple) I(Increment) A(After)storeafterspincrementIAD(Decrement)B(Before)
LDMDB sp!, {r4, pc}
factorial
BL fact ; fact(3)
SWI 0x11
SUBS r0, r0, #1 ; n - 1r0
BEQ fact1 ; if (n == 1) goto fact1
BL fact ; else fact(n - 1)
factn MUL r0, r4, r0 ; r0 = n * fact(n - 1)
LDMDB sp!, {r4, pc} ; return
fact1 MOV r0, #1 ; r0 = 1 ( = fact(1) )
LDMDB sp!, {r4, pc} ; return
AREA stack,DATA,READWRITE
{r4,lr=r14}
callee save registercaller save register
r0, r1, r2, r3 a1, a2, a3, a4
r4, r5, r6, r7, r8 v1, v2, v3, v4, v5


BL fact ; compute fact(3)
SWI 0x11
MOV r4, r0 ; r4 = n
SUBS r0, r0, #1 ; r0 = n-1
BEQ fact1 ; if (n == 1) goto fact1
BL fact ; else fact(n - 1)
factn MUL r0, r4, r0 ; r0 = n * fact(n - 1)
LDMDB sp!, {r4, pc} ; return
fact1 MOV r0, #1 ; r0 = 1 ( = fact(1) )
LDMDB sp!, {r4, pc} ; return
END
main1
execution
0001 NE Not equal Z clear
0010 CS/HS Carry set / unsigned higher or same C set
0011 CC/LO Carry clear / unsigned lower C clear
0100 MI Minus / negative N set
0101 PL Plus / positive or zero N clear
0110 VS Overflow V set
0111 VC No overflow V clear
1000 HI Unsigned higher C set and Z clear
1001 LS Unsigned lower or same C clear or Z set
1010 GE Signed greater than or equal N equals V
1011 LT Signed less than N is not equal to V
1100 GT Signed greater than Z clear and N equals V
1101 LE Signed less than or equal Z set or N is not equal to V
1110 AL Always any
N Z C V
001 MLA Multiply-accumulate (32-bit result) Rd := (Rm * Rs + Rn) [31:0]
100 UMULL Unsigned multiply long RdHi:RdLo := Rm * Rs
101 UMLAL Unsigned multiply-accumulate long RdHi:RdLo += Rm * Rs
110 SMULL Signed multiply long RdHi:RdLo := Rm * Rs
111 SMLAL Signed multiply-accumulate long RdHi:RdLo += Rm * Rs
fetch
decode
execute
ti
me
1
fetch
decode
execute
fetch
decode
execute
2
3
in
struction
instruction
fetch
instruction
fetch
Thumb
decompress
ARM
decode
reg
read
reg
write
shift/ALU
reg
write
shift/ALU
execution
0001 NE Not equal Z clear
0010 CS/HS Carry set / unsigned higher or same C set
0011 CC/LO Carry clear / unsigned lower C clear
0100 MI Minus / negative N set
0101 PL Plus / positive or zero N clear
0110 VS Overflow V set
0111 VC No overflow V clear
1000 HI Unsigned higher C set and Z clear
1001 LS Unsigned lower or same C clear or Z set
1010 GE Signed greater than or equal N equals V
1011 LT Signed less than N is not equal to V
1100 GT Signed greater than Z clear and N equals V
1101 LE Signed less than or equal Z set or N is not equal to V
1110 AL Always any
Branch Interpretation Normal uses
BNE Not equal Comparison not equal or non-zero result
BPL Plus Result positive or zero
BMI Minus Result minus or negative
BCC
BLO
Unsigned comparison gave lower
BVC Overflow clear Signed integer operation; no overflow occurred
BVS Overflow set Signed integer operation; overflow occurred
BGT Greater than Signed integer comparison gave greater than
BGE Greater or equal Signed integer comparison gave greater or equal
BLT Less than Signed integer comparison gave less than
BLE Less or equal Signed integer comparison gave less than or equal
BHI Higher Unsigned comparison gave higher
BLS Lower or same Unsigned comparison gave lower or same
cond
up/down
pre-/post-index
_1153839304.doc
Branch
Interpretation
BNE
BPL
Plus
Unsigned comparison gave lower
BVC
BVS
BGT
BGE
BLT
BLE
BHI
Higher
_1153914333.doc
Opcode
[31:28]
Mnemonic
extension
Interpretation
0000
EQ
C set
1001
LS
1010
GE
N equals V
1100
GT
1101
LE
Z set or N is not equal to V
1110
AL
Always
any
1111
NV
100
UMULL