Journal of the Korean Physical Society, Vol. 39, No. 6, December 2001, pp. 1100∼1102

Analysis and Modeling of the Data Retention Characteristics ofthe Stacked-gate Flash EEPROM Cell with an ONO Inter-Poly Dielectric

Jang Han Kim∗ and Jung Bum Choi

Department of Physics, Chungbuk National University, Chongju 361-763

Bong Jo Shin, Ikguen Choi and Keun Hyung Park

School of Electrical & Computer Engineering, Chungbuk National University, Chongju 361-763

Sung-il Yang

School of Electrical and Computer Engineering, Hanyang University, Ansan 425-791

(Received 21 September 2001, in final form 25 October 2001)

A new empirical model for the decrease of the threshold voltage due to the spontaneous loss ofthe charge stored in a floating gate of the stacked-gate flash EEPROM cell with an ONO (oxide-nitride-oxide) inter-poly dielectric is proposed. In the model, the decrease of the threshold voltageis expressed as ∆VT = β0t

me−Ea/kT , where t, k, and T are the bake time, the Boltzmann constant,and the absolute bake temperature, respectively. The constant β0, the exponent of the bake timem and the activation energy Ea have been determined to be 3.63×104 V, 0.332, and 0.54 eV,respectively, by fitting the measurement data to the model. The measurement data for the variousbake times and temperatures are fit superbly with the model, especially for the initial phase of thecharge-loss processes. Therefore, the model is sure to be very useful in anticipating precisely thedevice lifetime as affected by the charge loss.

I. INTRODUCTION

In general, floating gate nonvolatile memory devices,such as EPROM, EEPROM, and flash EEPROM devicesare required to retain the stored data over ten years un-der normal operating conditions [1,2]. Also, the degra-dation of the data retention capability has recently be-come one of the most important reliability issues with thescaling-down in the flash EEPROM. As is well known, anONO (oxide-nitride-oxide) stacked film has been widelyused as the inter-poly dielectric layer in stacked-gateflash EEPROM cells because it has the advantages ofa higher coupling ratio and a better charge retention ca-pability compared with the polysilicon oxide used earlierin the EPROM devices [3,4].

The inter-poly dielectric is known to be the main pathof charge leakage in a programmed cell since it is moredefective compared with a thermal gate oxide grown onsingle crystalline silicon [1,5]. Thus, the data reten-tion capability is generally determined by the charge-loss mechanism through it. Therefore, it is very impor-tant to understand the charge-loss mechanism through

∗E-mail: kimjh7156@hanmail.net

the inter-poly dielectric in order to forecast the devicelifetime as affected by the charge loss under normal op-erating conditions. The lifetime is generally defined tobe the time that it takes for the threshold voltage of theprogrammed cell to drop by 0.5 V under normal oper-ating conditions, and commercial products should havelifetimes larger than 10 years.

As is well known, the device lifetime as affected bythe charge loss is measured by using a high-temperatureacceleration test, where the shift of the threshold voltageat normal operating temperatures is obtained based on amodel by extrapolating from the data measured at highertemperatures [6]. Hence, it is very important to set up anaccurate model to evaluate the device lifetime correctly.In this paper, a new model for the shift of the thresholdvoltage of a programmed flash EEPROM cell is proposedand evaluated.

II. EXPERIMENTS

For these studies, stacked-gate flash EEPROM cellswith ONO inter-poly dielectric layers were fabricated us-ing 0.35 µm CMOS processes, and the effective channellength and width were 0.45 and 0.65 µm, respectively

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Analysis and Modeling of the Data Retention Characteristics of · · · – Jang Han Kim et al. -1101-

Fig. 1. The decrease of the threshold voltage versus baketime for various bake temperatures.

[7]. In addition, the gate oxide and the ONO inter-polydielectric layer are about 10 and 25 nm thick, respec-tively. Our process for ONO stacked films was similar tothat reported recently [8]. Firstly, the selected 30 sam-ple devices were programmed to a predetermined thresh-old voltage (i.e., 7.0 V) by using the channel hot elec-tron injection (CHEI) method. Then, they were bakeat one of various temperatures, such as 200, 240, 270,300, 320, 340, and 360 ◦C, for predetermined times ina heat-flow oven with a temperature controllability of4T = ±1 ◦C, and the shift of the threshold voltage wasmeasured by using an HP4156A device parameter ana-lyzer.

III. RESULTS AND DISCUSSIONS

The measurement results for the decrease of thethreshold voltage versus bake time for various bake tem-peratures is shown in Fig. 1. It can be seen from theprofiles that 4VT is linearly proportional to tm. Hence,4VT can be expressed as

4VT = βtm, (1)

where β and m are bake-time-independent parameters.The slopes of the profiles are almost equivalent indepen-dently of the bake temperature. Thus, the parameter mhas been determined to be 0.332 from the average valueof the slopes. On the other hand, the parameter β isfound to strongly depend on the bake temperature, asshown in Fig. 2 where the values of β obtained by fittingthe measurement data to the model of the Eq. (1) areplotted as a function of the bake temperature. The figureclearly shows that the parameter β is exponentially pro-portional to the inverse of the bake temperature. Hence,β can be expressed as

β = β0e−Ea/kT , (2)

Fig. 2. Arrhenius plot of the β values which are obtainedby fitting the measurement data to the model.

where β0 is a temperature-independent constant, Ea isthe activation energy, T is the absolute bake temper-ature, and k is the Boltzmann constant. In addition,values of 3.63×104 for β0 and and 0.54 eV for Ea weredetermined from the profile in Fig. 2.

If Eq. (2) is put into Eq. (1), the equation for 4VTcan be expressed as

4VT = β0tme−Ea/kT . (3)

Fig. 3 shows the measurement results and the simulationresults using Eq. (3) for various bake times and temper-atures. As expected, the measurement data fit the modelvery well initially, but gradually deviate from the modelas 4VT increases with increasing bake time for all thetested temperatures. The higher the bake temperatureis, the earlier this phenomenon occurs. Practically, thedependency of 4VT on the bake time becomes quite dif-ferent in the second phase of charge-loss, which impliesthat the dominant mechanism of charge-loss in the sec-ond phase is different from that in the initial phase, asreported previously in the literature [2,9]. Here, it shouldbe noticed that the most needed model for device appli-cations is one for 4VT in the initial phase, not in thesecond phase. As expected, there is no valid reason tostudy charge-loss processes in the second phase becauseno charge-loss process must be in progress in the secondphase to pass the data retention test.

As shown in Fig. 4, there are four major mecha-nisms of charge-loss through the ONO dielectric layerin a stacked-gate flash EEPROM cell [2,3,10]. Leakagepath (1) is thermionic emission of electrons stored in thefloating gate over the bottom oxide of the ONO layer.Leakage path (2) is the detrapping of electrons trappedduring the programming at the interface between thebottom oxide and the internitride, and their movementtoward the top oxide. Leakage path (3) is the movementof electrons trapped during the programming inside the

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Fig. 3. Comparison of the calculated versus the measured4VT .

Fig. 4. Charge conduction mechanisms through the ONOinter-poly dielectric in the stacked-gate flash EEPROM cell.

much more trapping prone internitride layer toward thetop oxide. Finally, leakage path (4) is the injection ofholes from the control gate to the internitride throughthe top oxide by direct tunneling. As shown in Fig. 3,the decrease of the threshold voltage is very fast in theinitial phase of the phenomenon, and is believed to bedue to the intrinsic characteristics of charge-loss mecha-nisms (2) and (3) which are known to be the dominantmechanisms during the initial phase [2,4].

It is possible to forecast the device lifetime as affectedby charge-loss by using the model. That is, an equationfor the device lifetime can be derived from Eq. (3):

τ = m

√4VTβ0

eEa/kT (4)

From Eq. (4), the lifetime of the test sample devices wasfound to be approximately 94 years under a 125 ◦C op-erating temperature, which seems to be of good enough

quality to satisfy the requirements for data retention.

IV. CONCLUSIONS

Based on the experimental results of the data reten-tion tests for stacked-gate flash EEPROM cells, we de-veloped a new model for the spontaneous decrease of thethreshold voltage. The empirical model can be expressedas 4VT = β0t

me−Ea/kT , where β0 is a temperature-independent constant, Ea is the activation energy, T isthe absolute bake temperature, and k is the Boltzmannconstant. In addition, values of 3.63×104 V for β0, 0.332for m, and 0.54 eV for Ea were determined from theexperimental results. The measurement data for variousbake temperatures and times fit with the model very wellinitially, but gradually deviate from the model as 4VTincreases with increasing bake time. This is because thedominant mechanism of charge-loss in the second phaseis different from that in the initial phase. The model canbe utilized to forecast precisely the device lifetime as af-fected by the charge loss. No simple model such as thisone for the initial phase of the charge loss phenomenonhas been reported before.

ACKNOWLEDGMENTS

This work was supported by MOST (ministry of sci-ence and technology) through the Frontier 21 Programfor Development of Tera-level Nanoscale Devices and byMOE (ministry of education) through the BK21 Pro-gram.

REFERENCES

[1] N. R. Mielke, in Proc. 21th IEEE IRPS, 106 (1983).[2] K. Wu, C. S. Pan, J. J. Shaw, P. Freiberger and G. Sery,

in Proc. 28th IEEE IRPS, 145 (1990).[3] S. Mori, Y. Kaneko, N. Arai, Y. Ohshima, H. Araki, K.

Narita, E. Sakagami and K. Yoshikawa, in Proc. 28thIEEE IRPS, 132 (1990).

[4] C. S. Pan, K. Wu, P. Freiberger, A. Chatterjee and G.Sery, IEEE Trans. Electron Dev. ED-37, 1439 (1990).

[5] B. D. Salvo, G. Ghibaudo, G. Pananakakis, G. Reimbold,F. Mondond, B. Guillaumot and P. Candelier, IEEETrans. Electron Dev. ED-46, 1518 (1999).

[6] H. Nozawa and S. Kohyama, Jpn J. Appl. Phys. 21, L111(1982).

[7] B. J. Shin, K. H. Park, J. H. Kim and J. B. Choi, J.Korean Phys. Soc. 39, 374 (2001).

[8] H. Lim, S. S. Kim and K. S. Chung, J. Korean Phy. Soc.33, 501 (1998).

[9] S. J. Shen, C. C. H. Hsu and M. S. Liand, Jpn J. Appl.Phys. 37(1), 4306 (1998).

[10] T. Watanabe, A. Menjoh, T. Mochizuki, S. Shinozakiand O. Ozawa, in Proc. 23th IEEE IRPS, 18 (1985).