Journal of the Korean Physical Society, Vol. 43, No. 5, November 2003, pp. 892∼897

Fabrication and Process Simulation of SOI MOSFETs witha 30-nm Gate Length

Won-ju Cho,∗ Jong-heon Yang, Kiju Im, Jihoon Oh and Seongjae Lee

Nano-electronic Device Team, Semiconductor Basic Research Laboratory,Electronics and Telecommunications Research Institute, Daejeon 305-350

Kyoungwan Park

Department of Nano Science & Technology, University of Seoul, Seoul 130-743

(Received 7 August 2003)

We have obtained systematic simulation and experimental results for 30-nm-gate-length metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator(SOI) substrates. The two-dimensional process simulation and the device simulation were carriedout to optimize the fabrication process conditions and the device characteristics of 30-nm-gate-length SOI MOSFETs. A new simple source/drain formation technique using the solid-phase dif-fusion (SPD) method was developed. Based on the simulation results and the SPD ultra-shallowjunction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. Theexperimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviorsand superior device scalability.

PACS numbers: 73.40.QvKeywords: SOI, Nano-MOSFET, SPD, Silumation, 30 nm gate

I. INTRODUCTION

As the gate dimension of the silicon metal-oxide-semiconductor field-effect transistor (MOSFET) goesdown into the deep submicron region, the standby powerconsumption of ultra-large-scale integration (ULSI) cir-cuits becomes a serious problem [1, 2]. Complemen-tary MOSFET (CMOS) devices fabricated on silicon-on-insulator (SOI) wafers have attracted a lot of atten-tion because of the advantages of full dielectric isolationand reduced junction capacitance over those on bulk sil-icon wafers in regard to IC applications for low stand-bypower and high performance [3–8]. Moreover, for thefabrication technique involved in SOI MOSFETs, someof the process and the material constraints on the MOS-FET scaling can be removed or relaxed [9, 10]. How-ever, as the device dimensions are further scaled downto submicron and nanometer dimensions, the impor-tance of device structure and fabrication technology in-creases. One of the major challenges to overcome is thesource/drain junction formation technique, which pre-vents short-channel effects for nano-scale devices.

In this paper, we present the characteristics of 30-nm-gate-length SOI nMOSFETs. The device structureand fabrication processes were optimized by using a pro-

∗E-mail: chowj@etri.re.kr

cess simulation and a device characteristics simulationfor the various dimensions of the SOI MOSFETs. Asimple solid-phase diffusion (SPD) technique to form anultra-shallow and low-resistance source/drain junctionwas developed. Based on the optimized device structureand fabrication processes, we successfully fabricated a30-nm-gate-length SOI nMOSFET.

II. EXPERIMENT

The SOI nMOSFETs used in this study were fabri-cated on p-type (100) UNIBOND SOI wafers with a 100-nm top silicon layer and a 200-nm buried oxide. The pro-cess conditions and two-dimensional (2-D) device char-acteristics were simulated using ATHENA (SilvacoTM )and ATLAS (SilvacoTM ), respectively, before the fabri-cation of 30-nm-gate-length SOI MOSFETs. Boron-ionimplantation at 10 keV was carried out to introduce animpurity into the channel region. Then, the top sili-con layer was thinned to 30 nm by thermal oxidation.Mesa-isolation, which is the most widely used isolationtechnique for thick films as well as ultra-thin-film SOIMOSFETs due to the advantages of high integration den-sities and process simplicity, was adopted in this studyto electrically isolate SOI devices. The active region wasdefined in the top silicon layer by using a combination of

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Fabrication and Process Simulation of SOI MOSFETs· · · – Won-ju Cho et al. -893-

photolithography and reactive ion etching (RIE).The etching process started with CF4-based RIE (iso-

topic etching) for smoothing the sharp corners of thesilicon active edge in order to prevent the subthresh-old hump phenomena and ended with Cl2-based RIE(anisotropic etching) to obtain a vertical sidewall pro-file. A phosphorus-doped 150-nm polysilicon film wasdeposited on the 4.5-nm gate oxide as a gate electrode byusing low-pressure chemical-vapor deposition (LPCVD),and a 40-nm silicon-dioxide hard mask was formed onthe polysilicon gate by using thermal oxidation. SAL601, a negative, chemically amplified resist, was usedas an electron-beam (e-beam) resist to form the 30-nmgate line. The etching of the gate electrode was doneby using Cl2-based RIE to obtain a vertical profile. Thephosphorus-doped oxide films, as solid-phase diffusion(SPD) sources, were usually prepared by using chemical-vapor deposition (CVD), but a liquid-state dopant sourcecontaining silicon, oxygen, and phosphorus atoms wasused in this study. Some wafers were coated with adopant source by spin coating after the RCA standardsurface-cleaning processes. A liquid-type dopant sourcewas changed to a solid-state phosphorus-doped silicon-oxide layer on the top of the wafer by using a bakingprocess.

A rapid thermal annealing (RTA) system was usedto diffuse the phosphorus atoms into the silicon [11].Other wafers were doped by phosphorus-plasma-dopingmethod (PLAD) [12], and then activated by using theRTA system. Secondary-ion mass spectroscopy (SIMS)was utilized to analyze the depth profiles of the phospho-rus atoms for various RTA process temperatures. Afterthe formation of interlayer dielectric (ILD) films by usingundoped silica-glass (USG) films and metal interconnec-tions, n+-p junction diodes and 30-nm-gate-length SOInMOSFETs were fabricated. Finally, the electrical char-acteristics were measured using the fabricated devices.

III. RESULTS AND DISCUSSION

1. Process and Device Simulation

In order to investigate the nano-scale SOI MOSFETdevice physics and characteristics, we performed an ex-tensive two-dimensional process simulation and devicesimulation by using ATHENA and ATLAS, respectively.Figure 1 show the ATLAS simulation results for the sub-threshold Id-Vg curves, the subthreshold swing, and thethreshold voltage of SOI MOSFETs as functions of thegate lengths for various channel thicknesses. The chan-nel doping concentration was 1 × 1015 cm−3 in thesesimulations. As the gate length was decreased to 20nm, the short-channel effects became serious becausethe roll-off of threshold voltage and the subthresholdswing increased. On the other hand, thinner SOI channelwas more effective for suppress the short-channel effects.

Fig. 1. Simulation results for the (a) subthreshold Ids-Vg curves, the (b) subthreshold voltage swing, and the (c)threshold voltage of SOI MOSFETs as functions of the gatelengths for various channel thicknesses.

However, because control of top silicon layer and of thethreshold voltage of SOI MOSFETs is very sensitive tosilicon-layer thickness variations, channel doping is es-sential to suppress the short-channel effects in nano-scaleSOI MOSFETs.

Figure 2 shows the ATLAS simulation results for thesubthreshold Ids-Vg curves for the 30-nm-gate-lengthSOI nMOSFET as a function of the channel doping con-centration. The channel thickness in this simulation wasfixed at 30 nm. A channel doping concentrations of3 × 1018 cm−3 was found to be required to suppress

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Fig. 2. Simulation results for the subthreshold Ids-Vg

curves for the 30-nm-gate-length SOI nMOSFET for variouschannel doping concentrations.

Fig. 3. Schematic cross-section of a 30-nm-gate SOI MOS-FETs and impurity profiles along the channel as simulatedby the ATHENA process simulator. The source/drain dopingwas performed by using the phosphorus solid-phase diffusiontechnique.

the short-channel effects on the characteristics of 30-nm-gate-length SOI MOSFETs.

Figure 3 shows the process simulation results obtainedby using the ATHENA process simulator. A schematiccross-section view of the 30-nm-gate-length SOI MOS-FETs is shown in Fig. 3(a). The source/drain junctionwas formed by using SPD and phosphorus-doped oxidefilm because the SPD technique is known to be an effec-tive method for fabricating ultra-shallow and defect-freejunctions. The gate oxide thickness, the channel thick-ness, and the channel doping concentration were fixed at5 nm, 30 nm, and 3 × 1018 cm−3, respectively. Figure3(b) shows impurity profiles along the channel surfacesof SOI MOSFETs. A sufficient phosphorus concentra-tion at the source/drain extension region and an effec-tive channel length of 20 nm were obtained from theoptimized process simulation.

Figure 4 shows the ATLAS device simulation resultsfor the 30-nm-gate-length SOI nMOSFETs shown in Fig.

Fig. 4. Ids-Vg and Ids-Vd characteristics of the simulated30-nm-gate-length SOI MOSFETs using a phosphorus SPDsource/drain region.

3. Good I-V characteristics were obtained as shown inFig. 4(a) and Fig. 4(b). The curves of the drain currentversus the gate voltage at drain biases of 0.1 V and 1 Vare shown in Fig. 4(a). The threshold voltage is 0.28 V,and the subthreshold slope is about 120 mV/dec. Fig-ure 4(b) shows the simulated output characteristics of30-nm-gate-length SOI nMOSFETs for several gate bi-ases. The output current of the device is 750 µA/µm atVgs-Vth = 1.2 V and Vds = 1.2 V. Using these resultsfrom the process and the device simulations, we opti-mized the device structure and the process conditionsfor fabricating 30-nm-gate-length MOSFETs on ultra-thin SOI substrates and estimated the characteristics ofdevice operation.

2. Device Fabrication

According to the process and device characteristicssimulations, we performed a boron-ion implantation witha dose of 2 × 1013 cm−2, at an acceleration energy of 10keV, and a tilted angle of 7◦ into the SOI top siliconlayer to obtain a doping concentration of 3 × 1018 cm−3.

Fabrication and Process Simulation of SOI MOSFETs· · · – Won-ju Cho et al. -895-

Fig. 5. SIMS profiles of phosphorus in SOI substrates forthe 950 ◦C, 30 s RTA samples.

Figure 5 shows the phosphorus profiles in the SOI sub-strates for SPD and PLAD. The RTA was carried out at950 ◦C for 30 s, and the SIMS was utilized to analyzethe depth profiles of the phosphorus for various RTA pro-cess temperatures. The junction depth Xj and the sheetresistance Rs were 33 nm and 270 ohm/cm2 for SPD.In comparison, phosphorus profiles formed by PLAD arealso shown. The PLAD profiles showed a high surfaceconcentration while the junction depth and abruptnesswere degraded compared to those for the SPD profiles.The inset shows the relationship between the sheet resis-tance and the RTA temperature. The sheet resistance ofthe phosphorus SPD sample was determined using theVan der Pauw technique. As the temperature of RTAwas increased from 850 ◦C to 1000 ◦C, the sheet resis-tance decreases from 2000 ohm/cm2 to 130 ohm/cm2.

Figure 6 shows the cross-sectional TEM images of thehighly doped phosphorus region obtained by PLAD orSPD after rapid thermal annealing at 950 ◦C for 30 s.The junction formations in modern MOS process tech-nology use ion implantation or plasma doping. However,such processes introduce crystal defects in the substrate.As a result, the generated crystal defects act as originsfor the leakage current in MOSFET devices and limit theintegrated device’s performance. Therefore, an alterna-tive method is required to make use of the advantages ofSOI devices. As Fig. 6 shows, crystal defects, such asdislocation loops, were found near the surface region forPLAD. On the contrary, crystal defects was not observedfor SPD, as shown in Fig. 6(b), so we conclude that SPDis an effective method to form damage-free ultra-shallowsource/drain junctions in nano-scale SOI MOSFETs.

Figure 7 shows a schematic diagram and the electri-cal characteristics of an n+-p diode fabricated on a SOIsubstrate by using SPD and PLAD with the RTA tem-peratures as a parameter. The forward bias current isobserved to depend on the RTA temperature, as shownin Fig. 7(b). As the RTA temperature was increased,the forward bias current increased while the reverse bias

Fig. 6. Cross-sectional TEM images of the phosphorushighly doped region by using (a) PLAD and (b) SPD after a950 ◦C RTA for 30 s in a N2 ambient.

current remained almost constant. The increase in theon-current could be attributed to a reduction in the sheetresistance at the high RTA temperature. On the otherhand, the PLAD samples showed lower forward bias cur-rents and higher reverse bias currents than the SPD sam-ples. The current ideality factor of the junctions formedby using SPD and PLAD were 1.1 and 1.7 at a forwardbias voltage of 0.1 V, respectively. The large reversebias current and current ideality factor for PLAD are at-tributed to the crystal defects generated by the PLADprocess. As Fig. 5 shows, the crystal defects were notcompletely annealed out, even by the high-temperaturepost-PLAD annealing. However, the SPD method doesnot create defects during junction formation. Conse-quently, these results clearly show that the SPD processis superior to the plasma-doping process for the forma-tion of diodes. Figure 7(c) shows a plot of 1/C2 versusthe reverse bias for diodes fabricated by using SPD atan RTA temperature of 900 ◦C. For an ultra-shallow andabrupt junction (one-sided step junction), the square ofthe reciprocal of capacitance induced by space charge indepletion region is proportional to the reverse bias volt-age, which is given by

(φi − Va) =qεsNd2C2

,

where φi is the built-in potential, εs is the permittivityof silicon, and Nd is the doping concentration of the SOI

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Fig. 7. Schematic diagram and electrical characteristicsof the n+-p diode fabricated on SOI substrate by using SPDand PLAD with the RTA temperature as a parameter.

[13]. As Fig. 7(c) depicts, the 1/C2-V curve is linear,which demonstrate that the junctions fabricated by usingSPD have the feature of being one-sided step junctions.

Figure 8 show the scanning electron microscope (SEM)images of fabricated 30-nm-gate-length SOI nMOSFETs.A phosphorus-doped polysilicon film was deposited onthe gate oxide as a gate electrode; then a 40-nm silicon-dioxide layer was deposited on the polysilicon layer usedas a hard mask for the dry-etching process. A negativeelectron-beam (SAL 601) resist was used to generate the30-nm gate-line pattern. The definition of a fine gateline was carried out by electron-beam lithography (EBL),

Fig. 8. SEM images of 30-nm-gate-length SOI MOSFETswith a simple source/drain structure fabricated by using theSPD technique.

Fig. 9. Ids-Vg and Ids-Vd characteristics of the fabricated30-nm-gate-length SOI MOSFETs using a phosphorus SPDsource/drain extension region.

and the etching of the polysilicon layer was carried outby using a Cl2-based ICP RIE (ULTECH, USE-150 ICPsystem) process. Consequently, we successfully formeda vertical 30-nm gate electrode based on electron-beamlithography and dry etching.

Figure 9 show the Ids-Vg and Ids-Vds characteristicsof the fabricated 30-nm-gate-length SOI MOSFETs witha phosphorus SPD source/drain extension region. Inspite of the simple source/drain structure and the ex-

Fabrication and Process Simulation of SOI MOSFETs· · · – Won-ju Cho et al. -897-

tremely short channel length, the experimental resultsshow good transistor behaviors. As compared with thesimulation results of Fig. 4, the subthreshold character-istics of the fabricated device show a relatively large sub-threshold swing, which is mainly attributed to the highdensity of interface states [14]. This means that a fur-ther improvement in the process conditions is necessaryfor the fabrication of high-performance sub-30-nm-gate-length SOI MOSFETs. Furthermore, a degradation ofthe output current was observed in the Ids-Vds charac-teristics due to the high parasitic resistance. Because thethickness of the SOI wafer was thinned to 30 nm and thelength between the source/drain contact and the gateline was larger than 40 um, as shown in Fig. 8(a), thevoltage drop across the parasitic source/drain resistanceincreased. Therefore, a further reduction in the seriesresistance by applying a silicide process is required toincrease the current drivability of our 30-nm-gate-lengthSOI nMOSFETs.

IV. CONCLUSIONS

We have reported systematic simulations and exper-imental results for SOI nano-MOSFET devices. In or-der to optimize the fabrication process and the devicecharacteristics of 30-nm-gate-length SOI MOSFETs, wecarried out the two-dimensional process simulations anddevice simulations. A new simple source/drain forma-tion technique using the SPD method was developed.Based on device-structure and fabrication-process opti-mization, we used the SPD ultra-shallow junction for-mation technique to successfully fabricated 30-nm-gate-length SOI nMOSFETs. The experimental results forthe 30-nm-gate-length SOI nMOSFETs showed goodtransistor characteristics and superior device scalabilityfor nano-scale MOS devices.

ACKNOWLEDGMENTS

This work was supported by the national program forTera-level Nanodevices of the Ministry of Science andTechnology as one of the 21st century Frontier Programsand by the Information Technology Initiative program ofthe Ministry of Information and Communication.

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