asada-san, r. brederlow, j.a. carballo, kashiwagi-san 2004 work in progress – do not publish 1...

Asada-san, R. Brederlow, J.A. Carballo, Kashiwagi-san

2004 Work in Progress – Do Not Publish 1

Design TWG 2004-2005 Goals

1. Development of design color tables- Design technology requirements- Design technology solutions

2. Revision of tables and content- Addition of DFM (“Technology Access”) section

- Cost/ROI model improvement - e-RAM content consistency and model accuracy- New DSP/MCU content

- Further SIP content and alignment with SoC - Reorganize AMS + modeling/simulation

3. Application / product alignment - Alignment with product (NEMI) roadmap (with other

TWGs)



Design TWG 2004-2005 Strategy

Goal 2004 Work 2005 Work Chapter

1. Develop color tables

-Extended general requirements

-Preliminary “general” solutions

Development of detailed color tables

-requirement (quantit.)

-solutions (qualit.)

Design

2. Revise tables and content

- Revise e-RAM model

- Better SIP content

-SoC cost model

-Preliminary DFM section

-Preliminary DSP/MCU

-Embed AMS & modeling

-Complete DFM ("Technology Access“) section (DFM, CD control, libraries,…)

-Total cost/ROI model

- Complete DSP/MCU

Design

3. Align with applications

-Align existing requirements to PDA model

-Identify mapping products-ITRS drivers

-Complete set of ITRS drivers on an SoC application basis

System drivers



Back Up Slides



1. Design Color Table Development

Current requirements / solutions tables by

– General

– Design process

– System level

– Logic, circuit, and physical design

– Verification

– Test Size ~ 50 requirements, 50 solutions



1. Design Color Table Development

Feedback summary (Japan)– Agree on definitions of productivity and power– Consistency / links with ORTC– Decomposition of requirements– Number of requirements and target audience– Alternative break-downs (by design objectives, by fabrics)

Feedback summary (Europe)– Clearly define each parameter

• e.g. (1 sentence in e-RAM section

– Choose driver (fabrics, app., objective)• Include that as comment to table rows or make extra row

– Cost/area as requirement



1. Design Requirements Color Tables

Requirement Comments SRC Leader

Complexity (system) Xtors/chip Combine from ORTC/app ORTC.. Smith

SoC Productivity - design cycle (mo) Improvement

%, By application

Include re-spins?

G.Smith

Carballo

%SW in overall productivity - design cycle (mo) Improvement

Include SW

% by application

G.Smith

Carballo

Productivity - Logic Mtx per designer-year improvement

% Smith

Carballo

Power efficiency - dynamic power reduction beyond scaling

Definition, Precond, assumption needed PIDS Table value ÷ Target value

PIDS+ Brederlow + Jap

Power efficiency - standby power reduction beyond scaling (X)

PIDS+ Brederlow + Jap

Area density – increase beyond scaling (X)

PIDS+ Brederlow

Manufacturing interface - %cov. Put in “Test” table Kahng

Design cost (improvement, norm) Smith

General requirements




Requirement Comments Req SRC Leader

# of verifiable states Growing Productivity

% states covered (non-f) Growing? Productivity

# of diverse fabrics modeled simultaneusly (eDRAM, etc.)

Yield/Cost

Productivity

# of factors to optimize at once

Area, Speed, Power, Test t,Y

Productivity

# of tools under single API Eg. Sim(A+D)+FV

Eg. P&R+STA

Productivity

Manageable power density Clarify Power

Analyzable noise frequency Clarify ?

% cross-chip variability Yield/cost

% manufacturability improvement

Yield/cost

Design process requirements




Requirement Comments Info source Leader

Analog scalability (versus digital?)

Clarify

% design block reuse

# of technologies implemented (eDRAM, eFPGA, SiGe, optical, MEMS)

Clarify

System-level design requirements





FOM for incremental analysis Define i. analysis

FOM for interconnect planning Define i.planning

% asynchronous global signaling Clarify %

“Tolerable” Defect density

% parameter uncertainty Clarify matching/%

AC/DC power reduction > scaling Repeated before

MTTF contribution (reliability) Define contribution

# simult. analysis objectives Area, Power, etc.

# of circuit families supported Important?

% analog content synthesized

% design on predictable platforms

% adaptive/self-repairing circuits

Logic / circuit / physical design requirements





Verifiable design size (gates)

% logic formally verified

% coverage for largest design

% effort in SW verification

% reuse of verification code

% acceptable cost increase

% verification time variability

% concurrency

Average granularity of block

% design formally verified

% analog formally verified

# of technologies simult. verified (MEMS, EO or EB devices, etc.)

Verification requirements





Max. at-speed test frequency

Max. serial I/Os test frequency

% chip self-tested

% logic with BIST

% AMS with BIST

% yield improvement through test

% block test reused in SoC

# technologies tested on same chip (MEMS, EO, etc.)

% defects detected by burn-in test

P, S—DFT and fault tolerant design for logic soft errors

% chip self-reconfigurable

Test requirements



1. Design Solutions Color Tables


High-freq. full chip noise analysis

Concurrent multi-factor optimization

Automated package analysis

Integrated A/D flows

Parallel processing-aware flows

Variability across entire flow

Automated mask correction

Automated SW+HW synthesis

Design process solutions





System-level component reuse

Automated interface synthesis

Explicit system-level energy-performance trade-off

Multi-fabric implementation planning (AMS, RF, MEMS…)

SW-SW co-design and verification

On-chip network design methods

System-level design solutions





Fully incremental analysis

Synthesis and timing accounting for variability (statistical?)

Circuit/layout enhancement accounting for variability

Macro/chip leakage analysis

Power management analysis & logic insertion SOI SoC tools

Analog synthesis (circuit/layout)

Cost-driven implementation flow

Implementation tools for sensors

Non-static logic implementation

Platform-specific tools

Logic, circuit and physical design solutions





Semi-formal verification

Problem difficulty characterization

Bug coverage determination

CAD support for D-f-Verifiability

Hierarchical verification algorits.

Predictable verification time with known cost penalty

MPU-specific verification

Concurrent multi-core processor verification

A/D/multi-fabric automated co-verification

Design verification solutions





DFT, test, measurement…for I/O

DFT for low-cost ATE

Power management during test

DFT for Signal integrity

DFT, BIST for core-based SOC

e-memory B-I-S-diagnosis+repair

AMS DFT/BIST

SOC/SIP test with MEMS/EO

On-chip multi-GHz RF circuit test

Design for burn-in defect screens

DFT for logic soft errors

System-level on-line test

Timing-related noise fault models

Design test solutions



2. Design SIP content, SoC alignment

SIP – alignment and data issues

SoC– How to align with SIP, migration



3. Design "Technology Access" Section

Content– DFM

– Libraries

– Cost

– CD variability survey?

Possible leads– Andrew Kahng (driver)

– J. Mainard & S. Nassif (IBM) - unconfirmed



3. Design Possible Section Structure

Design technology

Scope “Grand challenges” DT challenges

Design costDesign cost Productivity

Power

Manufacturing int.

Interference

Error tolerance

Design process

System-level design

Implementation

Verification

Design Test

Technology access

Cross-cutting

Cost?

Key

New position/section

Needed?

Modeling/sim?

Libraries/modelsDFMCost

Simple “enumeration” of challenges



4. Design Embedding of Content

AMS

– Elimination of separate AMS section– Incremental immersion of AMS content in

document– Possible lead Peter

Modeling/simulation– Embed lone paragraph withing rest of document

– Add to list of cross-cutting challenges



5. Design Cost/ROI model

Agreement on definition of cost Additions of non-cost metrics

– What metrics ROI?

– How to get data

– Possible leaders Smith, Carballo



6. System Drivers DSP/MCU content

From “F” to logic-sensible length scale (e.g., contacted M1). – Will impact SRAM A-factor model and logic density model

SRAM model– Recalibrate to the last few years of data (Dennis, Andrew)

Add more “design innovation”– Would increase chip white-space unless more “overhead” or – increase growth rate of SRAM and logic transistor counts look at spreadsheet

Key questions– Is multi-core model (2X SRAM+logic per node) still OK? – Calibration data (e.g. 140mm2, 310mm2 still correct?) – Date of deployment and model implications of eDRAM– Redoing the MPU model = “server-desktop” vs. “mobile”



7. System Drivers e-RAM model

e-memory dynamic power roadmap

– 2010 discontinuity– Review dynamic power calculation model (all memories)

e-memory static power roadmap

– System Drivers value <> PIDS table+model value– Review leakage power calculation model– Impact of Vt variations?

FRAM

– Widely used embedded, already integrated in SoC– Derive FRAM roadmap (like SRAM, FLASH, e-DRAM)

MRAM? Flash

– Andrew digging info on NOR-Flash



7. System Drivers e-RAM model

e-memory dynamic power roadmap

– 2010 discontinuity problem was spreadsheet mistake– Review dynamic power calculation model (all memories)

e-memory static power roadmap

– System Drivers value <> PIDS table+model value– Review leakage power calculation model– Impact of Vt variations?

FRAM

– Widely used embedded, already integrated in SoC– Derive FRAM roadmap (like SRAM, FLASH, e-DRAM)

MRAM? Flash

– Andrew digging info on NOR-Flash



7. System Drivers e-RAM model/content

Consistency Accuracy Content

– DRAM

– SRAM

– Flash



8. System Drivers Product Alignment (NEMI)

Will improve alignment with other documents – With systems chapter, based on each systems driver– With NEMI emulators, based on each NEMI emulator

Issues– Design organized by challenges and traditional EDA fields– Systems drivers based on “fabric/platform”– NEMI emulators based on “product”, NEMI is US organization

Actions (tentative)– Talk with NEMI about geographical composition– Aggressively improve each section’s alignment with s. drivers– Improve understanding of NEMI-ITRS drivers connection – Possible lead Andrew



Drivers

SoC/SIP

HPMT?LC-LP

MPU DSPAMS eMemory

Gaming PDANP Wireless

Architecture

Applications (NEMI)

Fabrics (ITRS)“MEMS”

“BioChip”

“Futures”


“Current”



8. System Drivers Product Alignment (NEMI?)

Drivers

MPU DSPAMS eMemory

Gaming PDANP Wireless

Architectures

Applications (NEMI?)

Fabrics (ITRS)“MEMS”

“BioChip”

“Futures”“Current”

High performance Low power

A1A2A3A4

α1 β1 γ1 δ1



8. System Drivers Product Alignment (NEMI?)

Year

Parameter

A1

A2A3

A4




Example product – System Driver’s Reference Design

– Personal digital assistant (PDA)

Composition– CPU

– DSP

– Peripheral I/O

– Memory

0.18um / 400MHz / 470mW (typical)

CPU

I-cache32KB

D-cache32KB

I2C

FICP

USB

MMC

UART AC97

I2S

OST

GPIO

SSP

PWM RTC

DMA controller

LCDCnt.

MEMCnt.

PWR CPG

SDRAM64MB

Flash32MB

LCDPeripheral

4 – 48MHz

Data Transfer100MHz

Processor

Max 400MHz6.5MTrs.

USB

MMC

KEY

Sound




SoC challenges MPU challenges AMS challenges

Productivity improvement

Power management

System-level integration

Test methodology

Design/verification productivity

Power management/delivery

Input/output bandwidth

Multi-core organization

Parametric yield

Skills and productivity

Decreasing supply

Increasing analog content

Higher speed

Crosstalk

Parametric variations



Interaction With Other TWGs (PIDS, PIDS/Litho/FEP, Test, Assembly/Packaging,

Yield)TWG Needed info TWG Contact

1. Development of color tables What %perf/power growth is design? 0

Are color tables OK?

“Tolerable” defect density

PIDS

Test

Yield

2. Further SIP content and alignment with SoC

Provide # & speed I/Os, max. power per application?

Assembly/ packaging Test

3. Addition of "Technology Access"

From PIDS Dev. param. variability generate high-level DTWG data (also (1.))

“Tolerable” defect density. Design rules.

PIDS/ Litho/ FEP

Yield

4. Embedding of AMS and modeling/simulation

Difficult to do Modeling/ simulation

Peter + Ralf



Interaction With Other TWGs (PIDS, PIDS/Litho/FEP, Test, Assembly/Packaging,

Yield)TWG Needed info TWG Collab/

contact

5. Cost/ROI model improvement

System Drivers

What part is design V. manuf V. test V. packaging? (PDA)

PIDS+ test + factory i. + Alan

6. Improved DSP/MCU content What part of 70% growth is design? 0 ORTC

PIDS

7. e-RAM content consistency and model accuracy

Vt variation, Igate, Flash data, bits/cell, ECC

Provide #IPs per chip

Read detailed table and say if it’s useful

PIDS

Test

8. Alignment with product roadmap (NEMI?)

Align Systems Drivers to PIDS too

Align by apps/drivers? SoC/SoP migration data

SoC/SoP yield model

PIDS

Assembly/P

Yield



Back-up Slides



Discussion on Cost Versus ROI Should we gather ROI trends?

Appendix Material



Cost Versus ROE/ROI

Investor care about ROE

Assets

Debt

Equity

A = D + ERevenue

Cost/expense

Interest/tax

Net profit

ROE

/. .



ROI versus Cost

Return On Investment a crucial metric

– Cost is not the only variable!

ROI = - I + ∑ Rt - Ct

(1 + r)tt = 1

n

Investment(upfront cost)

CostRevenue

Required return (risk)

Time (years)



$-

$10.0

$20.0

$30.0

$40.0

$50.0

2000 2002 2004 2006 2008 2010 2012

year

cost

($M

)

DT Investment versus Overall costs

2X EDA investment could half total design cost…

– …if it achieves 7% more productivity growth

2X EDA investment½ total cost



ROI Example

SoC

-12000

-10000

-8000

-6000

-4000

-2000

0

2000

4000

6000

8000

1 2 3 4 5 6 7

TimeCum

mul

ativ

e R

OI

Annual return

Cummulative ROI



Cost versus ROI Impact of Time/productivity

TTM increases ROI, as it reduces time parameter

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0% 10% 20% 30% 40% 50%

Productivity improvement

No

rmal

ized

RO

I

1. Higher revenues2. Earlier revenues3. Similar cost!



Cost versus ROI Impact of Uncertainty/Risk

Uncertainty lowers ROI, as it increases perceived risk

0.0

0.2

0.4

0.6

0.8

1.0

1.2

10% 12% 14% 16% 18% 20%

Risk-induced discount rate

No

rmal

ized

RO

I

asada-san, r. brederlow, j.a. carballo, kashiwagi-san 2004 work in progress – do not publish 1...

Documents

design twg

design objectives

design block reuse

existing requirements

normsmith general requirements

revise tables

revision of tables

requirement slide