NES FPGA EMULATION SYSTEM

Ashley GoodDavid GrazianoTim MeyerBen PetersenMatt Saladin

AdvisorsJoseph ZambrenoPhillip Jones

Project Plan

Design and implement the original Nintendo Entertainment System (NES) in reconfigurable hardware

FPGA: Xilinx ML-507 Xilinx development environment Develop the individual NES components in VHDL

CPU PPU

ROM Interface

System Control

Memory

Controller Polling Audio Clock Generation

VGA

Central Processing Unit

CPU components are completed and integrated ALU IFID Branch Logic

Central Processing Unit

Testing Plan Tested

ALU Instruction fetch/decode

CPU as a whole needs to be integrated and tested with ROM file as input

After CPU is fully tested, it will need to be integrated with the PPU and retested

Picture Processing Unit

Picture Processing Unit

Picture Processing Unit

Picture Processing Unit

Things to be done

Integrate components Test in Modelsim Test on FPGA

VGA output From test program From NES

Controller interface Connecting to FPGA

board Accessing

controllers from I/O pins on board

Reading a game file store on CompactFlash card

Semester Plan and Schedule 2/25: Have the CPU and PPU completed and tested

3/8: Full NES Modelsim testing 3/15: VGA output from FPGA 3/15: Controller Interface 3/15: Start on board testing 4/15: On board/full system testing 4/15: Poster 4/29: Design Report