Semiconductor MemoriesIEEE PRESS445 Hoes Lane, P. O. Box 1331Piscataway, NJ 08855-1331IEEEPRESSEditorial BoardJohn B. Anderson, Editor in ChiefP. M. AndersonM. Eden1\1. E. El-HawaryS. FuruiA. H. HaddadR. HerrickG. F. HoffnagleR. F. HoytS. KartalopoulosP. LaplanteR. S. MullerW. D. ReeveE. Sanchez-Sinencio0.1. WellsDudleyR. Kay, Director of Book PublishingJohn Griffin, Senior EditorLisa Dayne,Assistant EditorLindaMatarazzo, Editorial AssistantOrlando Velez, Production EditorIEEESolid-StateCircuitsCouncil,SponsorSSc-c Liaison to IEEE PressStu TewksburyWest Virginia UniversityTechnical ReviewersShri AgarwalJet Propulsion LaboratoriesDavidHoffCypress SemiconductorJim KinnisonJohns Hopkins UniversityRob PenchukAnalog DevicesSemiconductor MemoriesTechnology, Testing,and ReliabilityAshok K. SharmaIEEE Solid-State Circuits Council, Sponsor+IEEEThe Institute of Electrical and Electronics Engineers, Inc., New YorkffiWILEY-~ I N T E R S C I E N C EAJOHNWILEY &SONS, INC.,PUBLICATION 1997THE INSTITUTEOF ELECTRICAL ANDELECTRONICSENGINEERS, INC. 3 Park Avenue, 17th Floor, NewYork, NY 10016-5997Published by John Wiley& Sons, Inc., Hoboken, NewJersey.No part of this publication may be reproduced, stored in a retrieval system, ortransmittedin any formor by any means, electronic, mechanical,photocopying, recording, scanning, or otherwise, except as permittedunderSection 107 or 108 of the 1976 United States Copyright Act, without either theprior written permissionof the Publisher, or authorizationthrough payment ofthe appropriate per-copy fee to the Copyright ClearanceCenter, Inc., 222RosewoodDrive, Danvers, MA01923, 978-750-8400, fax978-750-4470, or onthe web at www.copyright.com. Requests to the Publisher for permissionshould be addressed to the PermissionsDepartment, John Wiley& Sons, Inc.,111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008,e-mail: permcoordinator@wiley.com.For general informationon our other products and services please contact ourCustomer Care Department within the U.S. at 877-762-2974, outside the u.S.at 317-572-3993 or fax 317-572-4002.10 9 8 7 6 5 4Library of Congress Cataloging-in-Publication DataSharma, Ashok K.Semiconductor memories: technology, testing, and reliability /Ashok K. Sharma.p. ern.Includes index.ISBN 0-7803-1000-41. Semiconductor storage devices. I. TitleTK7895.M4S491996621.39'732-dc20 96-6824CIPContentsPreface xiChapter 1Chapter 2Introduction 1Random Access Memory Technologies 102.1 Introduction......................................... 102.2 Static RandomAccess Memories (SRAMs) 122.2.1 SRAM (NMOSand CMOS) Cell Structures . . . . . . . . . . . . . . .. 122.2.2 MOS SRAM Architectures 142.2.3 MOS SRAMCell and Peripheral Circuit Operation 152.2.4 Bipolar SRAMTechnologies . . . . . . . . . . . . . . . . . . . . . . . . . . .. 172.2.4.1 Direct-CoupledTransistorlogic (DCTl) Technology................ 182.2.4.2 Emitter-CoupledLogic (Eel) Technology...... 192.2.4.3 SiCMOSTechnology................................................................ 202.2.5 Silicon-on-Insulator (SOl) Technology 242.2.6 Advanced SRAM Architectures and Technologies . . . . . . . . . .. 282.2.6.1 1-4 Mb SRAMDesigns 282.2.6.2 16-64 Mb SRAMDevelopment... 322.2.6.3 Gallium Arsenide (GaAs) SRAMs 342.2.7 Application-SpecificSRAMs 352.2.7.1 Serially Accessed Memory (Une Buffers) 352.2.7.2 Dual-Port RAMs 362.2.7.3 NonvolatileSRAMs 382.2.7.4 Content-AddressableMemories (CAMs) 382.3 Dynamic RandomAccess Memories (DRAMs) 402.3.1 DRAMTechnologyDevelopment 402.3.2 CMOS DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.3.2.1 1 Mb DRAM(Example) 472.3.3 DRAMCell Theory and AdvancedCell Structures . . . . . . . . . .. 502.3.3.1 TrenchCapacitor Cells 522.3.3.2 StackedCapacitor Cells (STC) 552.3.4 BiCMOS DRAMs 582.3.5 Soft-Error Failuresin DRAMs . . . . . . . . . . . . . . . . . . . . . . . . . .. 602.3.6 Advanced DRAMDesigns and Architectures . . . . . . . . . . . . . .. 62vvi Contents2.3.6.1 A 16 Mb DRAM(Example) 632.3.6.2 ULSI DRAM Developments........ 642.3.7 Application-Specific DRAMs 692.3.7.1 Pseudostatic DRAMs (PSRAMs) 692.3.7.2 Silicon File 692.3.7.3 Video DRAMs (VRAMs) 702.3.7.4 High-Speed DRAMs 712.3.7.5 Application-Specific RAMGlossary and Summaryof Important Characteristics..................................................... 75Chapter 3Chapter 4Nonvolatile Memories 813.1 Introduction 813.2 Masked Read-Only Memories (ROMs) 833.2.1 Technology Development and Cell Programming 833.2.2 ROMCell Structures 853.2.3 High-Density (Multimegabit) ROMs 873.3 Programmable Read-Only Memories (PROMs) 873.3.1 Bipolar PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 873.3.2 CMOS PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 913.4 Erasable (UV)-Programmable Read-Only Memories (EPROMs) 933.4.1 Floating-Gate EPROMCell 933.4.2 EPROMTechnology Developments .. . . . . . . . . . . . . . . . . . . .. 963.4.2.1 1 Mb EPROM(Example) 973.4.3 Advanced EPROM Architectures . . . . . . . . . . . . . . . . . . . . . . . . 983.4.4 One-Time Programmable (OTP) EPROMs 1033.5 Electrically Erasable PROMs (EEPROMs) 1043.5.1 EEPROMTechnologies 1053.5.1.1 Metal-Nitride-Oxide Silicon (MNOS) Memories.................... 1053.5.1.2 Silicon-oxide Nitride-Qxide Semiconductor (SONOS)Memories 1093.5.1.3 Floating-GateTunnelingOxide (FLOTOX) Technology.... 1103.5.1.4 Textured-Polysilicon Technology............................................. 1153.5.2 EEPROMArchitectures 1163.5.3 Nonvolatile SRAM (or Shadow RAM) 1203.6 Flash Memories (EPROMs or EEPROMs) 1223.6.1 Flash Memory Cells and Technology Developments 1233.6.2 Advanced Flash Memory Architectures . . . . . . . .. 128Memory Fault Modeling and Testing 1404.1 Introduction........................................ 1404.2 RAM Fault Modeling 1424.2.1 Stuck-At Fault Model 1424.2.2 Bridging Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1454.2.3 Coupling Faults 1474.2.4 Pattern-Sensitive Faults , 1514.2.5 Miscellaneous Faults 1554.2.6 GaAs SRAM Fault Modeling and Testing . . . . . . . . . . . . . . . .. 1554.2.7 Embedded DRAM Fault Modeling and Testing . . . . . . . . . . . .. 1564.3 RAM Electrical Testing 1584.3.1 DC and AC ParametricTesting . . . . . . . . . . . . . . . . . . . . . . . .. 1584.3.2 Functional Testingand some Commonly Used Algorithms ... 1584.3.3 Functional Test Pattern Selection . . . . . . . . . . . . . . . . . . . . . .. 1744.4 RAM Pseudorandom Testing . . . . . . . . . . . . . . . . . . . . . . . . . .. 176Contents vii4.5 Megabit DRAM Testing 1784.6 Nonvolatile Memory Modeling and Testing 1804.6.1 DC Electrical Measurements 1814.6.2 AC (Dynamic) and Functional Measurements 1824.6.2.1 256K UVEPROM 1824.6.2.2 64K EEPROM 1834.7 IDDQ Fault Modeling and Testing 1854.8 Application Specific Memory Testing. . . . . . . . . . . . . . . . . . . .. 1894.8.1 General Testing Requirements . . . . . . . . . . . . . . . . . . . . . . . .. 1894.8.2 Double-Buffered Memory (DBM) Testing 191Chapter5Chapter6MemoryDesign forTestability and FaultTolerance 1955.1 General Design for Testability Techniques 1955.1.1 Ad Hoc Design Techniques 1965.1.1.1 Logic Partitioning.................................................................... 1965.1.1.2 Input/Output Test Points 1965.1.2 Structured Design Techniques . . .. 1975.1.2.1 Level-Sensitive Scan Design 1975.1.2.2 Scan Path............................................................................... 1995.1.2.3 Scan/Set Logic....................................................................... 1995.1.2.4 Random Access Scan............... 2005.1.2.5 Boundary Scan Testing........................................................... 2025.2 RAM Built-In Self-Test (BIST) 2035.2.1 BIST Using Algorithmic Test Sequence 2055.2.2 BIST Using 13N March Algorithm 2075.2.3 BIST for Pattern-Sensitive Faults . . . . . . . . . . . . . . . . . . . . . .. 2095.2.4 BIST Using Built-In Logic Block Observation (BILBO) 2105.3 Embedded Memory DFT and 81STTechniques 2115.4 Advanced BIST and Built-In Self-Repair Architectures 2165.4.1 Multibit and Line Mode Tests 2165.4.2 Column Address-Maskable Parallel Test (CMT) Architecture .. 2195.4.3 BIST Scheme Using Microprogram ROM 2205.4.4 BIST and Built-In Self-Repair (BISR) Techniques 2225.5 OFT and BIST for ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2285.6 Memory Error-Detection and Correction Techniques 2305.7 Memory Fault-Tolerance Designs . . . . . . . . . . . . . . . . . . . . . .. 241Semiconductor Memory Reliability 2496.1 General Reliability Issues " 2496.1.1 Semiconductor Bulk Failures 2526.1.2 Dielectric-Related Failures . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2526.1.3 Semiconductor-Dielectric Interface Failures 2536.1.4 Conductor and Metallization Failures . . . . . . . . . . . . . . . . . . . . 2556.1.5 Metallization Corrosion-Related Failures . . . . . . . . . . . . . . . . . 2566.1.6 Assembly- and Packaging-Related Failures 2576.2 RAM Failure Modes and Mechanisms 2586.2.1 RAM Gate Oxide Reliability 2586.2.2 RAM Hot-Carrier Degradation 2606.2.3 DRAM Capacitor Reliability 2626.2.3.1 Trench Capacitors.................................................................. 2626.2.3.2 Stacked Capacitors 2646.2.4 DRAM Soft-Error Failures 264viii Contents6.2.5 DRAM Data-Retention Properties 2676.3 Nonvolatile Memory Reliability 2686.3.1 Programmable Read-Only Memory (PROM) Fusible Links . .. 2686.3.2 EPROM Data Retention and Charge Loss . . . . . . . . . . . . . . .. 2706.3.3 Electrically Erasable ProgrammableRead-Only Memories (EEPROMs) 2756.3.4 Flash Memories 2806.3.5 Ferroelectric Memories 2836.4 Reliability Modeling and Failure Rate Prediction . . . . . . . . . . .. 2876.4.1 Reliability Definitions and Statistical Distributions 2876.4.1.1 Binomial Distribution 2896.4.1.2 PoissonDistribution 2896.4.1.3 Normal (or Gaussian) Distribution 2896.4.1.4 Exponential Distribution 2916.4.1.5 Gamma Distribution 2916.4.1.6 Weibull Distribution 2916.4.1.7 Lognormal Distribution........................................................... 2926.4.2 Reliability Modeling and Failure Rate Prediction 2926.5 Design for Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2966.6 Reliability Test Structures 3006.7 Reliability Screening and Qualification 3046.7.1 Reliability Testing 3046.7.2 Screening, Qualification, and Quality Conformance Inspections(OCI) 310Chapter 7 Semiconductor Memory Radiation Effects . . . . . . . . . . . .. 3207.1 Introduction 3207.2 Radiation Effects 3227.2.1 Space Radiation Environments 3227.2.2 Total Dose Effects 3257.2.3 Single-Event Phenomenon (SEP) 3307.2.3.1 DRAMand SRAMUpsets 3337.2.3.2 SEU Modelingand Error Rate Prediction 3357.2.3.3 SEP In-Orbit Flight Data 3377.2.4 Nonvolatile Memory Radiation Characteristics 3447.3 Radiation-Hardening Techniques 3477.3.1 Radiation-Hardening Process Issues 3477.3.1.1 SubstrateEffects 3477.3.1.2 Gate Oxide (Dielectric) Effects 3477.3.1.3 Gate ElectrodeEffects 3487.3.1.4 Postgate-Electrode DepositionProcessing... 3497.3.1.5 Field Oxide Hardening 3497.3.1.6 Bulk CMOSLatchupConsiderations 3507.3.1.7 CMOSSOSISOI Processes 3517.3.1.8 Bipolar Process RadiationCharacteristics............................. 3527.3.2 Radiation-Hardening Design Issues 3527.3.2.1 Total Dose RadiationHardness...... 3537.3.2.2 Single-Event Upset (SEU) Hardening 3587.3.3 Radiation-Hardened Memory Characteristics (Example) 3637.4 Radiation Hardness Assurance and Testing 3677.4.1 Radiation Hardness Assurance 3677.4.2 Radiation Testing 3697.4.2.1 Total DoseTesting 3707.4.2.2 Single-Event Phenomenon(SEP)Testing 372Contents ix7.4.2.3 Dose RateTransientEffects 3767.4.2.4 Neutron.lrradiation 3777.4.3 Radiation Dosimetry 3777.4.4 Wafer Level RadiationTestingand Test Structures 3787.4.4.1 Wafer Level RadiationTesting 3787.4.4.2 RadiationTest Structures.............................. 379Chapter 8Chapter 9Advanced Memory Technologies . . . . . . . . . . . . . . . . . . . .. 3878.1 Introduction 3878.2 Ferroelectric Random Access Memories (FRAMs) 3898.2.1 Basic Theory 3898.2.2 FRAM Cell and Memory Operation 3908.2.3 FRAMTechnology Developments 3938.2.4 FRAM Reliability Issues " 3938.2.5 FRAM Radiation Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3958.2.6 FRAMs Versus EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3978.3 Gallium Arsenide (GaAs) FRAMs . . . . . . . . . . . . . . . . . . . . . .. 3978.4 Analog Memories 3988.5 Magnetoresistive Random Access Memories (MRAMs) 4018.6 Experimental Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . 4078.6.1 Quantum-Mechanical Switch Memories 4078.6.2 A GaAs n-p-n-p Thyristor/JFET Memory Cell. . . . . . . . . . . . .. 4088.6.3 Single-Electron Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4098.6.4 Neuron-MOS Multiple-Valued(MV) Memory Technology ..... 409High-Density Memory Packaging Technologies . . . . . . . .. 4129.1 Introduction........................................ 4129.2 Memory Hybrids and MCMs (2-D) 4179.2.1 Memory Modules (Commercial) 4179.2.2 Memory MCMs (Honeywell ASCM) 4219.2.3 VLSI Chip-an-Silicon (VCOS) Technology 4219.3 Memory Stacks and MCMs (3-D) 4249.3.1 3-D Memory Stacks (Irvine Sensors Corporation) 4279.3.1.1 4 Mb SRAMShort Stack" (Example) 4299.3.2 3-D Memory Cube Technology (Thomson CSF) 4309.3.3 3-D Memory MCMs (GE-HOIITI) 4319.3.3.1 3-D HOI Solid-State Recorder (Example) 4329.3.4 3-D Memory Stacks (n CHIPS) 4329.4 Memory MCMTesting and Reliability Issues 4359.4.1 VCOS OFT Methodology and Screening Flow (Example) 4379.5 Memory Cards 4409.5.1 CMO SRAM Card (Example) 4429.5.2 Flash Memory Cards 4429.6 High-Density Memory Packaging Future Directions . . . . . . . . . 446Index 451PrefaceSemiconductor memories are usually consid-ered to be the most vital microelectronicscomponent of the digital level designs for main-frame computers and PCs, telecommunications,automotive and consumer electronics, and com-mercial and military avionics systems. Semi-conductor memory devices are characterized asvolatile random access memories (RAMs), ornonvolatile memory devices. RAMS can eitherbe static mode (SRAMs) where the logic infor-mation is stored by setting up the logic state of abistable flip-flop, or through the charging of acapacitor as in dynamic random access memo-ries (DRAMs). The nonvolatile memory datastorage mode may be permanent or reprogram-mable, depending upon the fabrication technol-ogy used.In the last decade or so, semiconductormemories have advanced both in density andperformance because of phenomenal develop-ments in submicron technologies. DRAMs areconsidered key technology drivers and predic-tors of semiconductor manufacturing processscaling and performance trends. According tothe Semiconductor Industries Association's re-cent technology road map, the DRAMs are ex-pected to increase in density from64Mb in 1995to 64Gb in 2010. The growing demands for PCsand workstationsusing high-performancemicro-processors are the key targets of DRAM design-ers and manufacturers. The technical advancesin multimegabit DRAMs have resulted in agreater demand for application-specificproductssuch as the pseudostatic DRAM (PSRAM),video DRAM (VDRAM), and high speedDRAM (HSDRAM), e.g., synchronous, cached,and Rambus (configurations using innovativear-chitectures). Each of these specialty memory de-vices has its associated testing and reliabilityissues that have to be taken into considerationfor board and system level designs.Nonvolatile memories such as read-onlymemories (ROMs), programmable read-onlymemories (PROMs), and erasable and program-mable read-only memories (EPROMs) in bothultraviolet erasable (UVPROM) and electricallyerasable (EEPROM) versions have also madesignificant improvements in both density andperformance. Flash memories are being fabri-cated in 8 and 16 Mb density devices for use inhigh-density nonvolatile storage applicationssuch as memory modules and memory cards.The continuously evolving complexity ofmemory devices makes memory fault modeling,test algorithms, design for testability (DFT),built-in self-test (BIST), and fault toleranceareas of signific.ant concern. The general relia-bility issues pertaining to semiconductor de-vices in bipolar and MOS technologies areapplicable to memories also. In addition, thereare some special RAM failure modes and mech-anisms, nonvolatile memory reliability issues,xixiiand reliability modeling and failure predictiontechniques that are reviewed in this book.Radiation effects on semiconductor mem-ories is an area of growing concern. In general,the space radiation environment poses a certainradiation risk to electronic components on earthorbiting satellites and planetary mission space-crafts, and the cumulative effect of damage fromcharged particles such as electrons and protonson semiconductor memories can be significant.The memory scaling for higher densities hasmade them more susceptible to logic upsets andfailures. This book provides a detailed coverageof those radiation effects, including single-eventphenomenon (SEP) modeling and error rate pre-diction, process and circuit design radiationhardening techniques, radiation testing proce-dures, and radiation test structures.Several advanced memory technologiesthat are in the development stages are reviewed,such as ferroelectric random access memories(FRAMs), GaAs FRAMs, analog memories,magnetoresistive random access memories(MRAMs), and quantum-mechanical switchmemories. Another area of current interest cov-ered in the book is the section on high-densitymemory packaging technologies, which in-cludes memory hybrids and multichip module(MCM) technologies, memory stacks and 3-DMCMs, memory MCM testing and reliability is-sues, and memory cards. In high-density mem-ory development, the future direction is toproduce mass memory configurations of veryhigh bit densities ranging from tens ofmegabytes to several hundred gigabytes.There are very few books on the marketthat deal exclusively with semiconductor mem-ories, and the information available in them isfragmented-some of it is outdated. This bookis an attempt to provide a comprehensive and in-tegrated coverage in three key areas of semicon-ductor memories: technology, testing andreliability. It includes detailed chapters on thePrefacefollowing: Introduction; Random Access Mem-ory technology, both SRAMs, DRAMs, and theirapplication-specific architectures; NonvolatileMemories such as ROMs, PROMs, UVPROMs,EEPROMs, and flash memories; Memory FaultModeling and Testing; Memory Design forTestability and Fault Tolerance; SemiconductorMemory Reliability; Semiconductor MemoryRadiation Effects; Advanced Memory Tech-nologies; and High-Density Memory PackagingTechnologies.This book should be of interest and beuseful to a broad spectrum of people in thesemiconductor manufacturing and electronicsindustries, including engineers, system level de-signers, and managers in the computer, telecom-munications, automotive, commercial satellite,and military avionics areas. It can be used bothas an introductory treatise as well as an ad-vanced reference book.I am thankful to all of the technical review-ers who diligently reviewed the manuscript andprovided valuable comments and suggestionsthat I tried to incorporate into the final version. Iwould like to thank several people at GoddardSpace Flight Center, especially George Kramer,Ann Garrison, Ronald Chinnapongse, DavidCleveland, Wentworth Denoon, and CharlesVanek. Special thanks and acknowledgments arealso due to various semiconductor memory man-ufacturers and suppliers for providing product in-formation specification sheets and permission toreprint their material. And the author and IEEEPress acknowledge the efforts of Rochit Raj-suman as a technical reviewer and consultant.Finally, the acknowledgments would beincomplete without thanks to Dudley R. Kay,Director of Book Publishing, John Griffin, andOrlando Velez, along with the other staff mem-bers at IEEE Press, including the EditorialBoard for their invaluable support.Ashok K. SharmaSilver Spring, MarylandSemiconductor MemoriesIntroductionSemiconductor memories are usually consid-ered to be the most vital microelectronic com-ponent of digital logic system design, such ascomputers and microprocessor-based applica-tions ranging from satellites to consumer elec-tronics. Therefore, advances in the fabricationof semiconductor memories including processenhancements and technology developmentsthrough the scaling for higher densities andfaster speeds help establish performance stan-dards for other digital logic families. Semicon-ductor memory devices are characterized asvolatile random access memories ornonvolatile memory devices. In RAMs, thelogic information is stored either by setting upthe logic state of a bistable flip-flop such as in astatic random access memory (SRAM), orthrough the charging of a capacitor as in a dy-namic random access memory (DRAM). In ei-ther case, the data are stored and can be read outas long as the power is applied, and are lostwhen the power is turned off; hence, they arecalled volatile memories,Nonvolatile memories are capable of stor-ing the data, even with the power turned off. Thenonvolatile memory data storage mode may bepermanent or reprogrammable, depending uponthe fabrication technology used. Nonvolatilememories are used for program and microcodestorage in a wide variety of applications in thecomputer, avionics, telecommunications, and1consumer electronics industries. A combinationof single-chip volatile as well as nonvolatilememory storage modes is also available in de-vices such as nonvolatile SRAM (nvRAM) foruse in systems that require fast, reprogrammablenonvolatile memory. In addition, dozens of spe-cial memory architectures have evolved whichcontain some additional logic circuitry to opti-mize their performance for application-specifictasks.This book on semiconductor memoriescovers random access memory technologies(SRAMs and DRAMs) and their application-specific architectures; nonvolatilememorytech-nologies such as read-only memories (ROMs),programmable read-only memories (PROMs),and erasable and programmable read-onlymemories (EPROrvls) in both ultraviolet eras-able (UVPROM) and electrically erasable(EEPROM) versions; memory fault modelingand testing; memory design for testability andfault tolerance; semiconductor memory reliabil-ity; semiconductor memory radiation effects;advanced memory technologies; and high-density memory packaging technologies.Chapter 2 on "Random Access MemoryTechnologies," reviews the static and dynamicRAM technologies as well as their application-specific architectures. In the last two decades ofsemiconductor memory growth, the DRAMshave been the largest volume volatile memory12produced for use as main computer memoriesbecause of their high density and low cost perbit advantage. SRAM densities have generallylagged a generation behind the DRAMs, i.e., theSRAMs have about one-fourth the capacity ofDRAMs, and therefore tend to cost about fourtimes per bit as the DRAMs. However, theSRAMs offer low-power consumption andhigh-performance features which make thempractical alternatives to the DRAMs. Nowa-days, a vast majority of SRAMs are being fabri-cated in the NMOS and CMOS technologies,and a combination of two technologies (also re-ferred to as the mixed-MOS) for commoditySRAMs.Bipolar memories using emitter-coupledlogic (ECL) provide very fast access times, butconsume two-three times more power thanMOS RAMs. Therefore, in high-density andhigh-speed applications, various combinationsof bipolar and MOS technologies are beingused. In addition to the MaS and bipolar mem-ories referred to as the "bulk silicon" tech-nologies, silicon-on-insulator (SOl) isolationtechnology such as silicon-on-sapphire (SOS)SRAMs have been developed for improved ra-diation hardness. The SRAM density and per-formance are usually enhanced by scaling downthe device geometries. Advanced SRAM de-signs and architectures for 4 and 16 Mb densitychips with submicron feature sizes (e.g., 0.2-0.6urn) are reviewed. Application-specific mem-ory designs include first-in first-out (FIFO),which is an example of shift register memory ar-chitecture through which the data are trans-ferred in and out serially. The dual-port RAMsallow two independent devices to have simulta-neous read and write access to the same mem-ory. Special nonvolatile, byte-wide RAMconfigurations require not only very low oper-ating power, but have battery back-up data-retention capabilities. The content-addressablememories (CAMs) are designed and used bothas the embedded modules on larger VLSI chipsand as stand-alone memory for specific systemapplications.The DRAMs store binary data in cells oncapacitors in the form of charge which has to beChap. 1 Introductionperiodically refreshed in order to prevent it fromleaking away. A significant improvement inDRAM evolution has been the switch fromthree-transistor (3-T) designs to one-transistor(1-T) cell design that has enabled production of4 and 16 Mb density chips that use advanced,3-D trench capacitor and stacked capacitor cellstructures. DRAMs of 64 Mb density have beensampled, and prototypes for 256 Mb are in de-velopment. The DRAMs are susceptible to softerrors (or cell logic upset) occurring from alphaparticles produced by trace radioactive packag-ing material. In NMOS/CMOS DRAM designs,various techniques are used to reduce their sus-ceptibility to the soft-error phenomenon. TheBiCMOS DRAMs have certain advantages overthe pure CMOS designs, particularly in accesstime. The technical advances in multimegabitDRAMs have resulted in greater demand forapplication-specific products such as the pseu-dostatic DRAM (PSRAM) which uses dynamicstorage cells but contains all refresh logic on-chip that enables it to function similarly to aSRAM. Video DRAMs (VDRAMs) have beenproduced for use as the multiport graphicbuffers. A high-speed DRAM (HSDRAM) hasbeen developed with random access time ap-proaching that of SRAMs while retaining thedensity advantage of 1-T DRAM design. Someother examples of high-speed DRAM innova-tive architectures are synchronous, cached, andRambus" DRAMs.Chapter 3 reviews various nonvolatilememory (NVM) technologies. A category ofNVM is read-only memories (ROMs) in whichthe data are writtenpermanentlyduring manufac-turing, or the user-programmable PROMs inwhich the data can be written only once. ThePROMs are available in both bipolar and CMOStechnologies. In 1970, a floating polysilicon-gate-based erasable programmable read-onlymemory was developed in which hot electronsare injectedinto the floatinggate and removedei-ther by ultraviolet internal photoemission orFowler-Nordheimtunneling. The EPROMs (alsoknown as UVEPROMs) are erased by removingthem from the target system and exposing themto ultraviolet light. Since an EPROM consists ofChap. I Introductionsingle-transistorcells, they can be made in den-sities comparable to the DRAMs. Floating-gateavalanche-injection MOS transistors (FAMOS)theory and charge-transfer mechanisms are dis-cussed. Several technology advances in cellstructures, scaling, and process enhancementshave made possible the fabrication of 4-16 Mbdensity EPROMs. A cost-effective alternativehas been the one-time programmable (OTP)EPROMintroducedby the manufacturers for thehigh-volumeapplicationsROMmarket.An alternative to EPROM(or UVEPROM)has been the development of electrically erasablePROMs (EEPROMs) which offer in-circuit pro-gramming flexibility. The several variations ofthis technology include metal-nitride-oxide-semiconductor (MNOS), silicon-oxide-nitride-oxide-semiconductor (SONDS), floating-gatetunneling oxide (FLOTOX), and textured poly-silicon. Since the FLOTOX is the most com-monly used EEPROM technology, the Fowler-Nordheim tunnelingtheory for a FLOTOXtran-sistor operation is reviewed. The conventional,full functional EEPROMs have several advan-tages, including the byte-erase, byte-program,andrandom accessreadcapabilities. The conven-tional EEPROMs used NOR-gate cells, but themodified versions include the NAND-structuredcells that have been used to build 5 V-only4 Mb EEPROMs. An interesting NVM architec-ture is the nonvolatile SRAM, a combination ofEEPROMand SRAMin whicheach SRAMcellhas a corresponding "shadow" EEPROM cell.The EPROMs, including UVEPROMs andEEPROMs, are inherently radiation-susceptible.The SONOS technology EEPROMs have beendeveloped for military and space applicationsthat require radiation-hardened devices. Flashmemories based on EPROMor EEPROMtech-nologies are devices for whichthe contentsof allmemoryarraycells can be erased simultaneouslythrough the use of an electrical erase signal. Theflash memories, because of their bulk erasecharacteristics, are unlike the floating-gateEEPROMs whichhaveselect transistors incorpo-rated in each cell to allowfor the individual byteerasure. Therefore, the flash memories can bemade roughly two or three times smaller than3the floating-gate EEPROM cells. The improve-ments in flash EEPROMcell structures have re-sulted in the fabrication of 8 and 16 Mb densitydevices for use in high-density nonvolatile stor-age applications such as memory modules andmemory cards.Chapter 4 on "Memory Fault Modelingand Testing," reviews memory failure modesand mechanisms, fault modeling, and electricaltesting. The memory device failures are usuallyrepresentedby a bathtub curve and are typicallygrouped into three categories, depending uponthe product's operatinglife cycle stage where thefailures occur. Memory fault models have beendeveloped for the stuck-at faults (SAFs), transi-tion faults (TFs), address faults (AFs), bridgingfaults (BFs), coupling faults (CFs), pattern-sensitive faults (PSFs), and the dynamic (ordelay) faults. A most commonly used model isthe single-stuck-at fault (SSF) which is also re-ferred to as the classical or standardfault model.However, the major shortcomingof the stuck-atfault model is that the simulation using thismodel is no longer an accurate quality indicatorfor the ICs like memory chips. A large percent-age of physical faults occurringin the ICs can beconsidered as the bridging faults (BFs) consist-ing of shorts between two or more cells or lines.Another important category of faults that cancause the semiconductor RAM cell to functionerroneouslyis the couplingor PSFs. March testsin various forms have been found to be quite ef-fective for detecting the SAFs, TFs, and CFs.Many algorithms have been proposed for theneighborhood pattern-sensitive faults (NPSFs)based on an assumption that the memory array'sphysical and logical neighborhoods are identical.This may not be a valid assumption in state-of-the-art memory chips which are being designedwith the spare rows and columns to increaseyield and memory array reconfiguration, ifneeded. The embedded RAMs which are beingused frequently are somewhat harder to test be-cause of their limited observability and control-lability. A defect-oriented (inductive fault)analysis has been shown to be quite useful infinding various defect mechanisms for a givenlayout and technology.4In general, the memory electrical testingconsists of the de and ac parametric tests andfunctional tests. For RAMs, various functionaltest algorithms have been developed for whichthe test time is a function of the number ofmemory bits (n) and range in complexity fromO(n) to 0(n2) . The selection of a particular set oftest patterns for a given RAM is influenced bythe type of failure modes to be detected, mem-ory bit density which influences the test time,and the memory ATE availability. These are thedeterministic techniques which require well-defined algorithms and memory test input pat-terns with corresponding measurements ofexpected outputs. An alternate test approachoften used for the memories is random (orpseudorandom) testing which consists of apply-ing a string of random patterns simultaneouslyto a device under test and to a reference mem-ory, and comparing the outputs. Advancedmegabit memory architectures are being de-signed with special features to reduce test timeby the use of the multibit test (MBT), line modetest (LMT), and built-in self-test (BIST). Thefunctional models for nonvolatile memories arebasically derived from the RAM chip functionalmodel, and major failure modes in the EPROMssuch as the SAFs, AFs, and BFs can be detectedthrough functional test algorithms. Recent stud-ies have shown that monitoring of the elevatedquiescent supply currents (IDDQ) appears to bea good technique for detecting the bridging fail-ures. The IDDQ fault models are being devel-oped with a goal to achieve 100% physicaldefect coverage. Application-specific memoriessuch as the FIFOs, video RAMs, synchronousstatic and dynamic RAMs, and double-bufferedmemories (DBMs) have complex timing re-quirements and multiple setup modes which re-quire a suitable mix of sophisticated testhardware, the DFf and BIST approach.Chapter 5 reviews the memory design fortestability (DFT) techniques, RAM and ROMBIST architectures, memory error-detection andcorrection (EDAC) techniques, and the memoryfault-tolerance designs. In general, the memorytestability is a function of variables such as cir-cuit complexity and design methodology. TheChap. 1 Introductiongeneral guidelines for a logic design based onpractical experience are called the ad hoc designtechniques such as logic partitioning, and addi-tion of some I/O test points for the embeddedRAMs to increase controllability and observ-ability. Structured design techniques are basedupon a concept of providing uniform design forthe latches to enhance logic controllability, andcommonly used methodologies include thelevel-sensitive scan design (LSSD), scan path,scan/set logic, random access scan, and theboundary scan testing (BST). The RAM BISTtechniques can be classified into two categoriesas the "on-line BIST" and "off-line BIST." TheBIST is usually performed by applying certaintest patterns, measuring the output responseusing linear feedback shift registers (LFSRs),and compressing it. The various methodologiesfor the BIST include exhaustive testing, pseudo-random testing, and the pseudoexhaustive test-ing. For the RAMs, two BIST approaches havebeen proposed that utilize either the randomlogic or a microcoded ROM. The major advan-tages associated with a microcoded ROM overthe use of random logic are a shorter designcycle, the ability to implement alternative testalgorithms with minimal changes, and ease intestability of the microcode. The RAM BISTimplementation strategies include the use of thealgorithmic test sequence (ATS), the 13N Marchalgorithm with a data-retention test, a fault-syndrome-based strategy for detecting the PSFs,and the built-in logic block observation(BILBO) technique. For the embedded memo-ries, various DFf and BIST techniques havebeen developed such as the scan-path-basedflag-scan register (FLSR) and the random-pattern-based circular self-test path (CSTP).Advanced BIST architectures have beenimplemented to allow parallel testing with on-chip test circuits that utilize multibit test (MBT)and line mode test (LMT). An example is thecolumn address-maskable parallel test (CMT)architecture which is suitable for the ultrahigh-density DRAMs. The current generation mega-bit memory chips include spare rows andcolumns (redundancies) in the memory array tocompensate for the faulty cells. In addition, toChap. 1 Introductionimprove the memory chip yield, techniquessuch as the built-in self-diagnosis (BISD) andbuilt-in self-repair (BISR) have been investi-gated. BIST schemes for ROMs have been de-veloped that are based on exhaustive testing andtest response compaction. The conventional ex-haustive test schemes for the ROMs use com-paction techniques which are parity-based,count-based, or polynomial-division-based (sig-nature analysis).The err-ors in semiconductor memoriescan be broadly categorized into hard failurescaused by permanent physical damage to the de-vices, and soft errors caused by alpha particlesor the ionizing dose radiation environments.The most commonly used error-correctingcodes (ECC) which are used to correct hardand soft errors are the single-error-correctionand double-error-detection (SEC-DED) codes,also referred to as the Hamming codes. How-ever, these codes are inadequate for correctingdouble-bitlword-line soft errors. Advanced 16Mb DRAM chips have been developed that useredundant word and bit lines in conjunctionwith the ECC to produce an optimized fault tol-erance effect. In a new self-checking RAM ar-chitecture, on-line testing is performed duringnormal operations without destroying the storeddata. A fault tolerance synergism for memorychips can be obtained by a combined use of re-dundancy and ECC. A RAM fault tolerance ap-proach with dynamic redundancy can use eitherthe standby reconfiguration method, or memoryreconfiguration by the graceful degradationscheme. To recover from soft errors (transienteffects), memory scrubbing techniques are oftenused which are based upon the probabilistic ordeterministic models. These techniques can beused to calculate the reliability rate R(t) andMTTF of the memory systems.Chapter 6 reviews general reliability is-sues for semiconductor devices such as thememories, RAM failure modes and mecha-nisms, nonvolatile memories reliability, reliabil-ity modeling and failure rate prediction, designfor reliability, and reliability test structures. Thereliability of a semiconductor device such as amemory is the possibility that the device will5perform satisfactorily for a given time at a de-sired confidence level under specified operatingand environmental conditions. The memory de-vice failures are a function of the circuit designtechniques, materials, and processes used infabrication, beginning from the wafer levelprobing to assembly, packaging, and testing.The general reliability issues pertaining to semi-conductor devices in bipolar and MOS tech-nologies are applicable to the memories also,such as the dielectric-related failures fromgate-oxide breakdown, time-dependent dielec-tric breakdown (TDDB), and ESD failures; thedielectric-interface failures such as those causedby ionic contamination and hot carrier effects:the conductor and metallization failures, e.g.,electromigration and corrosion effects; the as-sembly and packaging-related failures. How-ever, there are special reliability issues andfailure modes which are of special concern forthe RAMs. These issues include gate oxide reli-ability defects, hot-carrier degradation, theDRAM capacitor charge-storage and data-reten-tion properties, and DRAM soft-error failures.The memory gate dielectric integrity and relia-bility are affected by all processes involved inthe gate oxide growth.The high-density DRAMs use 3-D storagecell structures such as trench capacitors, stackedcapacitor cells (STCs), and buried storage elec-trodes (BSEs). The reliability of these cell struc-tures depends upon the quality and growth ofsilicon dioxide, thin oxide/nitride (ON), andoxide/nitride/oxide (DNa) composite films.The reduced MaS transistor geometries fromscaling of the memory devices has made themmore susceptible to hot carrier degradation ef-fects. In DRAMs, the alpha-particle-inducedsoft-error rate (SER) can be improved by usingspecial design techniques. Nonvolatile memo-ries, just like volatile memories, are also suscep-tible to some specific failure mechanisms. ForPROMs with fusible links, the physical integrityand reliability of fusible links are a major con-cern. In floating-gate technologies such asEPROMs and EEPROMs, data retention charac-teristics and the number of write/erase cycleswithout degradation (endurance) are the most6critical reliability concerns. The ferroelectricmemory reliability concerns include the agingeffects of temperature, electric field, and thenumber of polarization reversal cycles on ferro-electric films used (e.g., PZT).Reliability failure modelingis a key to thefailure rate predictions, and there are many sta-tistical distributions such as the Poisson, Normal(or Gaussian), Exponential, Weibull, and Log-normal that are used to model various reliabilityparameters. There are several reliability predic-tion procedures for predictingelectroniccompo-nent reliability such as MIL-HDBK-217 andBellcore Handbook. However, the failure ratecalculation results for semiconductor memoriesmay vary widely fromone model to another. De-sign for reliability (DFR), which includes failuremechanisms modeling and simulation, is an im-portant concept that should be integrated withthe overall routine process of design for perfor-mance. The method of accelerated stress agingfor semiconductor devices such as memories iscommonly used to ensure long-term reliability.For nonvolatile memories, endurance modelingis necessary in the DFR methodology. An ap-proach commonly employed by the memorymanufacturers in conjunction with the end-of-line product testinghas been the use of reliabilitytest structures and process (or yield) monitors in-corporatedat the wafer level in kerf test sites and"drop-in" test sites on the chip. The purpose ofreliabilitytesting is to quantify the expectedfail-ure rate of a device at various points in its lifecycle. The memory failure modes which can beaccelerated by a combined elevated temperatureand high-voltage stress are the threshold voltageshifts, TDDB leading to oxide shorts, and data-retention degradation for the nonvolatile memo-ries. MIL-STD-883, Method 5004 ScreeningProcedure (or equivalent) are commonlyusedbythe memory manufacturers to detect and elimi-nate the infant mortality failures. MIL-STD-883,Method5005 Qualification and QCI Procedures(or equivalent) are used for high-reliability mili-tary and space environments.Chapter 7, entitled "Semiconductor Mem-ory Radiation Effects," reviews the radiation-hardeningtechniques,radiation-hardening designChap. 1 Introductionissues, radiation testing, radiation dosimetry,wafer level radiation testing, and test structures.The space radiation environment poses a certainradiation risk to all electronic components onearth orbiting satellites and the planetary mis-sion spacecrafts. Although the natural space en-vironment does not contain the high dose ratepulse characteristics of a weapon environment(often referred to as the "gamma dot"), the cu-mulative effect of ionization damage fromcharged particles such as electrons and protonson semiconductor memories can be significant.In general, the bipolar technology memories(e.g., RAMs, PROMs) are more tolerant to totaldose radiation effects than the nonhardened,bulk MOS memories. For the MOS devices, theionization traps positive charge in the gate oxidecalled the oxide traps, and produces interfacestates at the Si-Si02 interface. The magnitudeof these changes depends upon a number of fac-tors such as total radiation dose and its energy;dose rate; applied bias and temperature duringirradiation; and postirradiation annealing condi-tions. Ionization radiation damage causeschanges in the memory circuit parameters suchas standby power supply currents, I/O voltagethreshold levels and leakage currents, criticalpath delays, and timing specification degrada-tions.The single-event phenomenon (SEP) inthe memories is caused by high-energy particlessuch as those present in the cosmic rays passingthrough the device to cause single-event upsets(SEUs) or soft errors, and single-event latchup(SEL) which may result in hard errors. The im-pact of SEU on the memories, because of theirshrinking dimensions and increasing densities,has become a significant reliability concern.The number of SEUs experienced by a mem-ory device in a given radiation environmentdepends primarily on its threshold for upsets,usually expressed by its critical charge Qc orthe critical LET and the total device volumesensitive to ionic interaction, i.e., creation ofelectron-hole (e-h) pairs. The Qc is primarilycorrelated to circuit design characteristics. Criti-cal LET for a memory is found experimentallyby bombarding the device with various ionChap. 1 Introductionspecies (e.g., in a cyclotron). For the memorydevices flown in space, radiation tolerance is as-sessed with respect to the projected total doseaccumulated, which is the sum of absorbed dosecontributions from all ionizing particles, and iscalculated (in the form of dose-depth curves) bysophisticated environmental modeling basedupon the orbital parameters, mission duration,and thickness of spacecraft shielding. It is im-portant to verify ground test results obtained byobservation of actual device behavior in orbit.Several in-orbit satellite experiments have beendesigned to study the effect of the radiation par-ticle environment on semiconductor devicessuch as memories.The nonvolatile MOS memories are alsosubject to radiation degradation effects. The ra-diation hardness of memories is influenced by anumber of factors, both process- and design-re-lated. The process-related factors which affectradiation response are the substrate effects, gateoxidation and gate electrode effects, post-polysilicon processing, and field oxide harden-ing. The CMOS SOIlSOS technologies whichutilize insulator isolation as opposed to the junc-tion isolation for bulk technologies offer a sub-stantial advantage in the latchup, transientupset, and SED characteristics. The memory cir-cuits can be designed for total dose radiationhardness by using optimized processes (e.g.,hardened gate oxides and field oxides) and gooddesign practices. The bulk CMOS memorieshave been hardened to SEU by using an appro-priate combination of processes (e.g., thin gateoxides, twin-tub process with thin epitaxial lay-ers) and design techniques such as utilizingpolysilicon decoupling resistors in the cross-coupling segment of each cell.Radiation sensitivity of unhardened mem-ory devices can vary from lot to lot, and forspace applications, radiation testing is requiredto characterize the lot radiation tolerance. Theground-based radiation testing is based upon asimulation of space environment by using radia-tion sources such as the Cobalt-60, X-ray tubes,particle accelerators, etc. For example, totaldose radiation testing on the memories is per-formed per MIL-STD-883, Method 1019, which7defines the test apparatus, procedures, and otherrequirements for effects from the Co-60 gammaray source. Radiation testing requires calibra-tion of the radiation source and proper dosime-try. Sometimes, radiation test structures are usedat the wafer (or chip level) as process monitorsfor radiation hardness assurance.Chapter 8 reviews several advanced mem-ory technologies such as the ferroelectric ran-dom access memories (FRAMs), GaAs FRAMs,analog memories, magnetoresistive randomaccess memories (MRAMs), and quantum-mechanical switch memories. In the last fewyears, an area of interest in advanced non-volatile memories has been the development ofthin-film ferroelectric (FE) technology that usesmagnetic polarization (or hysteresis) propertiesto build the FRAMs. The high-dielectric-constant materials such as lead zirconate titan-ate (PZT) thin film can be used as a capacitive,nonvolatile storage element similar to trench ca-pacitors in the DRAMs. This FE film technol-ogy can be easily integrated with standardsemiconductor processing techniques to fabri-cate the FRAMs which offer considerable sizeand density advantage. A FRAM uses one tran-sistor and one capacitor cell. Although theFRAMs have demonstrated very high write en-durance cycle times, the FE capacitors depolar-ize over time from read/write cycling. Therefore,thermal stability, fatigue from polarization rever-sal cycling, and aging of the FRAMs are key re-liability concerns. In general, the FE capacitorsand memories made from thin-film PZT haveshown high-radiation-tolerance characteristicssuitable for space and military applications. TheFE element processing has also been combinedwith GaAs technology to produce ferroelectricnonvolatile (or FERRAMs) prototypes of 2KJ4Kbit density levels.The memory storage volatile (or non-volatile) usually refers to the storage of digitalbits of information ("O"s and "T's), However,recently, analog nonvolatile data storage hasalso been investigated using the EEPROMs andFRAMs in applications such as audio recordingof speech and analog synaptic weight storagefor neural networks. This nonvolatile analog8storage is accomplished by using the EEPROMswhich are inherently analog memories on a cell-by-cell basis because each floating gate canstore a variable voltage. The sensed value of acell's conductivity corresponds to the value ofthe analog level stored. This technology hasbeen used in audio applications such as single-chip voice messaging systems. Another technol-ogy development for nonvolatile storage is themagnetoresistive memory (MRAM) which usesa magnetic thin-film sandwich configured intwo-dimensional arrays. These MRAMs arebased upon the principle that a material's mag-netoresistance will change due to the presenceof a magnetic field. The magnetoresistive tech-nology has characteristics such as a nondestruc-tive readout (NDRO), very high radiationtolerance, higher write/erase endurance com-pared to the FRAMs, and virtually unlimitedpower-off storage capability. Another variationon this technology is the design and conceptualdevelopment of micromagnet-Hall effect ran-dom access memory (MHRAM) where infor-mation is stored in small magnetic elements.The latest research in advanced memory tech-nologies and designs includes the solid-state de-vices that use quantum-mechanical effects suchas resonant-tunneling diodes (RTDs) and reso-nant-tunneling hot-electron transistors (RHETs)for possible development of gigabit memorydensities. These devices are based upon the neg-ative resistance (or negative differential conduc-tance) property which causes a decrease incurrent for an increase in voltage. This effecthas been used in the development of a SRAMcell that uses two RTDs and one ordinary tunneldiode (TO) for the complete cell.Chapter 9, "High-Density Memory Pack-aging Technologies," reviews commonly usedmemory packages, memory hybrids and 2-Dmultichip modules (MCMs), memory stacksand 3-D MCMs, memory MCM testing and reli-ability issues, memory cards, and high-densitymemory packaging future directions. The mostcommon high-volume usage semiconductorRAMs and nonvolatile memories use "through-the-hole" (or insertion mount) and the surfacemount technology (SMT) packages. For high-Chap. I Introductionreliability military and space applications, her-metically sealed ceramic packages are usuallypreferred. For high-density memory layouts onthe PC boards, various types of packaging con-figurations are used to reduce the board levelmemory package "footprint." However, increas-ing requirements for denser memories have ledto further compaction of packaging technolo-gies through the conventional hybrid manufac-turing techniques and MCMs. For the assemblyof MCMs, various interconnection technologieshave been developed such as the wire bonding,tape automated bonding (TAB), flip-chip bond-ing, and high-density interconnect (HDI).A commonly used multichip module con-figuration for the DRAMs is the single-in-linememory module (SIMM). Several variations on3-D MCM technology have evolved for thememories, with a goal of improving storage den-sities while lowering the cost per bit. The densityof chip packaging expressed as the "silicon effi-ciency" is determined by the ratio of silicon diearea to the printed circuit board (or substrate)area. An example is the memory MCMs fabri-cated by Honeywell, Inc. for the AdvancedSpacebome Computer Module (ASCM) in thefollowing two technologies: MCM-D using thin-film multilayer copper/polyimide interconnectson an alumina ceramic substrate mounted in aperimeter-leaded cofired ceramic flatpack, andMCM-C which used a multilayer cofired alu-mina package. In the chip-on-board (COB)packaging, the bare memory chip (or die) is di-rectly attached to a substrate, or even PC board(such as FR4 glass epoxy). IBM (now LORALFederal Systems) has developed VLSI chip-on-silicon (VCaS) MCMs which combine HDItechnology with a flip-chip, C4 (controlled-collapse chip connect) attach process.An extension of 2-D planar technologyhas been the 3-D concept in which the memorychips are mounted vertically prior to the attach-ment of a suitable interconnect. The" 3-D ap-proach can provide higher packaging densitiesbecause of reduction in the substrate size, mod-ule weight, and volume; lower line capacitanceand drive requirements; and reduced signalpropagation delay times. Four generic types ofChap. 1 Introduction3-D packaging technologies are currently beingused by several manufacturers: layered die, diestacked on edge, die stacked in layers, and verti-cally stacked modules. An example is Texas In-struments (TI) 3-D HOI MCM packagingtechnology that has been used for the develop-ment of a solid-state recorder (SSR) for DARPAwith initial storage capacity of 1.3 Gb expand-able to 10.4 Gb.However, MCM defects and failures canoccur due to the materials, including the sub-strate, dice, chip interconnections, and manu-facturing process variations; lack of properstatistical process control (SPC) during fabrica-tion and assembly; inadequate screening andqualification procedures; and a lack of proper de-sign for testability(OFT) techniques.Availabilityof "known-good-die" (KGD) and "known-good-substrate" (KGS) are important prerequisites forhigh-yield MCMs and minimizing the need forexpensive module rework/repair. The MCMDFf9techniques such as the boundary scan and level-sensitive scan design (LSSD) are often used inconjunction with the design for the reliabilityap-proach. Another application for high-densitymemory bare chip assembly has been the devel-opment of memory cards that are lightweightplastic and metal cards containing the memorychips and associated circuitry. They offer signifi-cant advantages in size, weight, speed, and powerconsumption. These cards integrate multiplevolatile/nonvolatile memory technologies, andare intended to serve as alternatives for tradi-tional hard disks and floppy drives in notebookcomputers and mobile communication equip-ment.In high-density memory development, thefuture direction is to produce mass memoryconfigurations of very high bit densities rangingfrom tens of megabytes to several hundred giga-bytes by integrating 3-D technology into theMCMs.2Random AccessMemory Technologies2.1 INTRODUCTIONSemiconductor memory devices are generallycategorized as volatile or nonvolatile randomaccess memories (RAMs). In RAMs, the infor-mation is stored either by setting the state of abistable flip-flop circuit or through the chargingof a capacitor. In either of these methods, the in-formation stored is destroyed if the power is in-terrupted. Such memories are therefore referredto as volatile memories. If the data are stored(i.e., written into the memory) by setting thestate of a flip-flop, they will be retained as longas the power is applied and no other write sig-nals are received. The RAMs fabricated withsuch cells are known as static RAMs, orSRAMs. When a capacitor is used to store datain a semiconductor RAM, the charge needs tobe periodically refreshed to prevent it frombeing drained through the leakage currents.Hence, the volatile memories based on this ca-pacitor-based storage mechanism are known asthe dynamic RAMs, or DRAMs.SRAM densities have generally laggedbehind those for the DRAMs (1:4), mainly be-cause of the greater number of transistors in astatic RAM cell. For example, a 256 kb SRAMhas about the same number of transistors as a 1Mb DRAM. However, static RAMs are beingwidely used in systems today because of theirlow-power dissipation and fast data access time.10Early static RAMs were developed in three sep-arate technologies: bipolar, NMOS, and CMOS.By the middle of the 1980s, the vast majority ofSRAMs were made in CMOS technology.SRAMs are currently available in many vari-eties, ranging from the conventional MOS(NMOS or CMOS) to high-speed bipolar andGaAs SRAM designs. Full bipolar SRAMs, al-though less than 1% of the total SRAM market,are still available in lower densities for veryhigh-speed applications. The lower end com-modity SRAMs are represented by the "mixed-MOS" technology which is a combination ofCMOS and NMOS for high-density applica-tions, and by the full CMOS technology for acombination of high-density and low-powerrequirements. High-speed and high-densitySRAMs are fabricated in both CMOS andmixed-Mfrfi technologies, as well as combina-tions of bipolars and CMOS, called BiCMOS.SRAM speed has been usually enhancedby scaling of the MOS process since shortergate channel length, L(eft) translates quite lin-early into faster access time. Figure 2-1(a)shows the plot of SRAM wafer average accesstime versus L( eff). This scaling of the processfrom first -generation to second-generationSRAMs has resulted in support of higher den-sity products, as shown in the L(eft) versus den-sity logarithmic plot of Figure 2-1(b). Section2.2 of this chapter discusses in detail variousSec. 2.1 Introduction 11(a)Low-power dissipation and faster access timeshave been obtained, even with an increase inchip size for every successive generation ofDRAMs, as shown in Figure 2-2 [2]. TheDRAM memory array and peripheral circuitrysuchas decoders, selectors, senseamplifiers, andoutput drivers are fabricated usingcombinationsof n-channel and p-channel MOS transistors. Asa result, 1Mb DRAMshave reachedmaturity inproduction, and nowadays, 4 and 16 MbDRAMs are being offered by several manufac-turers. While the density of DRAMs has beenapproximately quadrupling every three years,neither their access time nor cycle time has im-proved as rapidly. To increase the DRAMthroughput, special techniques such as pagemode, static columnmode, or nibble mode havebeen developed. The faster DRAMs are fabri-cated withspeciallyoptimized processes and in-novative circuit design techniques. In some newDRAMsbeingofferedwith wide on-chip buses,1024-4096 memory locations can be accessedin parallel, e.g., cache DRAMs, enhancedDRAMs, synchronous DRAMs, and RambusDRAMs. Section 2.3 of this chapter discussesthe DRAM technology development; CMOSDRAMs; DRAMcell theory and advanced cellstructures; BiCMOS DRAMs; soft-errorfailures1.00.9..'.. ........ .....0.6 0.7 0.8L(eff) (microns)."..... ...0.516K 64K 256K 1M 4M 16M 64MLOGDENSITY(b)0.2 _ ___"_ --'4K12 _ ___'____'___ ___"___.....o--_----'0.416 ,...14.-3.02.52.0en 1.5 c FIRST0U 1.2 GENERATIONI 1.0e- 0.8Q)SECOND::r 0.6 GENERATIONC)0 0.5-J0.40,3w

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en 20 ----------.-------.,.---,500ACCESS: NOMINAL CONDITIONPOWER : Vee + 10%, 25C230ns CYCLE'S100 1000 a:wc:::;- ;:E 50 500 0.s POWER 0-w enN .sen w0- :EI i=U 10 100 (f)enw5 ACCESS TIME 50 UU4K 16K64K256K1M 4M 16M64M256M1GMEMORYCAPACITY (bit)Figure 2-2. Trends in standard DRAMdevelop-ment. (From [2], with permissionofIEEE.)Figure 2-1. (a) SRAMwafer average access timeversus L(eff). (b) L(eff) versus SRAMdensity logarithmic plot. (From [I],with permissionof IEEE.)SRAM (NMOS and CMOS) cell structures;MOS SRAM architectures, cell, and peripheralcircuits operation; bipolar SRAM (EeL andBiCMOS) technologies; silicon-on-insulator(SOl) technologies; advanced SRAM architec-tures and technologies; and some application-specificSRAMs.In the last decade of semiconductor mem-ories growth, dynamic randomaccess memories(DRAMs) have been produced in the largestquantities because of their high density and lowcost per bit advantage. Maincomputermemoriesare mostlyimplemented usingthe DRAMs, eventhough they lag behind the SRAMs in speed.12in DRAMs; advancedDRAMdesigns and archi-tectures; and a fewapplication-specific DRAMs.2.2 STATIC RANDOM ACCESSMEMORIES (SRAMs)SRAMis classifiedas a volatilememorybecauseit depends upon the application of continuouspower to maintainthe storeddata. If the power isinterrupted, the memory contents are destroyedunless a back-up battery storage systemis main-tained. SRAMoutput widthrangesfrom 1to 32 bwide. Standard inputs and outputs include inter-facing with CMOS, TfL, and ECL circuits.Power supply range includes standard 5 V andnew 3.3 V standard for battery-powered applica-tions. A SRAM is a matrix of static, volatilememorycells, and addressdecodingfunctions in-tegrated on-chip to allow access to each cell forread/write functions. The semiconductor memorycells use active element feedback in the form ofcross-coupled inverters to store a bit of informa-tion as a logic "one" or a "zero" state. The activeelements in a memorycell needa constant sourceof de (or static) power to remain latched in thedesired state. The memory cells are arranged inparallel so that all the data can be or .re-trieved simultaneously. An address multiplexingschemeis used to reducethe numberof input andoutput pins. As SRAMs have evolved, they haveundergone a dramatic increase in their density.Most of this has been due to the scalingdown tosmaller geometries. For example, the 4 kb MOSSRAM used 5 J.Lm minimumfeature size, whilethe 16kb, 64 kb, 256 kb, and 1Mb SRAMs werebuilt with 3.0, 2.0, 1.2, and 0.8 IJ.m feature size,respectively. Now, the 4 and 16Mb SRAMs havebeen developed with 0.6-0.4 IJ.m process tech-nology. Also, scaling of the feature size reducesthe chip area, allowinghigher densitySRAMs tobe made more cost effectively.2.2.1 SRAM (NMOS and CMOS)Cell StructuresThe basic SRAM cell made up of cross-coupled inverters has several variations. Theearly NMOS static RAM cells consisted of six-transistor designs with four enhancement modeChap. 2 Random Access Memory Technologiesand two depletion mode pull-up transistors.A significant improvement in cost and powerdissipation was achieved by substituting ion-implanted polysilicon load resistors for the twopull-up transistors. These were called R-IoadNMOS, and a successor to these is called the"mixed-MOS" or "resistor-load CMOS." TheseSRAMs consisted of an NMOS transistor ma-trix with high ohmic resistor loads and CMOSperipheral circuits which allowed the benefit oflower standby power consumption while retain-ing the smaller chip area of NMOS SRAMs.The transition from the R-Ioad NMOS to the R-load CMOS SRAMs occurred at the 4 kb den-sity level. At the same time, the concept ofpower-downmode controlled by the chip enablepin (eE) also appeared. In this low-voltagestandby mode, the standby current for themixed-MOS parts is typically in the microamp(J..LA) range, and for the full CMOS, in thenanoamp (nA) range. This low-power dissipa-tion in the standby mode opened the potentialfor high-density battery back-up applications.The mixed-MOS and the full NMOS de-signs have higher standby currents than theCMOS SRAMs. However, the mixed-MOStechnique provides better scaling advantagesand relatively lower power dissipation. Theearly CMOS RAMs with metal gate technologywere mostly used in the aerospace and otherhigh-reliability applications for their widernoise margins, wider supply voltage tolerance,higher operating temperature range, and lowerpower consumption. MOS SRAMs more popular with the development of silicongate technology in which the two levels of i.nter-connections through polysilicon and aluminumallowed reduction in cell area, enabling the fab-rication of larger and denser memory arrays. Inthe mid-1980s, a vast majority of all SRAMswere being made in several variations, such asthe CMOS or mixed-MOS formation in n-well,p-well, or the twin-tub technologies.Figure 2-3 shows an MOS SRAM cellwith load devices which may either be the en-hancement or depletion mode transistors as inan NMOS cell, PMOS transistors in a CMOScell, or load resistors in a mixed-MOS or an R-load cell. The access and storage transistors areSec. 2.2 Static RandomAccess Memories (SRAMs) 13Figure 2-3. Ageneral schematic of a SRAM mem-ory cell.enhancement mode NMOS. The purpose of loaddevices (L) is to offset the charge leakage at thedrains of the storage and select transistors.When the load transistor is PMOS, the resultingCMOS cell has essentially no current flow(a)through the cell, except during switching, Thedepletion load and resistive load have a lowlevel of current flowing through them, andhence the standby power dissipation is alwayshigher than that of the CMOS cell.Figure 2-4(a) shows the basic CMOSSRAMcell consistingof two transistors and twoload elements in a cross-coupled inverterconfig-uration, withtwo select transistors addedto makeup a six-transistor cell. Figure 2-4(b) showsthe use of polysilicon load resistors instead ofPMOStransistors intheCMOScell, which allowsup to a 300/0 reduction in the cell size in double-polysilicon technology, usingburiedcontacts.There can be several application-specificvariations in the basic SRAM cell. Figure2-4(c) shows an eight-transistor, double-ended,dual-port static cell. This is useful in cache ar-chitectures, particularly as an embedded mem-ory in a microprocessor chip. This chip can besimultaneously accessed through both of the(b)BIT(c)MATCH(d)Figure 2-4. Various configurations of CMOSSRAMcells. (a) Six-transistor fullCMOS. (b) Four transistors withR-load NMOS. (c) Dual-port withdouble-ended access. (d) Content-addressable memory(CAM).14ports. Figure 2-4( d) shows a nine-transistorcontent-addressable memory (CAM) cell. Thisis used in applications where knowledge of thecontents of the cell, as well as location of thecell, are required.2.2.2 MOS SRAMArchitecturesFigure 2-5 shows (a) a typical SRAM basicorganization schematic, and (b) the storage cellarray details. Each memory cell shares electricalconnections with all the other cells in its row andcolumn. The horizontal lines connected to all thecells in a row are called the "word lines," and thevertical lines along which the data flow in andout of the cells are called the "bit lines." Eachcell can be uniquely addressed, as required,through the selection of an appropriate word anda bit line. Some memories are designed so that agroup of four or eight cells can be addressed; thedata bus for such memories is called nibble orone byte wide, respectively.In a RAM, the matrix of parallel memorycells is encircled by the address decoding logicChap. 2 Random Access Memory Technologiesand interface circuitry to external signals. Thememory array nominally uses a square or a rec-tangular organization to minimize the overallchip area and for ease in implementation. Therationale for the square design can be seen byconsidering a memory device that contains 16KI-bit storage cells. A memory array with 16K lo-cations requires 14 address lines to allow selec-tion of each bit (214 = 16,384). If the array wereorganized as a single row of 16 Kb, a 14-to-16Kline decoder would be required to allow individ-ual selection of the bits. However, if the mem-ory is organized as a 128-row X 128-columnsquare, one 7-to-128 line decoder to select a rowand another 7-to-128 line decoder to select acolumn are required. Each of these decoders canbe placed on the sides of the square array. This128-row X 128-column matrix contains 16,384cross-points which allow access to all individualmemory bits. Thus, the square memory array or-ganization results in significantly less area forthe entire chip. However, the 16K memory mayalso be organized as a 64-row X 256-column (or256 X 64) array.RowAddress12RowDecoderNColumnDecoderColumnAddress2N Rows12Vee GND! lOne CellMemory Array2N Rows2MColumns(a)Figure 2-5. (a) A typical SRAM basic organization schematic.Sec. 2.2 Static Random Access Memories (SRAMs) 15SelO ,. ~ ,Data 0 Data 0 Data m(b)DatamFigure 2-5 (cont.), (b) The storage cell array details.Most RAMs operate such that the row ad-dress enables all cells along the selected row.The contents of these cells become availablealong the column lines. The column address isused to select the particular column containingthe desired data bit which is read by the senseamplifier and routed to the data-output pin ofthe memory chip. When a RAM is organized toaccess n bits simultaneously, the data from ncolumns are selected and gated to n data-outputpins simultaneously. Additional circuitry, in-cluding sense amplifiers, control logic, and tri-state input/output buffers, are normally placedalong the sides of a cell array.The two important time-dependent perfor-mance parameters of a memory are the "read-access time" and the "cycle time." The firsttiming parameter (access time) represents thepropagation delay from the time when the ad-dress is presented at the memory chip until thedata are available at the memory output. Thecycle time is the minimum time that must be al-lowed after the initiation of the read operation(or a write operation in a RAM) before anotherread operation can be initiated.2.2.3 MOS SRAMCell and PeripheralCircuit OperationA basic six-transistor CMOS SRAM celland its layout are shown in Figure 2-6. The bitinformation is stored in the form of voltage lev-els in the cross-coupled inverters. This circuithas two stable states, designated as "1" and "0."If, in the logic state" 1," the point Csis high andpoint C6 is low, then T} is off and Tzis on; also,16C,--+--4-----------+-----+-wB(a)Chap. 2 Random Access Memory TechnologiesASCs WI.......... (b)Figure 2-6. Six-transistor CMOS SRAM cell. (a) Schematic diagram. (b) Layout. (From Bastiaens and Gubbels[3], 1988, with permission of Philips Electronics, Eindhoven, The Netherlands.)T3 is on and T4 is off. The logic HO" state wouldbe the opposite, with point Cslow and ('6 high.During the read/write operations, the row ad-dress of the desired cell is routed to the row ad-dress decoder which translates it and makes thecorrect word line of the addressed row high.This makes transistors Tsand T6 in all cells ofthe row switch Han." The column address de-coder translates the column address, and makesconnection to the bit line B and the inverse bitline Bof all cells in the column addressed.A READ operation is performed by start-ing with both the bit and bit lines high and se-lecting the desired word line. At this time, datain the cell will pull one of the bit lines low. Thedifferential signal is detected on the bit and bitlines, amplified, and read out through the outputbuffer. In reference to Figure 2-6, reading fromthe cell would occur if Band B of the appropri-ate bit lines are high. If the cell is in state HI,"then T) is off and T2 is on. When the word lineof the addressed column becomes high, a CUf-rent starts to flow from B through T6 and T2 toground. As a result, the level of 1J becomeslower than B. This differential signal is detectedby a differential amplifier connected to the bitand bit lines, amplified, and fed to the outputbuffer. The process for reading a "0" stored inthe cell is opposite, so that the current flowsthrough Tsand T} to ground, and the bit line Bhas a lower potential than B. The READ opera-tion is nondestructive, and after reading, thelogic state of the cell remains unchanged.For a WRITE operation into the cell, dataare placed on the bit line and data are placed onthe bit line. Then the word line is activated. Thisforces the cell into the state represented by thebit lines, so that the new data are stored in thecross-coupled inverters. In Figure 2-6, if the in-formation is to be written into a cell, then B be-comes high and B becomes low for the logicstate" I." For the logic state "0," B becomes lowandIi high. The word line is then raised, causingthe cell to flip into the configuration of the de-sired state.SRAM memory cell array's periphery con-tains the circuitry for address decoding and theREADIWRITE sense operations. Typical writeSec. 2.2 Static Random Access Memories (SRAMs) 17circuitry consists of inverters on the inputbuffers and a pass transistor with a write controlinput signal to the bit and bit lines. Read cir-cuitry generally involves the use of single-ended differential sense amplifiers to read thelow-level signals fromthe cells. The data path isan important consideration with the SRAMs,since the power delay product is largely deter-mined by the load impedance along the datapath. The readdata pathcircuitry can be static ordynamic. SRAMs have been designed whichturn on or turn off the various sections of datapath as needed to reduce the operating power ofthe device. The internal signals in an outwardly"static" RAM are often generated by a tech-nique called "Address Transition Detection"(ATD) in which the transition of an address lineis detected to generate the various clock signals.The input circuitry for SRAMs consists of theaddress decoders, word line drivers, and de-coder controls. Figure 2-7 shows the variousSRAMcircuit elements.RAMs are considered clocked or notclocked, based on the external circuitry. Asyn-chronous (nonclocked) SRAMs do not requireexternal clocks, and therefore have a very sim-pIe system interface, although they have someinternal timing delays. Synchronous (clocked)SRAMs do require system clocks, but they arefaster since all the inputs are clocked into thememory on the edge of the systemclock.2.2.4 Bipolar SRAM TechnologiesThe earliest semiconductor memorieswere built in bipolar technology. Nowadays,bipolar memories arc primarily used in high-speed applications. Bipolar RAMs are often"word-oriented" and require two-step decoding.For example, in a I-kb X I-b memory orga-nized as a 32-row X 32-colull1n array, the rowdecoder selects one of the 32 rows, and all of the32 b (the "word") are read out and placed in aregister. Asecond 5 b code is used to access theWORDLINEWORDBUFFERCLOCK----al(a): ~ ~ f DA2 ~ to-----WORDDATA IN(c)BIT BITBIT-((d)DATAFigure 2-7. VariousSRAM circuit elements. (a) Static row decoder. (b) Dynamic row decoder. (c) Simple writecircuitry. (d) Inverter amplifier. (e) Differential sense amplifier. (From [4}. with permission ofWiley, New York.)18register and select the desired bit. Similarly,the data are stored by writing an entire wordsimultaneously. The broad category of bipolarmemories include the SRAMs fabricated indirect-coupledtransistor logic (DCTL), emitter-coupled logic (ECL), and mixed BiCMOStech-nologies.2.2.4.1 Direct-Coupled Transistor Logic(DCTL) Technology. The architectures forbipolar SRAMs are basically similar to those ofMOS SRAMs. Historically, transistor-transistorlogic (TTL) has been the most commonly usedbipolar technology. A simple bipolar DCTLRAM memory cell consists of two bipolar tran-Chap. 2 RandomAccess Memory Technologiessistors, two resistors, and a power source. In thisconfiguration, one of the transistors is alwaysconducting, holding the other transistor OFF.When an external voltage forces the OFF tran-sistor intoconduction, the initiallyON transistorturns off and remains in this condition until an-other external voltage resets it. Since only oneof the cross-coupled transistors conducts at anygiven time, the circuit has only two stable stateswhich can be latched to store information in theform of logic 1s and Os. The cell state is stableuntil forced to change by an applied voltage.The circuit in Figure 2-8 is an expandedversion of the DCTL memory cell [5], [37]. Inthis figure, the data lines are connected to Q13.5V2.5 V _R_t-- ---t..-- ---+__~0.4 VcWrite 1 Read 1 Write 0 Read0R 2.5C1.5 VI \ 2.5VC 1 . 5 V ~/ \. ./Figure 2-8. Direct-coupled memory cell (DCTL) with Schottky diodes. (From D. A. Hodges and H. Jackson[37], with permission of McGraw-Hill Inc., NewYork.)Sec. 2.2 Static RandomAccess Memories (SRAMs) 19and Q2 through the Schottkydiodes D1and D2.Toexplainthe operationof this cell, assumethata stored 1 corresponds to the state with Q2 on.The row selectionrequires that the row voltageshouldbe pulledlow. To write a "1," the voltageon line C is raised, forward-biasing diode Dr:This forces sufficientcurrent throughR1 so thatthe voltage at node 1 increases to tum on Q2'The current gain of Q1 is sufficiently high, andit remains in saturationso that most of the volt-age drop appears across R3. When Q2 turns on,its collector voltage drops rapidly, turning offQI' The currents in RI and R2 are always muchsmaller than the current used for writing, so thatthe voltage drops across R3 and R4 are muchsmaller than Vbe(on)' In the standby condition,D1 and D2 are reverse-biased. To read a stored"1," the row is pulled low, and current flowsthrough C through D2, R4, and Q2 to R. The re-sulting drop in voltage on C indicates the pres-ence of a stored"1."2.2.4.2 Emmiter-Coupled Logic (ECL)Technology. Another popular bipolar technol-ogy is the emitter-coupled logic (EeL). TheEeL memories provide very small access timeswith typical propagation delays of less than 1 nsand clock rates approaching 1 GHz. This highperformance is achieved by preventing thecross-coupled transistors from entering into thesaturation region. Figure 2-9 shows an EeLmemorycell [37]. In this configuration, the datalines are connected to the emitters of the twotransistors. Although both transistors have two..5:::: _R.....~ - - - - - - .......-1.3V~ _R_-+- ~ . - - _ - - - _ _ + _ - -O.3V1.5VWrite 1 Read 1 Write 0 Read 0C 1.5 Vo \ - - - - - " ~x.;---.IIC 1.5V'---------------Figure 2-9. Emitter-coupledlogic (EeL) memory cell. (FromD. A. Hodges and H. Jackson [37], with permis-sion of McGraw-Hili Inc., NewYork.)20emitters each, this cell is not a TTL circuit be-cause they operate in their normal mode (as op-posed to the inverted) modes. The operation ofthe cell is based on using the multiple-emittertransistors as the current switches. The voltagelevels are selected such that these transistorsnever conduct simultaneously. The read andwrite operation is controlled by switching thecurrent in the conducting transistor from therow line to the appropriate data line.The basic operation of an ECL cell is ex-plained with Figure 2-9. Assume that a logic ' ~ I "is stored with Q} on. The row selection requiresthat both Rand R* go to the positive levels asshown. To write a "I," the column line C mustbe held low, which forward-biases the emitter ofQl' regardless of the previous state of the cell.As a result, the collector-emitter voltage of QIdrops quickly, removing the base drive from Q2'When the row voltage returns to the standbylevels, QI remains "on," with its base currentcoming from R2. Cell current flows through Q)and returns to ground through the line R. Theemitters connected to C and Care reverse-biased in the standby condition. To read a stored"1," the cell is selected in the same way as forwriting. The emitters connected to R becomereverse-biased, and the current flowing in Q1transfers to the emitter connected to C. Theresulting rise in voltage on C indicates the pres-ence of a stored "I." The writing and readingoperation for a "0" are complementary to thosedescribed for a "1."A major drawback in the ECL technologyis that a very low value of resistors is required,which results in a constant current in the storagecell. This constant current drain causes rela-tively higher power dissipation compared to theTfL or MOS memories.Another bipolar logic developed in the1970s was the integrated injection logic (I2L).This evolved from the bipolar memory cell de-sign in which the old direct-coupled transistorlogic (DCTL) was shrunk to the single comple-mentary transistor equivalent. In memory cells,lateral p-n-p transistors were used as the currentsource and multicollector n-p-n transistors asthe inverters. The major attractive feature of thisChap. 2 RandomAccess MemoryTechnologiestechnology was the high packaging densitysince the cells were quite compact, in contrast tothe conventional bipolar memory cells using re-sistors for the load impedance of the flip-floptransistors. However, I2L technology for memo-ries failed to be commercially successful be-cause of the process- and structure-relateddependencies of its speed-power performancecharacteristics. The BiCMOS technology waspreferred for high-speed and high-performanceapplications.2.2.4.3 BiCMOS Technology. In high-density and high-speed applications, vario:... ~combinations of bipolar and MOS technologieshave been investigated. The BiCMOS process ismore complex because of the additional stepsrequired. Bipolar ECL input and output buffershave been used with the CMOS memories, bothto interface to a bipolar circuit as well as to in-crease the performance. The CMOS memorycells have lower power consumption, better sta-bility, and a smaller area compared to an equiv-alent bipolar cell. Therefore, the BiCMOSdesigns offer optimization of these parameters,since the various circuit elements are selectivelychosen to maximize the performance [6]. Forexample, since the bipolar n-p-n output transis-tors provide large output drive, BiCMOS gatesare effective with high capacitive nodes, such asthose in the decoders, word line drivers, andoutput buffers. The control logic with small fan-out can still use CMOS gates. The sense ampli-fiers which require high gain and high inputsensitivity for fast sensing of small differentialbit line swings are built in bipolar logic. Figure2-10 shows the BiCMOScircuit elements with atypical mix of various technologies [7]. Therecan be some variations on this technology mix,depending upon the manufacturer's process.In a typical double-polysilicontechnologyCMOS SRAM process, the first poly levelforms the MOS transistor gate; the second polylevel forms highly resistive load resistors in thefour-transistor CMOS memory cell, and makescontact to the silicon substrate. Since a poly-to-substrate contact already exists in such aprocess, a bipolar transistor with a polysiliconSec. 2.2 Static Random Access Memories (SRAMs) 21Figure 2-10. BiCMOScircuit elements.Poly 1Poly 2Bipolar TransistorMemory Cell..GI;:::llD'50-'5o - -- =-- =- = = : .::: .:..1- IY-pre-decoder IIV-input butler ID BipolarD BiCMOSDeMOS..GI;:semitter can be produced with minimum com-plexity. The emitter is created by a dopant diffu-sion from a doped poly into the silicon substratewhere an implanted base is present. Figure 2-II (a) shows the schematic cross-section of adouble-polysilicon SRAM with second poly asa bipolar emitter [81.A high-performance CMOS process canbe obtained from a core CMOS process by theaddition of a few steps such as: (I) use of aburied layer and an epitaxial layer, (2) a base re-gion for bipolar transistors usually by ion im-plantation, and (3) an additional collector region(collector sink or collector plug) to reduce col-lector resistance. Typically. the added steps mayincrease process complexity by 10-20%. Figure2-11 (b) shows the typical enhancements to acore double-polysilicon process for creatinghigh-performance BiCMOS memories.The higher density commodity SRAMstend to exhibit a balance of speed and powercharacteristics. The various density levels ofvery high-speed CMOS and BiCMOS SRAMsare specifically designed to optimize per-formance, often at the expense of chip areaand power consumption. The new generationBiCMOS includes many improvements. such asthe use of fast data bus in the sense circuit: paral-lel test circuits using the ECL sense amplifiers;optimized division of memory matrix to reduceparasitic capacitance on the signal lines (bit.word, and decoder); and column redundant cir-cuits suitable for divided word line architectures.The use of low-resistance metal interconnects al-(a)(b)Figure 2-11. Schematic cross-sections. (a) Adou-ble-polysilicon SRAMwith secondpoly as bipolar emitter. (b)Typicalprocess enhancements for creatingBiCMOS [8).lows more cells per bit-line pair without signifi-cantly increasing the delay.A 4 Mb BiCMOS SRAM was developedby Fujitsu in 1991. It uses a wired-OR data busin the sense circuit, a column redundant circuit,and a 16 b parallel test circuit [91. Figure 2-12(a) shows a block diagram of this SRAM. Ithas a typical address access time of 7 ns, a writepulse width of 4 ns, and active current consump-tion of about 120 mA for a 4M X l-b configura-tion. A symmetrical chip layout divides the bitlines, word lines. and decoder lines to reducethe ground noise from high-speed operation.The memory matrix is divided into four planes,each consisting of 16 blocks. The column re-dundant circuit is shown in Figure 2- l2(b). The22CSW& PSAColumnDecoderCSW& PSAPLANE-SEL.Y-ADD. 3 Y-ADD. 2 -Y-ADD. 1 .....X-ADD. 1 ........ Chap. 2 RandomAccess MemoryTechnologiesCSW&PSAColumnDecoder- - -Data BaSS - -CSW& PSA(a)Normal Columns(b)Redundant Columns2nd Poly 1st AI 1st Poly 3rd Poly(c)Figure 2-12. Fujitsu 4 Mb SRAM. (a) Block diagram. (b) Column redundant circuit. (c) Cross-section. (From[9], with permissionof IEEE.)redundancy is provided by two rows and eightcolumns, which provide more flexibility thanthe conventional architecture. The column ar-rays are distributed throughout each block andcan replace cells within the block. In this 4 MbSRAM, only four redundant column arrays areplaced in the 1 Mb plane to form a redundantsection, and they are used for any column arrayin the plane. The process technology is 0.6 umtriple-polysilicon and double-metal BiCMOS.Sec. 2.2 Static Random Access Memories (SRAMs) 23Figure 2-13. Schematic cross-section of the 0.5 urnBiCMOS technology. (From [10], withpermission of IEEE.)The first polysilicon layer forms the gate elec-trodes of the MOS transistors, and the secondlayer forms the emitter electrodes of the bipolartransistors. For memorycells, the VEE lines areformed with the second polysilicon layer, andthe 50 GO loads are formed with the third poly-silicon layer. The minimum gate lengths are 0.6and 0.8 J.1m for the NMOS and PMOS transis-tors, respectively. The thickness of the gateoxide is 15nm. Figure 2-12(c) shows the cross-sectionof this BiCMOS device.A 0.5 urn BiCMOS technology has beendevelopedfor fast 4 Mb SRAMs in which bipo-lar transistors are added to an existing 0.5 urnCMOS process [10]. This process requires thegrowth of a thin epitaxial layer, as well as theadditionof three maskingsteps as follows: self-aligned buried layer, deep collector, and activebase. The original CMOS process featured self-alignedtwin-well formation, framedmaskpoly-buffered LOCOS (FMPBL) isolation, a 150 Athick gate oxide, surface-channel NMOS andburied-channel PMOS transistors, disposablepolysilicon spacer module, three levels of poly-silicon, and two layers of metallization. Figure2-13 shows the schematic cross-section of thistechnology [10]. Three levels of polysiliconareused in this process. The first layer is the gateelectrode for the CMOS transistors. The secondlayer is the tungsten-polycide/polysilicon stackP+ BURIEDLAYERN.... BURIEDLAYERN-WELL PSUBSTRATENMOS PMOS NPNthat performsthe followingthree functions: cre-ating self-aligned contact landing pads in theSRAMbit cell, formingan emitter of the bipolarn-p-n transistor, and providing a global inter-connect. The third polysilicon layer forms theteraohm resistor load for the bit cell. Thisprocess provides a peak cutoff frequency (fr) of14 GHz with a collector-emitter breakdownvoltage (BVCEO) of 6.5 V, and ECL minimumgate delays of IOSps at a gate current of 3S0f.1A/J.1m2 have been achieve