ASIC Implementation of Soft Decision ViterbiDecoder for GSM Application

T.M.Chaitanyat, P Cyril Prasanna Raj2, Veena Sanath Kumar 3I Student, M.Sc. (Engg.) , 2 Program Manager, 3 Assistant Professor,

Centre for VLSI System Design, M. S. Ramaiah School of Advanced Studies, Bangalore.

AbstractViterbi decoder is widely usedfor decoding convolutionally encoded messages in wireless communication systems like

Satellite communication, GSM and wireless LAN. Viterbi decoders employed in digital wireless communications are inlack of performance. speed, area and power dissipation. In this thesis. An ASIC implementation of Soft decision Viterbidecoder for GSM application is targetedfor high speed and area.

The design uses 3-bit soft input in Branch metric unit. Node parallel ACS architecture in Path metric unit and RegisterExchange method in Survivor memory unit. The selected algorithm is verified by developing a 'C' code. The registertransfer level description is done in Verilog hard ware description language. Test bench is developed for the design andthe fUnctionality is verified using Modelsim 5.8e. The synthesis of design is carried out using Synopsys Design Compiler.The timing analysis of the design is estimated with Synopsys Prime Time. Formal verification is carried out usingSynopsys Formality. The Physical design is done using Synopsys Astro targeting TSMC O. 13 JDIl Technology library with4-metal layer CMOS technology.

A Soft decision Viterbi decoder chip is designed with dimensions IAmm x IAmm. It operates at a maximum frequencyof 62 MHz. with an equivalent gate count of 48 k. with a decoding window length of 32-bit.

Key Words: ASIC, Viterbi decoder, Soft decision, FEC, GSM.

NomenclatureK Constraint length.M Memory cell.R Code rate.

G Generator Polynomial

Abbreviations

ACSU Add-Compare-Select UnitBMU Branch Metric UnitED Euclidean distance

FS Full rate Speech signalGSM Global System for Mobile CommunicationsMU MultiplexerPMU Path Metric UnitSEN Shuffle exchange networkSMU Survivor Memory UnitSP Survivor path length.VD Viterbi Decoder

1. INTRODUCTION

During the past few years, the functionality of theGSM mobile communication service has become moreand more versatile. The cellular phone executes datatransmission and receiving very frequently. When data istransmitted through a noisy communication channel withno error protection, erroneous results at the receivingend. Such impairment could be originated from thenoise, fading and jamming. To impose an effectiveprotection on the data, several methods could be appliedon data transmitter and receiver, e.g. by using a higherpower transmitter, a larger antenna which results in highcost and area. A popular technique called channel codingis used to overcome the problem with good performanceresults by reducing cost and area with high protection ondata.

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Channel coding and decoding becomes favorableamong the others because it costs least power, physicalsize and is suitable for VLSI implementation. The mostfrequently seen channel coding and decodingmethodologies in the digital domain are convolutionalcoding and Viterbi decoding. Viterbi Decoding is apopular topic for chip design in communication systemdesign. There are several convolutional decodingtechniques described in [I, 2-9]. Here, the Soft decisionViterbi algorithm is chosen as the convolutional codingdecoder. The focus is the ASIC implementation of theSoft decision Viterbi decoder.

A convolution encoder typically will generate two orthree output bits for each input bit. The output bitsgenerated by the encoder are dependent on the currentinput bit, as well as the state of the encoder. The state ofthe encoder is represented by several bits, which precedethe current bit. If the state of the encoder consists of thethree previous bits, then there are eight possible encoderstates, one for each possible combination. This encoderis said to have a constraint length K = 4 since the outputdepends on four bits (the current bit plus three previousbits). The code rate r is defined as the number of inputbits divided by the number of output bits. Thus, anencoder which produces two output bits for every inputbit is said to have rate r = 11,. A good discussion ofConvolution encoders can be found in [1][2][3].

The Viterbi decoder is the most important part in thereceiver; the Viterbi algorithm is one of the mostcommon decoding algorithms used for decodingconvolutional codes. In 1967, Viterbi introduced adecoding algorithm for convolutional codes, which hassince become known as the Viterbi algorithm [2]. Later,Omura showed that the Viterbi algorithm was equivalentto a dynamic programming solution to the problem offinding the shortest path through a weighted graph.

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Finally, Forney recognized that it was, in fact, amaximum likelihood decoding algorithm for convolutioncodes; the decoder output selected is always the codeword that gives the largest value of the log-likelihoodfunction. Forney also was the first to point out thatthe Viterbi algorithm could be used to produce themaximum likelihood estimate of the transmitted

sequence over a band-limited channel with inter-symbolinterference.

To understand Viterbi's decoding algorithm, it isconvenient to expand the state diagram of the encoder.State diagram is obtained from the encoder throughwhich a state table is generated. Using this state table aTrellis structure is generated which is used in algorithmfor decoding purpose. A trellis diagram is an extensionof a convolutional code's state diagram that explicitlyshows the passage of time. The convolution code in aGSM system uses a rate of r = Y, and K = 5, [3][4] asshown in fig. I.

Fig. 1 Convolution encoder for GSM

which mean that five consecutive bits are used tocalculate the redundant bits and that for each data bit anadditional redundant bit is added. . Before theinformation bits are encoded, four bits are added at theend ofthe information bits. These bits are all set to zeroand are used to reset the convolutional encoder to itsinitial state. The different bits have a particular role inthe speech coding processing, and have different priorityfor various reasons. The 189 bits (Class la with paritybits and Class Ib) enter the convolutional encoder, and2 x 189 = 378 bits emerge, the 78 Class 2 bits areappended after the 378 coded bits to yield a total of 456bits [3][5]. The Viterbi decoder decodes these bits andthe resultant output is 189 bits.

The relation between the constraint length of theconvolutional encoder and the number of states isexponential. The complexity of the decoderexponentially increases against the constraint number.For GSM/FS, there are 16 states in the trellis. 32 Addand 16 Compare and Select operations have to be donefor every decoded bit. Comparing the units such as theBMU, PMU and SMU, the frequency of Viterbi decoderdepends on number of ACS operations in PMU. Thedecoding delay depends on the SMU operation [1][2].

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The Viterbi algorithm can be divided into threefunctional units as shown in fig. 2, the branch metric unit(BMU), path metric unit (PMU) that contains add­compare-select unit (ACSU), and the survivor memoryunit (SMU). While the BMU, PMU, ACSU performarithmetic operations such as addition, and maximum /minimum selection, the SMU has to trace the course of apath with the help of decision bits that were generated inthe ASCU.

~BMU~

Memory

Fig. 2 Block diagram of VDTherefore, careful design of the decoder's architecture

is crucial to the realization of a practical decoder thatadheres to high performance, low area and powerrequirements of modern systems.

To improve the performance of the Viterbi decoderSoft decision input is to be considered over the harddecision input. In path metric updating, node parallelACS results in better performance compared to thenormal ACS. The trace back operation in survivormemory unit has two methods namely trace backmethod, Register exchange method

The Register Exchange algorithm (RE) is the moststraightforward method to manage the decision vectorsproduced during the path metric updating operation inSurvivor memory management. The main advantage ofthis architecture is its small latency. After T cycles of thesurvivor memory management operation, the architectureis able to deliver the decoded sequence at a throughputrate that is matched to the rate at which the ACS unitdelivers new decision vectors. Another advantage of thisarchitecture is the regularity and simplicity of theprocessing elements (a register and a multiplexer). It isclear that when the number of trellis states is large, thisarchitecture becomes impractical due to the poor densityof storage and the large area required interconnecting theprocessing elements. In addition, since the registers inthe array are updated at every cycle, the powerdissipation of this architecture is quite large.Consequently, register exchange architectures areattractive only when the size of the trellis is small (K <6) [6][7][8].

In the Trace-Back algorithm (TB), the decision bitsgenerated by the ACS unit at each processing interval actas pointers to the visited states of the surviving paths.The principle of operation is very simple and is thenatural way of decoding the output sequence from thedecision vectors. The idea underlying the trace-backoperation consists in the utilization of the decision bits tofind the ancestor states of the best surviving path. Moreprecisely, the trellis state visited by the surviving path attime t, together with its decision bit, serve to find theancestor state visited by the surviving path at time t- I.

Vol. VI, No.1, April 2007

This way, all the trellis states visited by the survivingpath can be traced back in time and thus, the decodedsequence can be found. The main advantages of the TBalgorithm are the simplicity of operation, low powerconsumption and the large storage density since we canuse RAMs to store the decision vectors. As a

consequence, this algorithm is especially attractive fortrellises with large number of states .On the other hand,the main drawback of this approach is the decodingdelay since it has to wait for all the received sequence tobe processed by the ACS unit before starting the trace­back operation.

2. VITERBI DECODER IMPLEMENTATION

2.1 Specifications

The specifications chosen for the Viterbidecoder implementation(3].

• K (constraint length) = 5 (16 states),• R (code rate) = Y,• Generator polynomials

g (0) = 1+ M3 + M4 , .•.••..•..•...... (1)

g(I)= l+M +M3 +M4 , .....••.•• (2)• Input 3-bit soft decision• SP 32.• Target Frequency 30MHz.

2.2 Branch Metric Unit

The two 3-bit soft decisions are combined to form four

possible 4 bit branch metrics i.e. BMUOO,BMUOI,BMUIO, BMUII as shown in fig. 3. The branch metricsare generated using modified Euclidean distance (ED).The metrics on the branches can be any of thesecombinations(OOO,OOO),(000,111), (111,000), (111,111)which are generated from equations I and 2. Thecalculation of distance between 3-bit soft decision inputs('101,000') from branch values ('III,OOO')is 2 and fromthe ('000, III ') is 12. The maximum value it can take is14. The calculation of distance is explained in reference[6][7][8].

3-hjtj

III I

~ t

CfJ CfJBMUOO

BMUOIBMUIOBMUII

Fig. 3 Block diagram ofBMU

2.3 Path Metric Unit

This block consists of ACS and SEN. It calculates the

path metric of the present trellis state and stores the

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related path metric in memory PM[t] and it generates adecision bit corresponding to that path metric and it isassigned to the survivor memory unit (SMU) as shownin fig. 4. The shuffle exchange network (SEN) stores themetric value selected by the ACS, and these aretransferred to the pre specified states in next time cyclePM(t+ I) as shown in fig. 4, where the inputs to the nodesin the next time cycle (t+ I) are BMU value and SENvalue, the architectures are explained in reference[8][9][ 10].

PM[t]

Fig. 4 Block diagram ofPMUWhen the input distance from the branch metrics isready, the adder module adds the result of the previouspath metric 'PM [t-I)' and the distance calculated fromthe BMU in the present cycle. The outputs from theadder are fed to the comparator. Here comparatorcompares two values and depending on the smallestvalue a decision bit is generated .The output ofcomparator controls the MUX and the smallest pathmetric value is assigned to the 'PM[t)' register, and thedecision bit corresponding to the PM[t] is send to theSMU[9][1O][11] as shown in fig. 5.

WM[t]-.+PM t-11 I

It-----

Fig. 5 Block diagram of ACS

2.4 Survivor Memory Unit

In practice information sequences are very long. It is notpractical to wait until the entire sequence is received tobegin decoding. This would result in long delays and

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3.2 Test Bench Results For Viterbi Decoder

Fig. 7 Simulation result

transmitted is 11010 and the data is received with outerror.

with 0"01 1"llUI"

d" Qd." nut ul.

01 itatc01010

29,14.27,26

!':miltthil tlumbilr,3<:

IS

5722 ( wllh ""'" ,,,pu", )171

2<;,

17, ( <loco""d O.)tpUI$ )26.27 (,)1 .t~tt;t 1010

tJ),t9l: lhll numbt:r.5~~:;2723t;t

Example I

it,!>ol lo 01010

enler the numbenooii.,Qoo"1

o

21.Q,21.14 01'tlll,,01010

Example 2

"put 1H:i10

lilJ.l9'! Ih" tlun'll:>"r.7io7I)7(;)

o7(i

., 1.O.21.11.J~1#1{1til11 0 j 0

I----[}t

D+

require large amounts of storage. It has been made thatdecision can be made on the constraint length K. Withsome practical results we have a thumb rule that we candecode the data after the 5*k stages with littleperformance degradation. Survivor memory unit (SMU)can be implemented using Trace back method or registerexchange method. The Register Exchange algorithm isthe most straightforward method to manage the decisionvectors produced during the path metric updatingoperation. This method stores the decision bits obtainedfrom the PMU in registers. Depending on the PMUselection the bits are traversed according to the trellis .According to the trellis path the data is shifted from onestate register to another state register. So the data isshifted with respect to the ACS operation with out anydelay. The architecture used for this approach is aregister and mux as shown in fig. 6. As we have chosenthe SP to be 32, a 32-bit register is used to store the bits.After 32 cycles, all the metrics at the PMU are comparedand lowest metric is chosen among them and the datacorresponding to that in SMU is selected as the output

Fig. 6 Register exchange method

The main advantage of this architecture is its smalllatency where we obtain the output with the ACSoperation [3][11][12].

Test bench is generated for the soft decision Viterbidecoder architecture, for 6-bit input. The actualtransmitted data is 111000; it is input to the convolutionencoder represented as data in Fig.7. The encoded datafrom convolution encoder is 12 bits. The input to the VDare "a" and "b" with 18-bit input which are 3-bit softdecision bits as shown in Fig.7.

3. RESULTS AND DISCUSSIONS

3.1 Simulation Result Using C

C code was developed to the above discussedarchitecture. The following fig. 7 shows the outputresults of the Viterbi decoder for constraint length k=3.With 3-bit soft decision input for 5-bit input data. Here7 represent III and 0 represents 000. These are therepresentations of soft decision data.

In Fig.7 two examples are shown, the lefthand side values are original input data and the inputs onthe right hand side are input with error. In example 1 theinput transmitted is 01010 and error is added in thechannel as shown in the data on right hand side .TheViterbi decoder decoded the original information as01010 with out error, and in example 2 the data

The following result shows the representationof original data as Data and the conout is to compare thetransmitted data and the received data. The result showstwo soft decision data's with correct and error inputs.The first input data is the data with out error to the VDand the second data is the data with error input to theVD, now the Viterbi decoder operation is performed andthe output obtained from the Finrout is 111000, i.e. theoriginal data is decoded even after with the error input.

The conout shows that the received data is

equal to the transmitted data representing 000000. ifthere are any error the convout shows the corrupted bitposition compared with the original input . Thereforefrom the simulation result it is clear that the transmitted

data 111000 is received at the output fin rout with outerror as shown in the fig.8.

68SAsTECH Vol. VI, NO.1, April 2007

Fig. 10 Final Chip View of Soft decision VD

The architecture in the design uses soft decisionapproach in BMU, node parallel ACS structure in PMUand register exchange method in SMU to meet thespecified requirements. The Soft decision Viterbidecoder chip is designed with dimensions l.4mm xl.4mm. It operates at a maximum frequency of 62 MHz.with an equivalent gate count of 48 k, with a decodingwindow length of 32-bit targeting 0.13 ~m technologywith 4-metallayer CMOS technology.

50245189.65 um21514355.68 um256.4812%40.2904%81.2904%0.15ns

TSMCO.13~m1.2 V32-bit0.15ns5081.2904%1.4x1.4 mm262 MHz

Number ofIO Pad CellsTotal Standard Cell AreaTotal Pad Cell AreaCell/Core RatioCell/Pad Core RatioCell/Chip RatioFinal slack

TechnologyVoltageWord lengthSlackNumber ofIO Pads

Cell/Chip RatioDie SizeMax Frequency

Floorplan information Report:

4. CONCLUSIONS

3.5 Final ASIC Result

Fig. 9 Result ofVD for GSM

Fig. 8 Test bench result ofViterbi decoder

3.3 Simulation Result of Viterbi Decoder ForGSM

The following figure shows the simulation result ofViterbi decoder for the 378 bit frame, 378x3-bit data areinputs to the Viterbi decoder, as the survivor path lengthis 32, the output is decoded at the 32-cycle with adecoding window length of 32- bit data. So the totaldelay to get the final output is the actual length of thedata i.e. 189 plus 6 clock cycles. the simulation resultwith 32-bit decoding window length is shown in the fig.8

3.4 Synthesis and Floorplan InformationReport

Synthesis Report:

Total number of portsTotal Dynamic PowerDesign Compiler SlackPrime Time SlackViolations

: 42: 21.0403mW: 3.02 ns: 2.41ns: no

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[1] Bernard Sklar, "Digital Communications­Fundamentals and Application", Published byPearson education. Year 2003.

[2] Viterbi.A.J, "Convolution codes and theirperformance in communication systems,"IEEE Transaction on Communications,vol.com-19, pp. 751 to 771, October 1971.

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[3] Yingtaojiang, YiyanTang, YukeWang,M.N.S.Swamy , "A Trace-back free Viterbidecoder using a new survival pathmanagement algorithm", IEEE InternationalSymposium on Circuits and Systems, vol. I,no.I, pp 1-261 - 1-264, May 2002.

[4] www.freescaIe.com. browsed on (12thSeptember 2006).

[5] Thierry Turletti , "A brief Overview of GSMRadio Interface", Telemedia Networks andSystems Group Laboratory for ComputerScience Massachusetts Institute ofTechnology, pp.I-IO, March 1996.

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[9] Henry Hendrix ,"Viterbi DecodingTechniques in the TMS320C54x Family"SPRA07\. Texas instruments, Year 1996.

[10] SamirKumar Ranapra, Dong sam ha , "A Low­power Viterbi decoder design for wirelessCommunications Applications", Inl ASICConference, Washington DC, pp 1-5,September 1999.

[11] Wang Kaiming Wu Weiling, "ViterbiHardware Implementation for GSM". IEEEtransaction on Communications", vol.3,pp.I20 - 122, October 1993 .

[12] lun Jin Kong, Keshab K. Parhi, "Low-LatencyArchitectures for High-Throughput RateViterbi Decoders". IEEE Transactions on

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