asr1000 overview

ASR 1000 Overview

© 2006 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialPresentation_ID 1

Overview

ASR 1000 Overview

� Next-generation of Midrange router family

2RU/4RU/6RU chassis

5 / 10 / 20 / 40 Gbps forwarding

Supporting same feature set at different price performance points

� ASR 1000 Differentiators

Highly available carrier-class design

Integrated services (SBC, FPM, Security..)

© 2007 Cisco Systems, Inc. All rights reserved. Cisco ConfidentialASR 1000 Overview Jul 07 2

Integrated services (SBC, FPM, Security..)

State of the art QoS

Unmatched midrange scalability & performance

Feature velocity

� Feature richness provides deployment flexibility

Support for Service Provider & Enterprise features

BNG (BRAS, LAC, LNS)

IPSec Termination

Distributed PE / MSE

High-speed CPE

…

Cisco ASR 1000 Series Introduction

SPA Interface ProcessorCan take Up to 4 HH SPAs

SPA SlotsRe-Uses existing SPAs


Embedded Services Processor40 Cores with Traffic Manager

Route Processor1.5 GHz, Up to 4GB DRAM

ASR 1000 Product Family

ASR 10022RU

ASR 10044RU

ASR 10066RU

SPA Slots 3-Slot 8-Slot 12-Slot

Aggregated Services and Scale

Number of ESP Slots 1 1 2

Integrated


Number of RP SlotsIntegrated

(RP1)1 2

Number of SIP SlotsIntegrated

(SIP10)2 3

Cisco® IOS®

RedundancySoftware Software Hardware

Built-in GigE 4 N/A N/A

Height 3.5” (2RU) 7” (4RU) 10.5” (6RU)

Bandwidth 5–10 Gbps 10–40+ Gbps 10–40+ Gbps

Performance 4–8 Mpps 8–16+ Mpps 8–16+ Mpps

Air Flow Front to Back Front to Back Front to Back

Power Supply (Watts) 470 765 1275

ASR 1000 – Product Positioning

>300G

7600, GSR,CRS

ASR 1000 10K

20G

18G


3845

7200< 3G

5G

List Price

7304-NSE

10G

ASR 1000 with

ESP10

ASR 1000 with

ESP20

ASR 1000 2RU w/ ESP5

10KPRE-3

Price includes Chassis, engine

ASR 1000 Hardware & System Architecture


ASR 1000 Building Blocks

� RP (Route Processor)Handles control plane traffic

Manages system

� ESPHandles forwarding plane

traffic

RP(standby)

RP

Interconn.

ESP(active)

FECP

QFP subsys-

temCrypto assist

ESP(standby)

FECP

QFP subsys-

temCrypto assist

RP(active)

RP

Interconn.


� SPA Interface ProcessorHouses the SPAs

� SPAsProvide interface

connectivity

� Centralized Forwarding Architecture

All traffic flows through the ESP

Interconn. Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

Midplane

SPA-SPI, 11.2GbpsHypertransport, 10Gbps

ESI, (Enhanced Serdes Interface) 11.5Gbps

Route Processor – RP1

� General Purpose CPU based on 1.5GHz Freescale 8548

� Memory:

1. DRAM: Default: 2 GB; Max: 4 GB

2. NVRAM: 1G of Internal Flash for code storage, boot, config, logs, etc.

� Management Interfaces:

– Management ethernet management port, auxiliary port, console port


� Storage:

– For core dumps, failure capture, etc; 40 GB Hard Disk Drive (rotary) initially; Solid-state drive (SSD) option at FCS (TBD)

– External USB flash for IOS configs or File copying

� Communications paths to other cards (for control and for network control packets)

� Stratum-3 network clock circuitry and BITS reference input (for synchronizing SONET links, etc.)

� Miscellaneous control functions for card presence detection, card ID, power/reset control, alarms, redundancy, etc.

2RU

� Integrated RP1. Exact same hardware features as RP1 with the following exception

– DRAM – 4G default

– No Hard Drive for Mass storage

– eUSB of 8GB


– eUSB of 8GB

• 7GB used for mass storage

• 1 GB used as NVRAM for code storage, boot, config, logs, etc

� Modular ESP; supports ESP5, ESP10, ESP10-N

� Built-in 4XGE ports – feature/performance parity to GE SPA

� Software redundancy feature supported with IOS processes

� Centralized, programmable forwarding engine (i.e. QFP subsystem (PPE) and crypto engine) providing full-packet processing

ESP10-N does not support crypto engine

� Packet buffering and queuing/scheduling (BQS)

For output traffic to SPA Interface Processors/SPA’s

Embedded Services ProcessorsESP5 , ESP10, ESP10-N, ESP20


Processors/SPA’s

For special features such as input shaping, reassembly, replication, punt to RP, etc.

� Interconnect providing data path links (ESI) to/from other cards over midplane

Transports traffic into and out of QFP10

Input scheduler for allocating QFP10 BW among ESI’s

� FECP CPU managing QFP, crypto device, midplane links, etc

ESP10-N does not support crypto device

Quantum Flow Processor Architecture, 1st generation

+ +Quantum

Flow Processor Software


Multi-Core (40) Packet Processor Traffic Manager (BQS)

+ +Software

1. Scale � 100s of resources & massive feature scale2. Performance � Designed to deliver 5-100s of Gbps3. Feature Velocity � Software designed to deliver a

common forwarding plane for multiple systems.4. Multi-Generational � This is only the 1st Generation!

QFP Summary

• Packet Processing Engine (QFP-PPE)

– 40 Packet Processors – 4 Contexts (threads) each

– Up to 1.2GHz (Tensilica ISA) processors + DRAM packet memory

– Single TCAM4 I/F (can cascade 1-4 devices)

– C-language for feature development (extensive development support tools)


tools)

– HW assist for flow-locks, look-ups, stats, WRED, policers, range lookup, crypto, CRC

• Buffer/queue subsystem (QFP-BQS)

– HW hierarchical 3-parameter (min, max & excess) scheduler

– Fully configurable # of layers based on HQF

– Priority propagation through the multiple layers

ASR 1000 ESP Generations

ESP5 ESP10 ESP10-N ESP20

Bandwidth 5Gbps 10Gbps 10Gbps 20Gbps

Based on QFP10 QFP10 QFP10 QFP10

# of Processors 20 40 40 40

Roadmap


# of Processors 20 40 40 40

Clock Rate 900 Mhz 900 Mhz 900 Mhz 1.2 Ghz

Crypto Engine BW 1.8Gbps 4Gbps NA 8Gbps

QFP Memory 256MB 512MB 512MB 1GB

Packet Buffer 64MB 128MB 128MB 256MB

TCAM 10Mb 10Mb 10Mb 40Mb

SPA Interface Processor – SIP10

� Physical termination of SPA

� Supports up to 4 SPA’s

4 half-height, 2 full-height, 2 HH+1FH

full OIR support

� Does not participate in forwarding

� Limited QoS


– Ingress packet classification – high/low

– Ingress over-subscription buffering (low priority) until ESP can service them. Up to 128MB of ingress oversubscription buffering

� Capture stats on dropped packets

� Network clock distribution to SPA’s, reference selection from SPA’s

� IOCP manages Midplane links, SPA OIR, SPA drivers

System Architecture - Dataplane

RP(standby)

RP

Interconn.

ESP(active)

FECP

SP

I4.2 QFP

subsys-tem

Crypto assist

ESP(standby)

FECP

SP

I4.2 QFP

subsys-tem

Crypto assist

RP(active)

RP

Interconn.

� All data forwarding is through ESP

� Exception: Punt path for Legacy protocols –handled by the RP

� Interconnect ASIC in each of the functional


Interconn. Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

Midplane

SPA-SPI, 11.2Gbps

Hypertransport, 10Gbps

ESI, 11.5Gbps

each of the functional elements provides the backplane connection through ESI links

� ESI (Enhanced Serdes Interconnect) links are used for Data forwarding

� SPA-SPI links connect to the backplane through the SPA-Agg ASIC

System Architecture Control Plane

� Two different control plane links separate from the dataplane links

–Ethernet out-of-band Channel (EOBC).

–I2C - Monitor health of hardware components

RP(Standby)

RP(active)

ESP(Standby)

FECP

QFP subsys-

temCrypto assist

ESP(active)

FECP

QFP subsys-

temCrypto assist

RP RP


hardware components

� SPA control links

Run between IOCP and SPAs

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

SPASPA

IOCPSPA

Agg.

…

Interconn.

Interconn.Interconn.

Midplane

EOBC - 1Gbps

I2C – Inter Integrated Circuit

SPA ControlSPA Bus

What does the ESP Bandwidth mean?

� ESP bandwidth denotes the total ‘output’ bandwidth of the system, regardless of the direction

� High priority traffic (as long as it is not over-subscribed - Example: <=10G for ESP10) will not be affected by this bandwidth limit

� ESP10 Examples:

5G 5G

5G5GASR 1000

1G 8G

2G 2GASR 1000


5G5GASR 1000

5G Unicast in each directionTotal Output bandwidth 5+5=10

2G 2G

1G Multicast with 8X replication in one direction2G unicast in the other directionTotal Output bandwidth 8+2=10G

5G 5G

6G6G

5G Unicast in one direction & 6G Unicast in the other directionTotal output bandwidth (5+6=11) exceeds 10G; Only 10G will go through

1G 10G

1G1G

1G Multicast with 10X replication in one direction1G Unicast in the other directionTotal bandwidth (10+1=11) exceeds 10G; only 10G will go through

ASR 1000

ASR 1000 ASR 1000

� Total bandwidth of the system is determined by the following factors

– The type of forwarding engine : ESP5 or ESP10 or ESP20

– The type of SPA Interface Processor

� SPA Interface Processors in the system share the ESP bandwidth, regardless of the type of the SIP – 2XSIP in 4RU chassis and 3XSIP in 6RU chassis

ASR 1000 System Bandwidth


– ESP5 : 5G bandwidth shared among all SPAs (&built-in interfaces on ASR 1002)

– ESP10 & ESP10-N : 10G bandwidth shared among all SPA Interface Processors

– ESP20 : 20G bandwidth shared among all SPA Interface Processors

� The SIP bandwidth is the bandwidth of the link between one SPA Interface Processor and the ESP

– SIP10 :10G link between SIP and ESP

ESP & SIP Configurations

ESP10

SIP10

SIP10

10G

ESP20

SIP10

SIP10

20G


SIP10

10G shared by 3 XSIP10 20G shared by

3XSIP10

SIP10

SIP10

I/O – Shared Port Adapters

ATM:ATM: • T3/E3• OC3• OC12

• T3/E3• OC3• OC12

POS:POS: • OC3• OC12• OC48• OC192

• OC3• OC12• OC48• OC192

POS/DPT/RPR:POS/DPT/RPR: Channelized:Channelized:• T1/E1• T3• T1/E1• T3

Ethernet:Ethernet: • FE• GE• 10GE

• FE• GE• 10GE

Clear Chan.:Clear Chan.: • T3/E3• T3/E3

• SPAs currently supported in other Cisco Platforms will also be supported on ASR 1000

• Please refer to Roadmap for roll-out plan

• SPAs currently supported in other Cisco Platforms will also be supported on ASR 1000

• Please refer to Roadmap for roll-out plan

• OC3• OC3

© 2007 Cisco Systems, Inc. All rights reserved. Cisco Confidential 20

• OC192• OC192• STM1• OC12• OC48

• STM1• OC12• OC48

Double- WideSPA

Double- WideSPA

Single-HeightSPA

Single-HeightSPA

Double- HeightSPA

Double- HeightSPA

CEOP:CEOP: • OC3• T3/E3• T1/E1

• OC3• T3/E3• T1/E1

RPRRPR • GE• 10GE• GE• 10GE

Not supported on ASR 1000Not supported on ASR 1000

X

High Availability


ASR 1000 HA Highlights

� ASR 1000 leverages Cisco IOS HA infrastructure – NSF/SSO, ISSU

� 1+1 redundancy option for RP and ESP

– Active and standby

– No load balancing

� RP’s are separate from ESP’s


� RP’s are separate from ESP’s

– Switchover of ESP does not result in switchover of RP

– Switchover of RP/IOS does not result in switchover of ESP

� Single RP may be configured with dual IOS for SW redundancy (single RP only)

� No redundancy for SIP or other I/O cards

– SPA plugs into a single SIP

� Protection against SPA or SIP failure is via APS or Y-cable redundancy feature (Future: requires SPA support)

System Architecture – Distributed Control Plane

ActiveRoute

Processor

StandbyRoute

Processor

ZeroPacketLossRP fails

HW or SW

StandbyBecomes

Active


ActiveESP

StandbyESP

SPA Interface Processor

SPA SPA

SPA SPA


SPA SPA

SPA SPA


SPA SPA

SPA SPA

Separate and independent internal communication link for control plane (GE)

System Architecture – Centralized Data Plane

ActiveRoute

Processor

StandbyRoute

Processor

MinimalDataInterruption


ActiveESP

StandbyESP

SPA Interface ProcessorSPA Interface ProcessorSPA Interface Processor

SPA SPA SPA SPA SPA SPA

SPA SPASPA SPA SPA SPA

Active ESP fails(SW or HW)

StandbyBecomes Active

• All packets processed by QFP for forwarding

• Separate and Independent links for Data Plane communication (ESI 11.5G)

Software Architecture – IOS-XE

Route Processor

� IOS-XE = IOS + IOS-XE Middleware + Platform Software

� Operational Consistency - same look and feel as IOS Router

� IOS runs as its own Linux process for control plane (Routing, SNMP, CLI etc). 32bit and 64bit options.

� Linux kernel with multiple

Chassis Chassis ManagerManager

InterfaceInterfaceManagerManager

ForwardingForwardingManagerManager

IOS 12.2SR

(Active)

IOS-XE “Middleware”


Embedded Services Processor


Control Messaging

Kernel Kernel

Kernel

QFPClient/Driver

� Linux kernel with multiple processes running in protected memory for

– Fault containment

– Re-startability

– ISSU of individual SW packages

� ASR 1000 HA Innovations

– Zero-packet-loss RP Failover

– <50ms ESP Failover

– “Software Redundancy”

SPADriver

SPADriver

SPADriver

SPADriver


ChassisChassisManagerManager


ChassisChassisManagerManager

Software Redundancy on 4RU/2RU Single RP/ESP

� Stand-by IOS process in RP in the single-engine 4RU/2RU system

� Two IOS process in a single RP function similar to different processes on separate

Route Processor

IOSBackup

IOSActive

Active IOS Process

Stand-by IOS Process

Chassis Chassis InterfaceInterfaceForwardingForwarding

IOS-XE “Middleware”


processes on separate RP

� Support all NSF/SSO features supported by dual-RP systems

� Requires additional RP memory – 4G

Linux Kernel

Chassis Chassis ManagerManager



IOS XE IOS XEIOS XE IOS XE IOS XE IOS XE

ASR 1000 Innovations: IOS XEASR 1006 Control & Forwarding Plane Redundancy

RP Active

IOS XE Upgrade IOS XE Upgrade IOS XE Upgrade

RPStandby

RP Active

RPStandby

RP Active

RPStandby

Zero Packet LossZero Packet Loss

ISSU ISSU

Validated


50ms Traffic InterruptionZero Packet Loss

QFP QFPQFP QFP QFP QFP

ESPActive

ESPStandby

ESPActive

ESPStandby

ESP Active

ESPStandby

Step 1

ISSU

Step 2

ISSU

IOS XEIOS XE

ASR 1000 InnovationsSoftware Virtualization on Cisco ASR 1002 and 1004

IOSActive

IOSStandby IOS

ActiveISSU ISSU

IOS Upgrade IOS Upgrade IOS Upgrade

IOSStandby

IOS XE

IOS Active

IOSStandby

IOS XE

IOS Active

IOSStandby

ISSU ISSU

Step Step

Validated


… Industry first,delivering hitless upgrades without hardware redundancy

Zero Packet LossZero Packet Loss

Step 1

Step 2

asr1000 overview

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