CONCORDIA UNIVERSITY

DEPARTMENT OF COMPUTER SCIENCE AND SOFTWARE ENGINEERING

COMP 228 Fall 2009 ASSIGNMENT 2

Issued: Oct 1, 2009 Due: Oct 15, 2009 ___________________________________________________________________________________

1. Digital Logic [30%] (a) Show the validity of the following equivalences algebraically or by truth table. (i) xyz’ + x’yz’ = yz’

(ii) xy’z’ + x’y’z’ + xyz’ + x’yz’ = z’ (b) Do problem 32 on page 159 of your text. (d) Design a circuit with three Boolean inputs (a, b and c) representing the bits of a

binary number, and three Boolean outputs (x, y an z). The output xyz (as a binary number) is always equal to (abc + 010) mod 8. For example, if abc = 111, then xyz = (110 + 011) mod 8 = 001. Show both the truth table and the circuit involving NAND only. Assume the inverted form of each input variable (i.e. x’) is also available. Try to minimize the number of NAND gates used.

(e) Draw the state transition diagram of the following digital system consisting of three D flip flops and a single NAND gate. Assume initially Q1Q2Q3 = 000.

(f) What is the main difference between a combinational logic circuit and a sequential

logic circuit? Is a clock always used in a sequential circuit?

2. Instruction encoding [18%] A 1-address computer is one whose instruction can contain at most one operand address. MARIE is an example of such a computer. Typically each instruction is stored as a single word in the memory. Assume the following machine details. (i) A word contains n bits, and k bits (k < n) are used to encode each opcode. (ii) There are 200 distinct opcodes in the ISA. (iii) The largest program requires 64M words of memory to run. (a) What is the minimum value of k required? What is the minimum value of n

required? Keeping minimum value of k, what is the maximum number of opcodes that can be used?

(b) If the size of each word must be an integer number of bytes, what is the minimum value of n required? What is largest memory that can be used in this computer then?

ck Q1 D1 clock

ck Q2D2 ck

Q3D3

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COMP 228 (System Hardware), Winter 2009 ⎯ Assignment 2 Page 2

(c) Now consider a 2-address computer whose instruction can contain two operand addresses. Redo (a). Compare the two results and comment on the cost-effectiveness of the change (from 1-address to 2-address design).

3. Memory organization [24%] A 2G x 4 byte memory system is constructed using 512M x 1 byte RAM chips. (a) How many RAM chips are needed? (b) How many address bits are needed for the memory system? (c) How many address bits are needed for each RAM chip? (d) How many RAM chips are selected for each memory access? (e) Show a 2-D layout of the RAM chips and explain what happens when memory

address 25 is applied to access the memory system. (f) What is the main advantage of memory interleaving? (g) Why is low-ordering address interleaving more often used than high-order address

interleaving? (h) In a 4-way (low-order) interleaved memory system, if a processor wants to access 100

words from memory locations (hex) 1000, 1004, 1008, … etc, how many memory cycles will be needed for those 100 accesses?

4. Buses and Clock [28%] In a computer system, often a system bus is used to connect among CPU, memory and other internal components/devices and an external bus expands the connection with some selected subset of peripheral devices. (a) Explain the differences between proceesor cycle, memory cycle and bus cycle. (b) A computer with a faster clock may not actually be faster in running a given

machine language program when compared with another system running the same machine language program. Referring to the equation on p. 184 of your text, explain some possible causes of this phenomenon.

(c) Which of the following bus arbitration schemes is fastest? (i) daisy chain, (ii) distributed self-detection, (iii) centralized parallel. Justify your answer.

(d) What is I/O interrupt? What problem would a user face if I/O interrupt is not available in a computer system?