at94 training 2001slide 1 at17 series eeprom configuration memories atmel corporation 2325 orchard...

AT94 Training 2001Slide 1

AT17 Series EEPROM Configuration Memories

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

Hotline

(408) 436-4119

[email protected] OR [email protected]


architecture behave of CNT6 is

signal SQA, SQB : integer range

0 to 6 := 1;

begin

QA <= To_Vector(3,SQA);

VHDL/VerilogSynthesis

Schematic

Place & Route

Tpd = 10 nsFmax = 100 MHzSize = 12x8 CellsIcc = .2mA/MHz

101000100110100111101011

Timing Analysis

ATDH2200ATDH2225Third Party Programmer

Configurator Download

Design Entry &Simulation

Physical Design(Including synthesis compiler)

Board Layout

Libraries &Interface

Macro Generators

Behavioral

ProgramConfigurationMemory


FPGA/FPSLIC ISP Configuration Memories65K, 128K, 256K, 512K, 1M, 2M & 4M Serial EEPROMs

(Direct Xilinx & Altera OTP Replacement)

• 7 Sizes – AT17C65 - 65K Version (8/20 pins)

– AT17C128 - 128K Version (8/20 pins)



– AT17C010 - 1Meg Version (8/20 pins)

– AT17C020 - 2Meg Version (20 pins)

– AT17C040 - 4Meg Version (44 pins) Q3/2001

• Interface with any Atmel or other SRAM FPGA & FPSLIC- AT6000/AT40K (Atmel FPGA) - OR2/3/4Cxx (ORCA)

- AT94K (Atmel FPSLIC) - Altera 1K/6K/8K/10K/20K (Flex)

- XC2000/3000/4000/5200 - Spartan XCS

- Xilinx Vertex XCV - Cypress Delta39K

• Up to 15 MHz configuration rate

• Fast, ISP via 2-wire interface

• 3V (17LV) & 5V (17C) options RECONFIGURABLE!

RECONFIGURABLE!

Were #1 in Prog.

Were #1 in Prog.

Logic ISP memories

Logic ISP memories

Configurator

SRAM-BasedFPGA/FPSLIC- Atmel- Altera- Lucent- Xilinx


• ISP 5V or 3.3V• Fast programming up to 15MHz • Cascade

– Multiple devices can be cascaded.

• Reconfigurable FPGA Memory– EEPROM is priced competitively with OTP products

• Two Parts in One– AT17Cxxx can also emulate 24Cxxx parts

• In System (Re)ProgrammableEasy system hook-up for ISP operation– Can be soldered to PCB - no socket required

Key Features and Benefits


Two Parts in One

• Use ‘spare’ memory like a 24Cxxx device.– Save on cost/Board space/Power consumption.– Use ISP interface mux to enable 2-wire

SEEPROM capability.

0000

1AD7

FPGA Configuration memory requirements are stored from zero page to 1AD7 Hex.This memory space is accessed in AT17Cxxx mode by the FPGA (SerEn =1)

1B00

1FFF

AT17 Device Address space.

‘Unused’ memory at the end of the AT17Cxxx can be accessed in 24Cxxx mode (SerEn=0).Information such as last number redial/PCI I.D.Plug and Play/IP address etc. can easily be stored or retrieved using a micro-controller.

17CXXX

24CXXX


Configurators ISP OSC WP Ready Cascade PackageLow Density(Old) Mux N RESET/OE N Y(Except 65) 8 DIP, 8/20

SOIC, 20 PLCC

Low Density(New) Simple N RESET/OE N Y, using A2 8 DIP, 8/20 SOIC, 20 PLCC

High Density(Old 512/010) Simple Y WP1/WP2 Y Y, using A2 20 PLCC, 8 DIP

High Density(Old 020) Simple Y N Y N 20 PLCCHigh Density(New 002) Simple Y WP1/WP2 Y Y, using A2 20 PLCC4M Simple Y Y Y Y 44 TQFP/PLCC8M/16M(AT17C/F)) Simple Y Y Y Y 44 TQFP/PLCC2M/4M/8M(AT18F) JTAG ISP Y Y Y Y 44 TQFP/PLCC

New Parts / Old Parts Design Differences

OSC : Internal Oscillator function available

WP : Write Protect, this feature allows portions of the memory to be blocked during Write instructions.


Configurator AvailabilityAtmel & Xilinx Versions

Device 8-DIP 8-SOIC 20-PLCC 20-SOIC 44 TQFP JTAG

17C6517C12817C256

NowNowNow

NowNowNow

NowNowNow

NowNowNow

------

------

17C51217C01017C020

Q3/01Q3/01

--

------

NowNowNow

------

------

------

17C00217C04017F08017F016

--------

--------

Q2/01------

--------

--Q3/01H2/01H2/01

--------

18F02018F04018F080

------

------

H2/01H2/01H2/01

------

--H2/01H2/01

YesYesYes

• AT17C/F series = 2-wire serial ISP• AT18F series = JTAG ISP


Configurator AvailabilityAltera Versions

Device 8-DIP 8-SOIC 20-PLCC 20-SOIC 32 TQFP JTAG

17C65A17C128A17C256A

------

------

NowNowNow

------

------

------

17C512A17C010A17C020A

Q2/01Q2/01

--

------

NowNowNow

------

------

------

17C002A17C040A17F080A17F016A

--------

--------

Q2/01------

--------

Q3/01Q4/01H2/01H2/01

--------

18F020A18F040A18F080A

------

------

------

------

H2/01H2/01H2/01

YesYesYes

• AT17C/F series = 2-wire serial ISP• AT18F series = JTAG ISP


GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

GNDVCC

GND

VCC

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CE CEO (A2)RESET/OE

M2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

RESET/OECE

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CERESET/OEM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

Simple ISP circuit

Use Mux for ISP circuit

Figure 1: In-System Programming of AT17C/LV65/128/256 (old) EEPROM in AT40K FPGA Application

Figure 2: In-System Programming of AT17C/LV65/128/256 (new) EEPROM in AT40K FPGA Application

ISP Programming


‘A’ Vs ‘Non A’ EEPROM

High Density EEPROM

AT17(A) Internal oscillator is enabled by

default• 'A' part is recommended for

Altera users• Pin out is different• Oscillator must be enabled for

Altera’s Flex 1K,10K & 6K family, disabled for Altera’s Flex 8K family

AT17(Non A)Internal oscillator is disabled by

default

• Non-A part is recommended for Atmel, Xilinx, and Lucent users


Programming Options

• ATDH2200 board for ISP and stand-alone device programming

• ATDH2225 for ISP - Recommended for Atmel custom board layout- Allows cascading controlled by software

• Broad third party programmer support– Faster to program than OTP parts

• Source Code is available - For development of Microcontrolled programming


ATDH2200E

• PC Programmer kit for ALL AT17 Series EEPROMs– Standalone programming of Configuration EEPROM, OR– Interface to target board for In-System Programming– Supports .pof, .rbf, .hex, .mcs and .bst file formats

• Takes files straight from Atmel/Xilinx/Altera/Lucent software

– 5V and 3.3V operation (from supply or target board)– Choice of 20pin PLCC or SOIC socket adapter

• ATDH2221 for all 20 pin SOIC• ATDH2222 for all 20 pin PLCC (incl. Altera, 2M)

• ATDH2223 for all 8 pin SOIC

• ATDH2224 for 44 pin TQFP

• ATDH2226 for 32 pin TQFP

• ATDH2227 for 44 pin PLCC– Directly supported by Atmel’s IDS FPGA software CPS (Configurator Programming System) software– Quick start user’s guide

NEW!NEW!

NEW!


ATDH2200Stand-alone Device Programming

ParallelPort

PC

ATDH2200

AT17CXXX Configurator

Socket

Parallel Cable

DB-25M

DB-25F


ParallelPort

ATDH2200In-System Programming

PC

ATDH2200

Target System

In-System Programming

Connector Header



Connector Header

FPGA FPGA

Parallel Cable

10-pin RibbonCable

DB-25M

DB-25F


ParallelPort

ATDH2225In-System Programming Cable

PC

ATDH2225

Target System


Connector Header


FPGA FPGA

DB-25M

NEW!

Programming Dongel


CPS Configurator Programming Software

• AT17 Configurator Programming System s/w

• Clear and compact GUI

• Windows 95/98/NT/2000 support

• 2Meg device support

• Partitions Altera bitstream files for use in third party programmers

• Reset polarity verification (on ATDH2200E only)

• Download data rate calibrated to PC processor

• Save and restore settings between sessions

• Enable/Disable internal clock for Altera ‘A’ parts

• Online help and link to WWW-based FAQ


CF.EXE(Windows 3.1/95/98 DOS software)

• Program from Atmel .bst file format [AT40K]CF /P /I input_file.bst /S code /Z level [/G] [/D LPT1]

• Program from Altera .pof or .hex file formatsCF /A /I input_file.pof /S code /Z level [/D LPT1]CF /A /I input_file.hex /S code /Z level [/D LPT1]

• Program from Xilinx .mcs file formatCF /E /I input_file.mcs /S code /Z level [/D LPT1]

• Density ‘codes’ are 65, 128, 256, 512, 010

– 2Meg part supported in CPS (GUI version of CF) only• Reset ‘levels’ are L (active low) or H (active high)• Altera file conversion for 3rd party programmers

CF /B /I input_file.pof /O output_file.bst /F HEXCF /B /I input_file.hex /O output_file.bst /F HEX

• Source code for CF available on request (cf.c)


AT40K Configuration Statistics

Device Configuration Bits* Configurator

AT40K05 63K AT17C/LV65AT40K10 135K AT17C/LV256AT40K20 236K AT17C/LV256AT40K40 521K AT17C/LV512AT40K80 916K AT17C/LV010AT40K125 1419K AT17C/LV020

Configurator

AT40K

* = Can be reduced by using bit-stream compression option


FPSLIC Configuration Statistics

Device Configuration Bits*Configurator*

AT94K10 423K AT17LV512AT94K20 524K AT17LV010AT94K40 809K AT17LV010

Configurator

AT94K

* = Can be reduced by using bit-stream compression option


Drop-In of AT17C65/128/256AT40K FPGA Application

GND

RESET

VCC

Note: 1. 4.7k ohm resistors used unless otherwise specified.2. Reset polarity must be set to active low.

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CERESET/OEM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

VCC


ISP of AT17C/LV65/128/256(Old Vs New) EEPROM

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

GNDVCC

GND

VCC

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CE CEO (A2)RESET/OE

M2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

RESET/OECE

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CERESET/OEM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

New (No Multiplexor)Old (using Multiplexor)


Drop-In of AT17C512/010/002AT40K FPGA Application

GND

RESET

VCC

Note: 1. 4.7k ohm resistors used unless otherwise specified.2. Use of the READY pin is optional.3. Reset polarity must be set to active low.

DATACLK

SER_EN

AT17C512/010/020AT17LV512/010/020

CERESET/OE

READYM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT


In-System Programming of the AT17C/LV512/010/002AT40K FPGA Application

GND

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. Use of the READY pin function is optional.3. Reset polarity must to be set active low.

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C512/010/002AT17LV512/010/002

CERESET/OE

READYM2

RESETD<0>CCLKCON

AT40K

M1M0

INIT

RESET


ISP of New Low Density(AT17C/LV65/128/256) VS

High Density(AT17C/LV512/010/002)

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CERESET/OEM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C512/010/002AT17LV512/010/002

CERESET/OEM2

RESET D<0>CCLKCON

AT40K

M1M0

INIT

RESET

Ready


Drop-In of AT17C65/128/256AT60xx FPGA Application

M1M0

M2 D0CCLKCON

AT60xx

CS

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CERESET/OE

VCC

GND

REBOOT

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. Reset polarity must be set active high.


DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

GNDVCC

GND

VCC

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. Reset polarity must be set active high.

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CE CEO (A2)RESET/OE

RESET/OECE

M1M0

M2 D0CCLKCON

AT60xx

CS

VCC

GND

REBOOT

In-System Programming of the AT17C65/128/256 (Old)RESET/OE Programming Arrangement

AT60xx FPGA Application

Old Version


GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CEM1M0

M2 D0CCLKCON

AT60xx

CS

REBOOT

RESET/OE

In-System Programming of the AT17C65/128/256 (New)RESET/OE Programming Arrangement

AT60xx FPGA Application

Note : Reset Polarity of the EEPROM is programmed HIGH for AT6K devices

New Version


Drop-In Replacement of XC17/AT17 PROMsXilinx/Lucent FPGA Application

GND

PROGRAM

M1M2

M0

DINCCLK

INITDONE

XC4000/OR3

DATACLK

AT17CxxxAT17LVxxx

CERESET/OE

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. An optional internal pullup resistor is enabled here for DONE.3. Reset polarity must be set active low.4. Use of the READY pin is optional (available on AT17C512/010/020 only).

PROGRAM

READY

VCC

VCC

SER_EN


In-System Programming of the AT17C65/128/256RESET/OE Programming Arrangement

Xilinx/Lucent FPGA Application

GND

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

GNDVCC

GND

VCC

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

VCC

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. An optional internal pullup resistor is enabled here for DONE.3. Reset polarity must be set active low.

PROGRAM

DATACLK

SER_EN

AT17C65/128/256AT17LV65/128/256

CE CEO (A2)

PROGRAM

M1M2

M0

DINCCLK

INITDONE

XC4000/OR3

RESET/OE

SER_ENRESET/OECE


In-System Programming of the AT17C512/010/002


GND

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. An optional internal pullup resistor is enabled here for DONE.3. Use of the READY pin function is optional.4. Reset polarity must be set active low.5. This schematic cannot be used with the AT17C020 device.

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

PROGRAM

M1M2

M0

DINCCLK

INITDONE

XC4000/OR3

DATACLK

SER_EN

AT17C512/010/002AT17LV512/010/002

CERESET/OE

READY

PROGRAM


In-System Programming of the AT17C512/010/002Cascaded Arrangement


GND

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. An optional internal pullup resistor is enabled here for DONE.3. Use of the READY pin function is optional.4. Reset polarity must be set active low.5. This schematic cannot be used with the AT17C020 device.

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

PROGRAM

M1M2

M0

DINCCLK

INITDONE

XC4000/OR3

DATACLK

SER_EN

AT17C512/010/002AT17LV512/010/002

Device 1

CERESET/OE

READY

PROGRAM

DATACLK

SER_EN

AT17C512/010/002AT17LV512/010/002

Device 2

CERESET/OE

READY

VCC

CEO (A2)

CEO (A2)


In-System Programming of the AT17C/LV020 Xilinx/Lucent FPGA Application

GND

VCC

Notes: 1. 4.7k ohm resistors used unless otherwise specified.2. An optional internal pullup resistor is enabled here for DONE.3. Use of the READY pin function is optional.4. Reset polarity must be set active low.5. This schematic can be used for AT17C512 and AT17C010 devices.6. A2 bit (device address bit) must be specified high in the software.

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

PROGRAM

M1M2

M0

DINCCLK

INITDONE

XC4000/OR3

DATACLK

SER_EN

AT17C020AT17LV020

CERESET/OE

READY

PROGRAM

VCC

/CEO (A2)


Drop-In Replacement of the EPC1064/EPC1213External Oscillator Arrangement

Altera FPGA Application

nCONFIG

MSELnCE

DATA0DCLK

nSTATUSCONF_DONE

EPF6K

GND

VCC VCC

Note: 1. 1.0k ohm resistors and 0.1uF capacitor are used unless otherwise specified.2. Reset polarity must be set active low.3. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)

DATADCLK

AT17C65(A)/128(A)/256(A)AT17LV65(A)/128(A)/256(A)

nCSOE

EXT_CLK

GND

VCC VCC

SER_EN


In-System Programming of Old Low Density(AT17C/LV65A/128A/256A) VS

New Low Density(AT17C/LV65A/128A/256A) using Altera FPGA

New (No Multiplexor)Old (using Multiplexor)

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

GND

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_ENOEnCS

GNDVCC

GND

VCC

DATADCLK

AT17C65(A)/128(A)/256(A)AT17LV65(A)/128(A)/256(A)

nCSOE

nCASC (A2)

SER_EN

nCONFIG

MSELnCE

DATA0DCLK

nSTATUSCONF_DONE

EPF6K

VCC VCC

VCC

EXT_CLK

GND

VCC

DATADCLK

AT17C65/128/256AAT17LV65/128/256A

Device 1

nCSOE

SER_EN

GND

VCC VCC

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

nCONFIG

MSELnCE

DATA0DCLK

nSTATUSCONF_DONE

EPF6K

EXT_CLK

GND


Drop-In Replacement of the EPC1064/EPC1213Altera FPGA Application

nCONFIG

MSEL0nS/P

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF8K

GND

VCC VCC VCC

Note: 1. 1.0k ohm resistors used unless otherwise specified.2. Reset polarity must be set active low.

DATADCLK

AT17C65(A)/128(A)/256(A)AT17LV65(A)/128(A)/256(A)

nCSOE

VCC

VCC

SER_EN


Drop-In Replacement of the EPC1441/EPC1/EPC2Internal Oscillator Arrangement


nCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

GND

VCC VCC

Note: 1. 1.0k ohm resistors and 0.1uF capacitor are used unless otherwise specified.2. Applicable to EPF6K.3. Reset polarity must be set active low.4. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)5. Use of the READY pin is optional.

DATADCLK

AT17C512A/010A/020AAT17LV512A/010A/020A

nCSOE

READY

SER_EN

GND

VCC

VCC


Drop-In Replacement of the EPC1441/EPC1/EPC2Internal Oscillator and Cascaded Arrangemen


DATADCLK

AT17C512A/010A/020AAT17LV512A/010A/020A

Device 1

nCSOE

nCASC

READY

SER_EN

GND

VCC VCC

Notes: 1. 1.0k ohm resistors and 0.1uF capacitor are used unless otherwise specified.2. Reset polarity must be set active low.3. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)4. An additional pullup resistor on the nCS of Device 2 is only required if this device exhibits a sensitivity to the power-up ramp of VCC (i.e. it incorrectly powers up as a bus master thereby driving DCLK as well).5. Use of the READY pin is optional.

DATADCLK

AT17C512A/010A/020AAT17LV512A/010A/020A

Device 2

nCSOE

SER_ENnCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

GND

VCC

VCCVCC


In-System Programming of the AT17C65(A)/128(A)/256(A)RESET/OE Programming Arrangement


GND

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_ENOEnCS

GNDVCC

GND

VCC

74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

DATADCLK

AT17C65(A)/128(A)/256(A)AT17LV65(A)/128(A)/256(A)

nCSOE

nCASC (A2)

SER_EN

nCONFIG

MSEL0nS/P

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF8K

VCC VCC

VCC

Notes: 1. 1.0k ohm resistors used unless otherwise specified.2. Reset polarity must be set active low.

VCC


In-System Programming of the AT17C65A/128A/256A(older version)RESET/OE Programming with External Oscillator Arrangement


74HC(T)157 SE

1A 1B 2A 2B 3A 3B 4A 4B

1Y 2Y 3Y 4Y

2 3 5 6 11 10 14 13

15 1

4 7 9 12

GND

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_ENOEnCS

GNDVCC

GND

VCC

DATADCLK

AT17C65(A)/128(A)/256(A)AT17LV65(A)/128(A)/256(A)

nCSOE

nCASC (A2)

SER_EN

nCONFIG

MSELnCE

DATA0DCLK

nSTATUSCONF_DONE

EPF6K

VCC VCC

VCC

Notes: 1. 1.0k ohm resistors used unless otherwise specified.2. Applicable to EPF10K.3. Reset polarity must be set active low.4. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)

EXT_CLK

GND

VCC


In-System Programming of the AT17C512A/010A/002AAltera FPGA Application

DATADCLK

AT17C512A/010/002AAT17LV512A/010/002A

Device 1

nCSOE

READYSER_EN

GND

VCC VCC

VCC

Notes: 1. 1.0k ohm resistors used unless otherwise specified.2. The internal oscillator of the AT17A Configurator is disabled.3. Reset polarity must be set active low.4. Use of the READY pin is optional.5. This schematic cannot be used with the AT17C020A device.

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

nCONFIG

MSEL0nS/P

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF8K

VCC


In-System Programming of the AT17C512A/010/002AInternal Oscillator Arrangement


DATADCLK

AT17C512A/010A/002AAT17LV512A/010A/002A

Device 1

nCSOE

READYSER_EN

GND

VCC VCC

VCC

Note: 1. 1.0k ohm resistors and 0.1uF capacitor are used unless otherwise specified.2. Applicable to EPF6K.3. Reset polarity must be set active low.4. Use of the READY pin is optional.5. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)6. This schematic cannot be used with the AT17C020A device.

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

nCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

GND


In-System Programming of the AT17C512A/010A/002A

DATADCLK

AT17C512A/010A/002AAT17LV512A/010A/002A

Device 1

nCSOE

READYSER_EN

nCASC (A2)

GND

VCC VCC

VCC

Notes: 1. 1.0k ohm resistors and 0.1 uF capacitor are used unless otherwise specified.2. Use of the READY pin is optional.3. Reset polarity must be set active low.4. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)5. This schematic cannot be used with the AT17C020A device.

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

DATADCLK

AT17C512A/010A/002AAT17LV512A/010A/002A

Device 2

nCSOE

SER_EN

VCC

nCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

GND

Internal Oscillator and Cascaded ArrangementAltera FPGA Application


In-System Programming of the AT17C512A/010A/002A

DATADCLK

AT17C512A/010A/002AAT17LV512A/010A/002A

Device 1

nCSOE

READYSER_EN

GND

VCC VCC

VCC

Note: 1. 1.0k ohm resistors and 0.1uF are used unless otherwise specified.2. Applicable to EPF6K.3. The internal oscillator of the AT17A Configurator is disabled.4. Reset polarity must be set active low.5. Use of the READY pin is optional.6. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)7. This schematic cannot be used with the AT17C020A device.

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

nCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

EXT_CLK

GND

External Oscillator ArrangementAltera FPGA Application


In-System Programming of the AT17C/LV020A

DATADCLK

AT17C020AAT17LV020A

Device 1

nCSOE

READYSER_EN

GND

VCC VCC

VCC

Note: 1. 1.0k ohm resistors and 0.1uF capacitor are used unless otherwise specified.2. Applicable to EPF6K.3. Reset polarity must be set active low.4. Use of the READY pin is optional.5. RC filter recommended for input to nCONFIG to delay configuration until Vcc is stable. (nCONFIG can instead be connected to an active low system reset signal.)6. This schematic can be used with AT17C512A and AT17C010A devices.

DATADCLK

2

3 4

1

6

7

5

8

9 10

GND

SER_EN

VCC VCC

VCC

nCONFIG

MSEL0nCE

MSEL1

DATA0DCLK

nSTATUSCONF_DONE

EPF10K

GND

VCC

/CEO (A2)

Internal Oscillator ArrangementAltera FPGA Application

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