A. Aloisio

ATLASLevel–1 Muon Barrel

RODbusPreliminary Design Review

Mar.12, 2002Alberto AloisioINFN - Sezione di Napoli, Italy

e-mail: aloisio@na.infn.it

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Overview

� Muon Level-1 Trigger and Data path� ROD crate architecture� RODbus features� Measure, models & simulations� Test results� Conclusions

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From PAD to ROD/SL

ROD

TriggerSL

MTCPI

RXData

PAD Logic

� Optical out from PAD to:– SL– ROD

� 12 bit @ 40MHz on the trigger path; synch, fixedand low latency link required to guarantee timing.

� 16 bit + strobe on the data path.

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ROD Crate layout

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RODbus requirements

4848+48

48+48 4848

48

ROD RX

RODbus (SL)

SL

MTCPI

SL

MTCPI RODbus (RX)

RX12 16

� SL to ROD– 48 bit@40MHz– synchronous with low

latency

� RX to ROD– (16+8 bits x 2 = 48 bits)

� ROD to RX/SL(not shown)– Low skew, low jitter

clock distribution– control signals

(RST*, LVL1A, ...)

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Strategy

� Common platform for both SLs and RXs to RODbackbones:– SL asks for a synchronous design.

– Low skew, low jitter signals need a differentialsignaling scheme.

– Doubling data lines saturates the pin availability (andboard space) if a SerDes approach is not used.

– Low voltage, low power (and high performances)suggest LVDS.

– System level “non-timing” signals (as RST*) can runTTL.

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Choosing the chip-set

� DS90CR483/4 chip-set, a 48:8 bit + clock LVDSpseudo SerDes

� Deskew and Preemphasis for improved performances

� Data transfer rate @ 7x master clock frequency

backplane

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Partitioning the problem

� To optimize board layout and backplaneperformances, we decided to assign the SLsto ROD and the RXs to ROD channels totwo “add on” backplanes.

� In this review, we present the prototype ofthe RXs to ROD backplane, assigned to J2

� The SLs to ROD backplane will be doneusing the same technology, mapped to J0

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RODbus: RXs to ROD

� 3 slot backplane to link2 RXs to one ROD

� 10 layer stack-up

� Diff. microstrip forLVDS pairs and singleended for TTL lines onseparate planes

� Plug-in to the VME64rear side. TTL linesterminated as VME

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ROD slot pinout

� ROD distributes clock and 8 system control signals

� Receives 48bits@40MHz from each adjacent RX

TTL lines

RXB

SerDes

RXA

SerDes

clock

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Physical layout

� Diff. LVDS pairsrouted as edgecoupled microstrips

� All pairs have thesame length (10 miltolerance).

� Noisy TTL lines arerouted on a separateplane.

RXB clock

LVDS diff.

RXA clock

LVDS diff.

SerDes clock

LVDS diff.

SerDes clock

LVDS diff.

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TDR interface

� Two test fixtures havebeen designed to interfacethe RODbus to TDR

� Diff. Impedance profilecan be measured

� Impact of connectors,vias, stubs and holes(present in the realenvironment) can beevaluated

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TDR profile

� TDR step probesbackplane line andconnectors

� PCB stack-up is tested

� line length andimpedance are measured

� lumped L/C (connectors,vias, solder pads) arevisible

50 Ohm

coax cable

test

fixture

backplane

connectors

L=575ps

Open load

reflection

50 Ohm

LVDS line

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Testing the SerDes: ROD slot

� ROD emulation:– Distributes Clock to RXs (from ext. or local source)

– Receives serial streams from RXA and RXB

Interface to

ParBERT

Ext. Clock

Deserializer

(RXB)

Clock

LVDS driver

Deserializer

(RXA)Local Clock

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Testing the SerDes: RX slot

� RX emulation:– Receives Clock from ROD

– Transmits serial streams to ROD

Interface to

ParBERT

Clock

LVDS receiver

Serializer

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TDR system test

RODbus

VME

J2/P2

RXB

Emulator

ROD

EmulatorTDR step

launch point

� The entire RX-to-ROD connection is analyzed

� Unpopulated RX and ROD emulators are used toevaluate the signal integrity using TDR

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Impedance profile

� The TDR reflectedstep shows thediscontinuities (vias,holes, connectors, ...)

� The impedanceprofile is deriveddeconvolving themultiple reflections

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Modelling the system

� A PSpice model hasbeen developed, basedon the impedanceprofile

� The model is based onideal (lossless) linesegments

� Model validation is performed by simulatingthe TDR reflected step. Results are in excellentagreement with experimental data

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IBIS models

Typical output stage

Typical input stage

� IBIS is an ANSI standard tomodel I/O buffers mainly forsignal integrity issues

� Different from SPICE, IBISgives only a behavioraldescription - disclosing noproprietary circuit information

� The I/O buffer is characterizedby means of a standard templateof VI curves and stray L,C and R

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DS90CR483 LVDS Output

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System simulation

TX LVDS

PSpice models derived

from IBIS

RODbus

PSpice model

RX LVDS

PSpice models derived

from IBIS

� PSpice system simulation includes backplanes,connectors, stubs, SerDes TX and RX

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Simulation caveat

� Interconnection Model is based on idealtransmission lines

� Crosstalk, ground bounce, probe loading arenot modeled

� TDR-derived models are less accurate thelonger the step travels

� SerDes IBIS model only specs typ. values,pre-emphasis and deskew not modeled

� Standing wave needs long simulation runs(>15h to simulate 2us on a Pentium II – 350)

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SerDes LVDS clock - TX side

LVDS SerDes

Clock @ TX

simulation

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SerDes LVDS clock – RX side

LVDS SerDes

Clock @ RX

simulation

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Test results (preliminary)

� Tests with 2^15 PRBS show no errorsin the SerDes operations up to 60 MHz(420 Mbit/s). Fine tuning should allowreaching 80 MHz (560 Mbit/s).

� Latency is 5 clock cycles (125ns @ 40MHz), dominated by the SerDes specs.RODbus Tpd (570 ps) is negligible.

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More tests to be done

� RODbus performances in a real VME(noisy) environment

� EMI

� BER vs. clock frequency and differentpatterns

� 48-bit 2^16 Pseudo Random WordSequence (PRWS) test requires acustom platform (generator, analyzer,adapters, …) to be developed

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Conclusions (1/2)

� RODbus is the proposed backbone for all theROD crate interconnection needs

� It specifies the physical layer (backplane, lineimpedance, levels) and the logical layers(SerDes specs)

� Data transfer rate is 7x the master clockfrequency (280 Mbit/s @ 40MHz) requiringcareful PCB layout for backplane and users’boards. Emulators have been designed proof ofconcept, tests and PCB layout reference

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Conclusions (2/2)

� RODbus has been in-deep characterized byusing TDR techniques. SPICE models have beenderived and validated. SerDes SPICE modelshave been crafted starting from IBIS files.

� The entire system has been simulated withPSpice and results show good agreement withexperimental data.

� Analog simulations has been successfully usedto evaluate the system performances and signalintegrity issues.