p 　 1

ATM-Board Specification(Daughter 　 board 　 I/F)

2006.9.26

IWATSU TEST INSTRUMENTS CORP.

Koji Ishikawa

p 　 2

Daughter board dimension

• Outline size• 85mm(H) × 120mm(W)

• Thickness• 1.6mm max• It is recommended to be less than 1.6mm for durability of stacking.

p 　 3

Daughter board dimension

Daughter　Board(Bottom　view)

120.0mm85.0mm

J 1J 2

Daughter　Board

1.6mm J 1J 2

ATM　BoardP2 P1

11

Daughter　BoardBottom　side

Daughter　BoardTop(parts)　side

ATM　BoardBottom　side

ATM　BoardTop(parts)　side

110.0mm

φ 3.5mm

5.0mm

37.5mm

75.0mm

37.5mm

105.0mm

p 　 4

Screw mounting

• Mounting hole for metal spacer• There are 4 mounting hole to avoid coming out ATM board.• M3 screw and spacer are used to attach the ATM and DB.• All of mounting hole on both ATM and DB should have φ3.5mm in diameter.• It might be better that the mounting holes are isolated from beside ground

plane. (see figure plz.)• We can provide these screw and spacer attaching with ATM board.

Therefore Daughter board can be mounted on ATM by them.

p 　 5

Connector and Spacer for mounting

• Connector location• There are two connectors on both ATM and DB.• P1 and P2 connector are located on the ATM board.• J1 and J2 connector are located on the Daughter board.

• J2 and J3 proposed by BU had unified into one J2 connector, and J2 and J1 connectors are located with the same way to ensure matching P1/2 on ATM and J1/2 on DB.

• Stacking connectors• The daughter board is mounted by facing downward to the ATM board.• J1 connector is stacked for P1 on ATM, and J2 is stacked for P2.• FX6-80S-0.8SV connectors of HIROSE are used for P1 and P2 on ATM.• FX6-80P-0.8SV2 connectors of HIROSE are used for J1 and J2 on DB.• The stack height between parts face of DB and that of ATM should be less

than 7mm.• All of parts on the daughter board must be avoid to contact with surface of

the ATM board.• Except for P1,P2 and four spacers ,there will be no parts on the mounting

area (120mm x 85mm) of ATM board.

p 　 6

Stacking formation

• Stacking formation view

Daughter　Board(Bottom　view)

120.0mm

85.0mm NEW　ATM-　Board

(top　view)

Front　Panel　side

Back-plane　side

J 1J 2

Daughter　Board(Side　view)

1.6mm J 1J 2

ATM　Board(Side　view)

P2 P1

Screw　head　(Low　height　1mm)

Metal　Spacer　(7mm)

FX6-80S-0.8SV

FX6-80P-0.8SV2

Screw　head

M3　screw

M3　screw

p 　 7

P1,P2 connectors pinout

Daughter　board　mount　areaon　ATM　board

TOP　VIEW(PARTS　SIDE)

P2 P1

123456

757677787980

123456

757677787980

base　mark

ATM　front　panel　side

• P1,P2 on the ATM borad are located as the following figure.

p 　 8

Signal lines wiring

NEW　ATM-　Board(top　view)

Front　Panel　side

Back-plane　side

RJ -45ATM　Borad　Front　Panel

FPGA(SIC)

Daughter　Board(Bottom　view)

J 　1

FPGAEnhanced　TKO　I/F

CLOCK

J 　2

Tx+Tx-

Rx+Rx-

V1power

LED2 LED1

JTAGI/F

p 　 9

Power specification

• V1 power source• Supply voltage : 　 +15V• V1power is directly provided from TKO backplane.• Absolute maximum current is totally 15A in two crate. So it is required that

one daughter-board has low electricity consumption less than 0.5A.

p 　 10

Clock specification

• Frequency: 60MHz

→ 　 The FPGA(SIC) on ATM board supplies this clock by redirecting from Local clock on ATM board.

• Stability: less than 100ppm

• Jitter 100ps peak to peak (T.B.D)

→ Outcome is merely wired without PLL processing in FPGA.

→ If this would be processed with PLL, the value of jitter will be estimated less than 0.02UI.

• Signal standard: differential LVDS 2.5V

p 　 11

Clock distribution

• Clock distribution on the ATM board

FPGA(DSM　3)

QTC5

60MHz_CLK,　　SerialTrigger,　TDC_Reset

ATM　Borad　Front　PanelRJ -45CLK(LED)

CLK　detect

QTC6

LVCMOS_3.3VLVDS_2.5V

60MHz_CLK

　EventNumber[3:0]

RJ -45

TDC3

FPGA(DSM　1)

QTC1QTC2

TDC1

FPGA(DSM　4)

QTC7QTC8

TDC4

FPGA(DSM　2)

QTC3QTC4

TDC2

DHS

Local60MCLK

CLKSelect

for　debug　only

FPGA(SIC)

CLK　 Distributor　1:10Daughter　Board

J 1

p 　 12

Clock domain allocation

• Local clock should be available to operation whenever external system clock had come off illegally.

System_Clock　DomainLocal_Clock　Domain

60MHz_CLK,　　SerialTrigger,　TDC_Reset

ATM　Borad　Front　PanelRJ -45

LVCMOS_3.3VLVDS_2.5V

60MHz_CLK

　EventNumber[3:0]

RJ -45

Local60MCLK

CLKSelect

LOC_CLK

CLK　 Distributor　1:10

FPGA　(SIC)

clock　detect

SerialTrigger　I/ F

ManualTriggercontrol

TDCTriggergeneration

DualPortMemory

TriggerIDextract

DATAM rgeｅ

Event_numberI/ F

VETO　inputcontrol

Mark　Hitgeneration

Pedestalgeneration

CAL　selectCAL_Triggergeneration

CAL　startcontrol

ReadOutFIFO

Daurhter　I/ F

LED　control LED　control

StoreMemoryaccess

SYS_CLK

TKO　I/ F

p 　 13

Pinout information

• ATM board• RJ-45 connector

• Ethernet control signals are connected• Pinouts are conformed to the MDI interface standard.

• P1 connector• Enhanced interface signals are routed to this connector.

• P2 connector• Ethernet signals and LED control signals are routed to this connector.• V1 power line is routed to this connector(#45-51, #59-65).

• Daughter board• J1 connector

• Enhanced interface signals are routed to this connector.• J2 connector

• Ethernet signals and LED control signals are routed to this connector.• V1 power line is routed to this connector (#45-51, #59-65).

p 　 14

Pinout information

• P1 connector pinout information

Pin Signal I/ O Pin Signal I/ O Pin Signal I/ O Pin Signal I/ O1 GND - 2 Clock_T Out 41 GND - 42 *D(2) Bidir3 GND - 4 Clock_C Out 43 GND - 44 *D(3) Bidir5 GND - 6 GND - 45 GND - 46 *D(4) Bidir7 GND - 8 *SA(0) In 47 GND - 48 *D(5) Bidir9 GND - 10 *SA(1) In 49 GND - 50 *D(6) Bidir11 GND - 12 *SA(2) In 51 GND - 52 *D(7) Bidir13 GND - 14 *SA(3) In 53 GND - 54 *D(8) Bidir15 GND - 16 *SA(4) In 55 GND - 56 *D(9) Bidir17 GND - 18 *SA(5) In 57 GND - 58 *D(10) Bidir19 GND - 20 *SA(6) In 59 GND - 60 *D(11) Bidir21 GND - 22 *SA(7) In 61 GND - 62 *D(12) Bidir23 GND - 24 *SA(8) In 63 GND - 64 *D(13) Bidir25 GND - 26 *SA(9) In 65 GND - 66 *D(14) Bidir27 GND - 28 *SA(10) In 67 GND - 68 *D(15) Bidir29 GND - 30 *F(0) In 69 GND - 70 DOIT* In31 GND - 32 *F(1) In 71 GND - 72 YSSIR* Out33 GND - 34 *F(2) In 73 GND - 74 Q* Out35 GND - 36 *F(3) In 75 GND - 76 RSV(0) In37 GND - 38 *D(0) Bidir 77 GND - 78 RSV(1) In39 GND - 40 *D(1) Bidir 79 GND - 80 G_TRG Out

note1　　Except　for　the　clock　signal,　all　interface　signals　use　2.5V　CMOS　logic　levels.　　　note2　Clock　signal　use　2.5V　LVDS　using　differential　signaling.　

P1　Pinout　(　#1to　#40) P1　Pinout　(　#41to　#80)

p 　 15

Pinout information　

• P2 connector pinout information

Pin Signal I/ O Pin Signal I/ O Pin Signal I/ O Pin Signal I/ O1 NC - 2 NC - 41 GND - 42 GND -3 Rx+ Out 4 NC - 43 NC - 44 GND -5 NC - 6 Tx+ In 45 V1 - 46 GND -7 Rx- Out 8 NC - 47 V1 - 48 GND -9 NC - 10 Tx- In 49 V1 - 50 GND -11 NC - 12 NC - 51 V1 - 52 GND -13 NC - 14 NC - 53 NC - 54 GND -15 NC - 16 NC - 55 GND - 56 GND -17 NC - 18 LED1 In 57 NC - 58 GND -19 NC - 20 LED2 In 59 V1 - 60 GND -21 Vccj - 22 GND - 61 V1 - 62 GND -23 TDO Out 24 GND - 63 V1 - 64 GND -25 TDI In 26 GND - 65 V1 - 66 GND -27 NC - 28 GND - 67 NC - 68 GND -29 NC - 30 GND - 69 GND - 70 GND -31 TMS In 32 GND - 71 NC - 72 GND -33 GND - 34 GND - 73 NC - 74 GND -35 TCK In 36 GND - 75 NC - 76 GND -37 NC - 38 GND - 77 NC - 78 GND -39 NC - 40 GND - 79 GND - 80 GND -

note1　　Vccj　needs　to　be　provided　3.3V　level.　　　note2　J TAG　signals　for　ATM-board　use　3.3V　CMOS　logic　levels.　

P2　Pinout　(　#1to　#40) P2　Pinout　(　#41to　#80)

p 　 16

Pinout information

• RJ-45 connector pinout information

note1　　All　of　pins　are　allocated　by　the　MDI　specification.　　　

RJ - 45　Pinout　Pin Signal I/ O12345678

Tx+Tx-Rx+NCNCRx-NCNC

OutOutIn--In--

p 　 17

Ground allocation

• Stacking connector• Ground pattern area must be fortified with outside allocated area of connectors,J1and J2.• Ethernet signal lines that routed form P2 to RJ-45 are isolated from the signal ground by

using such as gapped area. This way also will be need for the daughter board.

• Metal spacer• There are some small through via hole around the Φ3.5mm hole for screw mounting.• This way is effective for stable contact to the signal ground.

Stacking　areafor

Daughter-Board

Ø0.5mmThrough Hole

Ø3.5mmNon Through Hole

Non Resist area

P1

GND　allocated　area

RJ -45 GND　gapped　area

P2

p 　 18

TKO interface

• Enhanced 　 TKO interface• Data handshaking of TKO interface is communicated through P1and J 1connectors.

• All of signals use 2.5V LVCMOS logic levels.

• Almost of the all FPGA devices have the slow slewrate function. This function will improve the quality of signal transmission.

• There will be series damping resistors for the same reason above.

Min Max Min MaxT0- T1 50 25T1- T3 50 33 50T3- T4 50 25T4- T6 50 25Total 200 125

Note1　　　In　the　Enhanced　mode,　all　of　signals　use　2.5V　CMOS　logic　levels.　

ATM/Daughter　Board　Interface　timing　CharacteristicsStandard　[ns] Enhanced　[ns]

p 　 19

0

GA[3:0]*1 IN G-Address[0] G-Address[0]

SA[10:0]*2 IN SubAddress[0] SubAddress[2]

F[3:0]*3 IN FunctionAddress[0] FunctionAddress[2]

DOIT*4 IN

YSSIR*5 OUT

D[15:0]*6 I/O Data[0]

Q*7 OUT

DAT_RD8 OUT

SA[10:0],　F[3:0]9 IN LatchedAddress[0]

0 25ns～

0 25ns～

0 25ns～

33.3　 　50ns～

0 10ns～

0 25ns～ 0 25ns～

125ns～

T0 T1 T2 T3 T4T5 T6NAME I/O Log

TKO interface

• Enhanced-TKO Interface 　 READ cycle timing chart

Slave Master ATM Daughter board (computer)

‘IN’ are driven by the daughter card

p 　 20

TKO interface

• Enhanced-TKO Interface 　 WRITE cycle timing chart

0

GA[3:0]*1 IN G-Address[0] G-Address[0]

SA[10:0]*2 IN SubAddress[0] SubAddress[2]

F[3:0]*3 IN FunctionAddress[0] FunctionAddress[2]

DOIT*4 IN

YSSIR*5 OUT

D[15:0]*6 I/O Data[0]

Q*7 OUT

CMD_WR8 IN

SA[10:0],　F[3:0]9 IN LatchedAddress[0]

D[15:0]10 IN LatchedData[0]

0 25ns～

0 25ns～

0 25ns～

0 25ns～

0 25ns～

33.3 50.1ns～

0 25ns～

125ns～

T0 T1 T2 T3 T4 T5 T6NAME I/O Log

Master SlaveDaughter board (computer) ATM

‘IN’ are driven by the daughter card

p 　 21

Ethernet Interface

• Ethernet interface• Serial data is communicated by sending or receiving between P2 and J 2 connector.

• Serial data line(Tx+, Tx-, Rx+, Rx-) should be well isolated from the signal GND.

• Two LEDs are used to indicate for Network 　 status.

• There is no label on the LEDs.

• LED1 lights in green. LED2 lights in yellow. 　• On the ATM board, serial data lines are merely wired to RJ-45 connector placed at

front side panel.

p 　 22

JTAG interface specification

• JTAG interface specification• 4-wire interface

• TCK JTAG 　 test clock• TDI JTAG 　 test data input• TMS JTAG 　 test mode select• TDO JTAG test data output

• Vccj needs to be provided 3.3V level to conform with other JTAG devices.• TCK 　 clock frequency must be less than 25MHz.• JTAG interface is operated by IEEE1149.1. • JTAG interface can be used to configure FPGA and SPI flash memory that

redirected by master FPGA.

p 　 23

Global Trigger specification

• Global trigger interface specification• G_TRG signal is used for detection of global trigger.

• Logic level LVCMOS 2.5V• Function If global-trigger is detected by SIC, G-TRG line

goes to active high level for two clock cycles (33.3ns

).

Daughter-board can use this line to manage the timing for access data by counting G_TRG pulses.

p 　 24

TKO address map

• Summary of TKO address map

• The daughter board can read-out the hit-data accessing Function0 address.

• About details of the registers, it is not prepared to define

TKO　function　assignment

b3 b2 b1 b00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

Q Read/Write Functiondecimal

binary

0 0　to　2047 0/ 1 Read Read　out　cells　from　FIFO

F[3:0]SA[10:0]

Read　module　ID2 0　to　2047 0/ 1 Read Read　mode1 0　to　2047 0/ 1 Read

4 0　to　2047 0/ 1 Read Read　out　QTC　registers3 0　to　2047 Read

Read　out　TDC,DSM,SIC　registers6 0　to　2047 0/ 1 Read Read　out　Other　devices/ block,　BMC　registers5 0　to　2047 0/ 1 Read

8 0　to　2047 0/ 1 Write Write　data　into　FIFO7 0　to　2047 Read

10 0　to　2047 0/ 1 Write Write　mode9 0　to　2047 0/ 1 Write

Write　threshold12 0　to　2047 0/ 1 Write Write　data　to　QTC　registers11 0　to　2047 0/ 1 Write

Write　data　to　TDC,DSM,SIC　registers14 0　to　2047 0/ 1 Write Write　data　to　Other　devices/ block,　BMC　registers13 0　to　2047 0/ 1 Write

Initialize　ATM　board,　clear　FIFO15 0　to　2047 0/ 1 Write

p 　 25

Summary architecture of DATA Format

• Basic format ：• 6byte Encapsulation -> form as 1 Cell

• One cell consists of 6 bytes for each format.• Header - ID

• length ：　 4bit• The value of 4bit-ID identifies classification of the defined 4-cells.

Hit-DATA Spacer RAW-DATA Status-massage

p 　 26

DATA Format

• ReadOut cell’s common format

Common Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word

15 14 13 12

0 0 x x

0 1 x x

1 0 x x

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

Bit Function

Bit

HEADER (Ch#)

HEADER

RAW-DATA cell

Status-massage cell

not used

Hit-DATA cellChannel Number: 0～23 (00000B～10111B)

Spacer cell

p 　 27

DATA Format

• Hit-DATA cell• Function

• This cell contains the Hit-data which is captured in ATM board.

• Header-ID value

• Upper 4bit of channel number field is used to identify the cell.

• value = 0000(b) 　～　 1011(b) 　 （ applying for Signal-Ch0 ～　 Ch23 ）• 6 bytes encapsulation

• Length: 6 bytes

• Raw data from TDC is formed into 6 bytes.

• Channel number

• Length: 　 5bit （ Upper 4bits is used for Header-ID commonly)

• Event-number

• length ：　 12bit

• Local event number reading-out from TDC

p 　 28

DATA Format

• Hit-DATA cell• TDC count value

• length ：　 16bit, 0.52ns/LSB• Read-out count value from TDC• This value is allowed to count up to 65535, and it corresponds to 34.078us. • If there are multiple hits between one event , another Hit-data cell also include

this count value.• Range

• length ：　 2bit• Detect range is Small ,Medium or Large. Each range is encoded to 2bit value.• In the Narrow or Wide trigger case, optimum range detected by DSM is encoded

into cell.• In the Pedestal or Calibration case, all of the 3-ranges is encoded into cell.

• QTC gate count value• length ：　 11bit, 0.52ns/LSB• This value is allowed to count up to 2027, and it corresponds to 1064ns.• Difference count between T2 and T1. T1 is rising edge time count. T2 is falling

edge count.• Trigger ID

• length ：　 2bit• Used to detect Narrow/Wide/Pedestal/Calibration

p 　 29

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word E#

3rd_Word Range QTC　gate　countTDC

Bit

Ch#　(HEADER) Event　#

TDC　count

TRG

DATA Format

• Hit-DATA cell• Format change

• QTC gate count needs to be changed to extend the count range. • 10bits length of QTC gate_count -> 11bits length• 17bits length of TDC count -> 16bit• Almost of all the items have arranged for separating by boundary.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word TDC　count

Ch#　(HEADER) QTC　gate　count

Range TRG Event　#

Bit

Current format New format

p 　 30

DATA Format

• New Hit-DATA cell format

Hit-DATA　cell　Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word

TDC　countMSB:　3rd_Word　　Bit15LSB:　3rd_Word　Bit0

16bitsTDC　count　(T1　leading　edge):0 65535　(0000H FFFFH)～ ～

Event　#MSB:　1st_Word　　Bit11LSB:　2nd_Word　Bit0

12bitsTDC　Event　Number:

0 4095　(000H FFFH)～ ～

Ch　#MSB:　1st_Word　　Bit15LSB:　1st_Word　Bit11

5bitsChannel　Number:

0 23　(00000B 10111B)～ ～

Bit

Ch#　(HEADER)

TDC　count

Bit　Location Length Function

QTC　gate　count

Range TRG Event　#

QTC　gate　countMSB:　1st_Word　　Bit10LSB:　1st_Word　Bit0

11bitsQTC　gate　count　value:

0 2047　(000H 7FFH)→0 1064ns,　　0.52ns/ bit～ ～ ～

TRGMSB:　2nd_Word　　Bit13LSB:　2nd_Word　Bit12

2bitsTrigger　ID:

00B　=　Narrow,　01B　=　Wide,10B　=　Pedestal,　11B　=　Calibration

RangeMSB:　2nd_Word　　Bit15LSB:　2nd_Word　Bit14

2bitsRange　code:

00B　=　small,　01B　=　medium,　10B　=　large

p 　 31

DATA Format

• Spacer cell• Function

• This cell is inserted every 64Global event number. It contains global event number and check data.

• Header-ID value

• length 　： 4bit

• value = 1100(b)

• 6 bytes encapsulation

• Length: 6 bytes

• Global event number

• length ：　 28bit

• This number is distributed from Mclock-module.

• Original global event number is 32bits-length. DSM reject lower 4bits from original 32bits number. So 28bits number is stored in the cell.

• Check data(16bit Sum)

• length ：　 16bit

• This value is added by every 16bit between all of the 64 event period.

• The target cells for the Sum-calculation are Hit-DATA cells.

p 　 32

DATA Format

• Spacer cell format

Spacer　cell　Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word

MSB:　1st_Word　　Bit15LSB:　1st_Word　Bit12

4bitsHEADER　code:

1100B　(code　of　Spacer　cell)

Bit　Location Length Function

Bit

HEADER　 Grobal　Event　Number　(bit31　- 　20)

Grobal　Event　Number　(bit19　- 　4)

16bit　Check- data

16bit　Check- dataMSB:　3rd_Word　　Bit15LSB:　3rd_Word　Bit0

16bits16bit　Check- data:

0 65535　(0000H FFFFH)～ ～

Grobal　Event　NumberMSB:　1st_Word　　Bit11LSB:　2nd_Word　Bit0

28bitsGrobal　Event　Number:0000000H FFFFFFFH～

Remove　the　lower- 4bit　from　32bit

HEADER

p 　 33

DATA Format

• RAW-DATA cell• Function

• This cell includes incoming 32bits raw-data from TDC’s FIFO.

• Header-ID value• length 　： 4bit• value = 1101(b)

• TDC-ID

• length ：　 4bit

• TDC-ID code is allocated to the TDC device on the ATM board.

• RAW － DATA

• length ：　 32bit

• 32bits raw-data read out from TDC is stored into one RAW-DATA cell.

p 　 34

DATA Format

• RAW-DATA cell format

RAW cell Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word

Reserved:

RAW-data of TDCMSB: 2nd_Word Bit15

LSB: 3rd_Word Bit032bits

RAW-data of TDC:Header/Single measurement data/Trailer

Bit Location Length Function

HEADERMSB: 1st_Word Bit15LSB: 1st_Word Bit10

4bitsHEADER code:

1101B (code of RAW cell)

RAW-data of TDC (bit15 - 0)

Bit

HEADER

RAW-data of TDC (bit31 - 16)

TDC ID Reseved

TDC IDMSB: 1st_Word Bit11LSB: 1st_Word Bit8

4bitsTDC ID:

0000B,0001B,0010B,0011B

ReservedMSB: 1st_Word Bit7LSB: 1st_Word Bit0

8bits

p 　 35

DATA Format

• RAW-DATA cell format : 　 TDC-ID field

11 10 9 8

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

1 1 x x

1 x x x

BIT Function

TDC0 (Ch0-5)

TDC1 (Ch6-11)

TDC2 (Ch12-17)

not used

TDC IDTDC3 (Ch18-23)

not used

p 　 36

DATA Format

• Status-message cell• Function

• This cell informs status of events on the ATM board.

• This will allow to get the error information without polling accesses from the host controller.

• Header-ID value

• length 　： 4bit

• value = 1110(b)

• Classification

• length ：　 2bit

• This code classifies device or circuit block on the ATM board.

• Device-Number

• length ：　 4bit

• This code identifies the number of selected device on the ATM board.

• Status-ADR

• length ：　 6bit

• Status value

• Length: 32bit

p 　 37

DATA Format

• Status-message cell format

Status-message cell Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1st_Word

2nd_word

3rd_Word

Status-ValueMSB: 2nd_Word Bit15

LSB: 3rd_Word Bit032bits

Status-Value:value for selected status-function

Status-ADRMSB: 1st_Word Bit5LSB: 1st_Word Bit0

6bitsStatus-ADR:

selected status address

Device-NumMSB: 1st_Word Bit9LSB: 1st_Word Bit6

4bitsDevice-Number :

Device number for selected any devices

Class.MSB: 1st_Word Bit11LSB: 1st_Word Bit10

2bitsClassification:

identify for Devices or Blocks

Function

HEADERMSB: 1st_Word Bit15LSB: 1st_Word Bit10

4bitsHEADER code:

1110B (code of Status cell)

Status-Value (bit15 - 0)

Status-ADR

Bit

HEADER

Status-Value (bit31 - 16)

Class.

Bit Location Length

Device-Num