aurora quick start

Aurora Quick Start Guide XUP Virtex-2 Pro Development System

Aurora Quick Start Guide

Introduction In this guide, you will establish a point-to-point connection between two MGTs (ie. Loopback or board-to-board) via the SATA connectors on the XUP Virtex-2 Pro board. The XUP Virtex-2 Pro Development System contains a Virtex-2 Pro XC2VP30 that is equipped with eight Rocket IO Multi-Gigabit Transceivers. Four of the eight transceivers have been brought out to connectors (Figure 1) on the XUP board: three to Serial ATA connectors and one to a user-supplied SMA connector. The SATA channels are split into two interface formats, two HOST ports and a TARGET port. The TARGET port interchanges the transmit and receive differential pairs to allow two XUP Virtex-2 Pro boards to be connected as a simple network, or multiple boards to be connected in a ring.

SATA 1 Target

SATA 0 Host

S
ATA 2Host
User Supplied SMA Connectors

Figure 1. Illustration of Digilent XUP Virtex-2 Pro

www.xilinx.com/univ Aurora Quick Start-3 [email protected]

Objectives After participating in this guide, you will be able to: • Instantiate the Aurora core into a design to • Perform an HDL simulation of the serial link • Implement the serial link using the Xilinx tool flow • Establish a simple point-to-point link in hardware, verifying operation using Chipscope-Pro

Requirements • XUP Virtex-2 Pro development System • Low cost Serial ATA cable • v7.1 ISE Foundation + SP3 (or latest service pack) • Latest IP Update – should contain Aurora Core 2.3 • v7.1 Chipscope-Pro • MTI Modelsim SE or PE (v5.7 or later)

References • XUP Virtex-2 Pro User Guide (www.xilinx.com/univ) • Rocket IO Transceiver User Guide (http://www.xilinx.com/bvdocs/userguides/ug024.pdf) • Aurora Core User Guide (provided with generation of aurora core via CORE Generator) • Constraints Guide (http://www.xilinx.com/support/software_manuals.htm → 7.1i Software

Manuals → Select PDF/HTML → Constraints Guide on left side) • Chipscope Pro 7.1 User Manual (http://www.xilinx.com/literature/literature-chipscope.htm)

Deliverables

User to create directory called /quickstart (ie. C:/xupv2p/quickstart) and unzip aurora.zip here. After unzipping, you should see the following directories along with contents: ../quickstart/aurora/docs

• Aurora_QuickStart.doc (Aurora Quick Start Guide) • Simulation_Waveforms.ppt (Modelsim Simulation Results) • IP_Aurora.ppt (Aurora overview presentation)

../quickstart/aurora/source • Aurora_sample_onefpga.v (top-level design used for this quick start)

../quickstart/aurora/sim • Aurora_sample_tb_onefpga.v (test fixture that performs HDL simulation emulating loopback

with a serial ATA cable; this one is used in the quick start) • sim_onefpga.do (simulation script file for Modelsim; this one used to perform simulation on

using aurora_sample_tb_onefpga.v) ../quickstart/aurora/cs_proj

• Chipscope project that contains signal and net names according to the aurora_sample_onefpga.v design

../quickstart/aurora/UCF • Constraints file that contains pin locations and timing for aurora_sample_onefpga.v design

../quickstart/aurora/test


• Working .bit file that can be downloaded to the FPGA ../quickstart/aurora/core

• This is where you will generate the Aurora core files via Core Generator ../quickstart/aurora/ise

• Contains the ISE Project

Aurora Core Overview Aurora is a scalable, light-weight, link-layer protocol that is used to move data across point-to-point serial links. Figure 2 illustrates a high-level functional diagram of aurora.

Aurora Aurora Lane 1 Channel

Figure 2. Aurora in a Nutshell

Each high-speed serial connection between MGTs is called a lane. Any number of lanes can be bonded to create an Aurora channel. When the aurora channel is not being used to send data, it is filled with a random idle sequence. Aurora uses the same idle characters as the XAUI protocol, randomized for low EMI. Aurora uses 8B/10B encoding for DC balance, error detection, and to allow control characters in the data stream. Fore more information, refer to the

Aurora user guide (provided after generating the core in CoreGen) Aurora presentation (provided with this distribution)

The Aurora core can be downloaded free of charge from the Xilinx web site at: http://www.xilinx.com/products/design_resources/conn_central/grouping/aurora.htm Click on the Aurora Core link and follow the instructions to register, download, and install the Aurora core. The deliverables include

Protocol Specification Bus Functional Model (support for Modelsim, VerilogXL, VCS, and NCVerilog

simulators) Reference Designs (Key for free Xilinx Core Generator reference designs)

User

Application

User

ApplicationAurora Aurora Interface InterfaceUser User

Interface Interface

Aurora Lane n


Other Collateral (User guides, EDK based demonstration designs using PPC,

LocalLink interface specification)

Design Overview The sample design instantiates the generated Aurora core twice. One instantiation interfaces to the SATA

igure 3. Design Functional Diagram

0 host and the other to the SATA 1 target on the MGT side, which enables a loopback test using a Serial ATA cable. On the FPGA side, they interface to a counter which feeds the transmit and an error checkingmodule on the receive.

Virtex-2 Pro xc2vp30

Counter

Aurora Module 1

Transmit

eceive

SATA 0

Host

Error

F

RCheck

Aurora Module 2

Transmit

eceive

Counter

Error

SATA 1

Target R

tx_di_1

rx_di_2

tx_di_2

rx_di_1

MGT

MGT

Check


Procedure In this guide, you will perform the following steps

on the design

o the ISE project and instantiate the aurora core

Add and Modify the UCF hipscope Cores

Step 1: Generate the Aurora Core Step 2: Setup for MGT simulation Step 3: Perform an HDL simulationStep 4: Open an ISE project Step 5: Add a sample design tStep 6: Debug with Chipscope Analyzer Conclusion Appendix A:Appendix B: Generate and Instantiate the C

Generate the Aurora Core Step 1

You will invoke Core Generator to specify parameters and generate the Aurora core.

Go to Start → Programs → Xilinx ISE v7.1 → Accessories → CORE Generator

Click on Create a New Project

Browse to ..\quickstart\aurora\core directory, enter aurora_link as the name, and click Next to continue

Figure 4. Creating a New CORE Generator Project


Note: if a dialog opens indicating that the directory does not click, click Yes to create it.

Enter the following options to target the Virtex-2 Pro device on the XUP board and click OK

Family: Virtex2P

Package: ff896

ial Interfaces, and select Aurora v2.3

Figure 6. Aurora Core Location in CORE Generator Library

Device: xc2vp30

Speed Grade: -7

Figure 5. Targeting the Virtex-2 Pro xc2vp30

Expand Communications & Networking Ser


Click on Customize an then OK if a dialog opens indicating that you do not have access to the source code

Enter the following parameters and click Next to continue Component Name: aurora_link Target Device: XC2VP30 Aurora Lanes: 1 (# of MGTs) Interface: Streaming

Figure 7. Aurora Parameters

Enter the following parameters and click Generate

Row 1 Clock: BREF_CLK Row 1, Column 0: 1


Figure 8. Specify MGT Clock and Location

Note: Refer to the “Using the Multi-Gigabit Transceivers” section of the XUP Virtex-2 Pro user guide for information on available MGT clocks. The MGT connectors are in order

1 Target, SATA 2 Host, SMAs

Review the README dialog that lists the directories created along with a description of each directory. For convenience, the file names, locations and descriptions are listed in the table below. Click <OK> when finished.

Note: You may view the generated directory structure in windows explorer

across the top row as follows: SATA 0 Host, SATA


Setting up for MGT Simulation Step 2

The Xilinx MGT simulation model is distributed in Smart Model/SWIFT format, which are encrypted versions of the actual HDL code. These models allow the user to simulate the actual functionality of the design without having to access the code itself. A simulator with SmartModel capability, such as Modelsim, is required to use SmartModels.

In this step, you will verify that the SWIFT models are properly setup on your system.

Go to www.xilinx.com/support and browse for the following solution records:

Solution record #14019 which explains the setup process Set the LMC_HOME environment variable Modify the modelsim.ini

Solution record #15338 which explains the Xilinx Modelsim library installation process Using the CompXlib utility via command prompt (ie. compxlib –s mti_se –f all – l all -0

c:\modeltech_6.0b\xilinx_libs)

Simulate

the Design Step 3 There are two Modelsim *.do files provided that enable to you simulate the design. These files perform the following tasks:

Maps to the relevant Xilinx Modelsim libraries

You will mroject directories. Next, you will open up Modelsim and simulate the design.

There are two test benches available:

aurora_sample_tb_onefpga: intantiates the DUT and implements the external MGT cable along with control and clock/reset

aurora_sample_tb_twofpga: tests point-to-point link between two XUP boards

Open the sim_onefpga.do file in a text editor such as Word Pad

Compiles the Verilog files Loads relevant signals into the wave viewer Executes for 120us

odify the file(s) according to your Modelsim installation path and p


Modify the directory paths for the map n of the XiliModelsim Libraries and save the file

ping as appropriate to your installatio nx

Ex. vmap XilinxCorelib_ver /Modeltech_6.0b/xilinx_libs/XilinxCoreLib_ver

Enter the following command at the Modelsim prompt

Not for clock rate differences between the s iggers 6 clock compensation transfers every 500 c

pen the ISE Project Step 4

Open Modelsim and change to the /sim directory. For example, you may use the cd commandas follows:

> cd c:/quickstart/aurora/sim

> do sim_onefpga.do

View the waveform in the Modelsim waveform viewer, referencing the Simulation_Waveform.ppt file provided with the distribution

e: The Aurora protocol provides a compensating mechanismtra _manager.v file trn mitter and receiver. The cc

cy les 0

O

Launch the ISE Project Navigator and create a new design project.

ams → Xilinx ISE 7.1i → Project Navigator

the Project Navigator, select File → Open Project, and browse to the /ise subdirectory

Select aurora_link.ise and click <Open>

Select Start → Progr

In

Figure 9. Open Project


Note: You will notice several modules that consist of verilog design files and a UCF file. Other modules are listed with a red question mark, which indicates a black box.

Figure 10. Sources in New Project.

ck <OK> when

Figure 11. Device and Design Flow Dialog

Double-click on the device line and review the settings and tool options. Clifinished.


Add the Aurora Core Files to Project Step 5

You will instantiate the generated Aurora core in the design. The design includes two instances of the Aurora Core, one that connects to the SATA host 0 port and one that connects to the SATA Target 1 port. An ever increasing count sequence drives the data input to the transmitters on both instances. You will also add the UCF, which is the user constraints file. This file contains location constraints for the MGT, as well as timing and location constraints for the clock signals. Refer to Appendix A for more information on adding the constraints for the Aurora design.

In the ISE Project Navigator, go to Project → Add Source

Browse to the \src subdirectory created when running CORE generator, select all files using CTRL + Shift keys, and add them to the project

Figure 12. Add Aurora Source Files to Project

to Project → Add Source, browse to the \cc_manager subdirectory, and add the andard_cc_module.v as a Verilog Design File to the ISE project

Expand User Constraints in the Processes for Source window and double-click on Edit aints (Text) to view the constraints that are placed on the design.

ote that these constraints have been modified from the original copy generated from Core rator as there are two instances of the Aurora core in the design.

Gost

Constr N

Gene


Figure 13. Edit Constraints (Text)

All the files are now added, and you should see the hierarchy similar to Figure 17.

Figure 14. Hierarchichal View of Design


Debug with Chipscope Analyzer Step 6

The Chipscope cores have already been generated and pre-connected in the design (refer to appendix B). Use the Chipscope Analyzer interfaces directly to the ICON and ILA cores. You will configure the device, specify trigger options, setup the console, and view results on the fly.

Right-click on Translate in the Processes for Source window, and select Properties.

Click on the Macro Search Path and br se to the /cs_proj directory.

the chipscope core netlists when implementing the esign.

Double-click on Analyze Design Using Chipscope in the Processes for Source window of the ISE Project Navigator.

Note: This may run through Synthesis, Implementation, and bitstream generation

Connect the JTAG download and Serial ATA cables, and power up the board.

ow

Note: The ISE software will included

Figure 15. XUP Board with Cable Connections


Figure 16. Chipscope Pro Analyzer

Click <OK> in the JTAG Chain Device Order dialog, which lists all the devices detected in the JTAG chain on the target board.

Click on the Open Cable/Search JTAG Chain icon


igure 17. JTAG Chain Device Order

Review the various windows displayed in the Chipscope Analyzer, which include the ILA units, Signal view, Trigger Setup, and Display windows.

Note: The Data and Trigger port signals to not reflect the signal names in the design.

igure 18. Chipscope Pro Analyzer Windows

Go to File → Open Project and select aurora_link_cs.proj from the \cs_proj directory.

Note: A chipscope pro project has been created for you, which includes all of the appropriate signal names for the trigger/data port connections.

F

F


Double-click on Trigger Setup under UNIT:0 MyILA0 (see Figure ) under the Project window pane on the upper left side of the window.

Note: The trigger value is left un-defined for this example. However, the user may go in and specify trigger conditions according to design specifications.

Figure 19. Trigger Setup for ILA Unit 0

Select the Click the Apply Settings and Arm Trigger icon

Note: The trigger stays armed until the trigger condition is satisfied. In this guide, we specify the trigger condition as don’t care (X) values so the ILA/ICON cores will automatically capture data when armed.


Figure 23. Apply Settings and Arm Trigger

Right-click on a value (ie. 16770) for tx_d_i_1 in the waveform view and select Place O Cursor.

Figure 20. Place O Cursor on Transmit Value

Scroll through the waveform and find the same value for the rx_d_i_2, right-click on the waveform, and select Place X Cursor.


Figure 21. Place X Cursor on Receive Value

Note the (X-O) value in the bottom right-hand side of the waveform view, which indicates the number of clock pulses between the transmit and receive. This will help to determine the latency of the cable.

Figure 22. Chipscope Pro Waveforms

Transmit216770

Receive 16770

Latency of 38 clock

cycles



Conclusion

In this quick start guide, you completed the major stages of generating the Aurora core using Core Generator and instantiating the generated core in a simple design. You performed an HDL simulation of the design using Modelsim. Next, you generated ICON and ILA Chipscope Pro cores and inserted them into the design. Finally, you invoked Chipscope Pro Analyzer to perform an on-chip verification.

Add and Modify the UCF Appendix A

The aints file) is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor. You can also use the Constraints Editor to create constraints within a UCF file. These constraints affect how the logical design is implemented in the target device. The following figure illustrates the UCF flow.

Figure 23. UCF Flow The UCF file is an input to NGDBuild (see the preceding figure). The constraints in t ation in the NGD file produced by NGDBuild. For FPGAs, som aints are used when the design is mapped by MAP and some of the constraints are written into the PCF (Physical Constraints File) produced by MAP. The constraints in the PCF file are used by each of the physical design tools (for example, PAR and the timing analysis

ols), which are run after your design is mapped.

UCF (user constr

he UCF file become part of the informe of these constr

to

There aretiming, p

various constraint types that can be entered in the UCF file that include lacement, grouping, mapping, routing, modular design, synthesis, fitter,

d for the Aurora core contains constraints that set the locations of input clock pins, as well as period constraints that communicate the timing speed objectives to Implementation process of the ISE flow. Other constraints are provided to initialize the MGT.

Figure 24. Serial ATA Clock Overview The UCF provided during the generation of the Aurora core from CoreGen includes constraints for only one instance of the Aurora core. The UCF file has been updated to include constraints for two instances of the Aurora core, ccording to the design. This was accomplished by simply copying the and

s in the UCF file, so that there were two sets of identical onstraints. The constraint paths were then updated according to the instance

r

initialization, and DLL/DCM. Figure illustrates a high-level functional diagram of connections between the 75MHz Serial ATA differential clock source and the MGTs & input clock buffer. The UCF file generate

BREF_CLK_P

MGT – SATA

apasting the constraintcnames in the top-level Verilog code. The MGT locations were also updated to place the MGTs (and MGT pinouts) in their respective positions to interface to the SATA 0 host and SATA 1 target connectors. Constraints were also added foclock signals to provide a period constraint and clock pin location on the FPGA.

75 MHz Serial ATA Clock

Source BREF_CLK_N

IB O I

Differential Clock Buffer

Differential

_i

Clock Output

Global Clock

user clk

Buffer Top_BREF_CLK_i

Virtex-2 Pro xc2vp30


Note: Highlighted text below indicates key constraints that will need to be updated according to

1 at http://www.xilinx.com/support/mysupport.htm

your design. The following steps were taken • Modified syntax for PERIOD constraints (This is due to error generated in software: perform

a search for solution record # 2097 )

# Timing Contraints for the MGT Recovered clock. These period constraints should match the # period used for your MGT reference clock (REFCLK, REFCLK2, BREFCLK or BREFCLK2). This # constraint controls the routing between each MGT's REC_CLK port and the phase alig# module for t NET aurora_module_i_1/lane_0_mgt_i/RXRECCLK PERIOD=13.3 ns; NET aurora_module_i_2/lane_0_mgt_i/RXRECCLK PERIOD=13.3 ns; #Sample user clock constraint NET user_clk_i PERIOD = 13.3 ns; NET top_BREF_CLK_i PERIOD = 13.3 ns; ############################### Init values ############################### #When the FPGA powers up, the AURORA Module should reset itself once and #prepare its pseudorandom Idle sequence generators INST global_logic_i/idle_and_ver_gen_i/lfsr_last_flop_i INIT= 0; INST global_logic_i/idle_and_ver_gen_i/lfsr_taps_i INIT= 0; INST gINST gINST gINST g INST g INST g INST gINST g INST global_logic_i/idle_and_ver_gen_i/gen_k_flop_0_i INIT= 0; INST global_logic_i/idle_and_ver_gen_i/gen_r_flop_0_i INIT= 0; INST global_logic_i/idle_and_ver_gen_i/gen_k_flop_1_i INIT= 0; NST g obal_logic_i/idle_and_ver_gen_i/gen_r_flop_1_i INIT= 0;

• Copied Initialization, Lane 0, and Attribute constraints, and then pasted at the bottom of UCF file to create constraints for the second MGT in the design

• Modified paths to reflect location in design hierarchy for each MGT • Modified location constraint for 2nd MGT (providing a simple line of text automatically

updates all pin locations for the MGT)

n hat lane

lobal_logic_i/idle_and_ver_gen_i/ver_counter_0_i INIT= 0000; lobal_logic_i/idle_and_ver_gen_i/ver_counter_1_i INIT= 0000; lobal_logic_i/channel_init_sm_i/free_count_1_i INIT= 8000; lobal_logic_i/channel_init_sm_i/free_count_2_i INIT= 8000;

lobal_logic_i/channel_init_sm_i/reset_lanes_flop_i INIT= 1;

lobal_logic_i/idle_and_ver_gen_i/gen_a_flop_0_i INIT= 0;

lobal_logic_i/idle_and_ver_gen_i/gen_v_flop_0_i INIT= 0; lobal_logic_i/idle_and_ver_gen_i/gen_v_flop_1_i INIT= 0;

I l


########################## Lane 0 Constraints #################### #Constraint locatation of the registers in the Phase Align Module. This insures # correct timing with respect to the MGT's enable comma align signal INST l eAREA_G UAREA_GROUP "PHASE_ALIGN_0_GRP" RANGE=SLICE_X14Y152:SLICE_X15Y153; # Place lane_0_mgt_i at location X0Y1 INST lane_0_mgt_i LOC=GT_X0Y1;

K_V_SEL = 1; R_INSERT_IDLE_FLAG = FALSE;

ST lane_0_mgt_i CLK_COR_SEQ_1_2 = 00111110111; _3 = 00111110111;

= 00111110111; E = FALSE;

= 2; = TRUE;

ST lane_0_mgt_i COMMA_10B_MASK = 1111111111; 100000101; 011111010;

= FALSE;

an _0_phase_align_i/phase_align_flops_r* RO P="PHASE_ALIGN_0_GRP";

# Set the attributes for lane_0_mgt_i INST lane_0_mgt_i ALIGN_COMMA_MSB = TRUE; INST lane_0_mgt_i CHAN_BOND_MODE = OFF; INST lane_0_mgt_i CHAN_BOND_ONE_SHOT = FALSE; INST lane_0_mgt_i CHAN_BOND_SEQ_1_1 = 00101111100; INST lane_0_mgt_i REF_CLST lane_0_mgt_i CLK_COIN

INST lane_0_mgt_i CLK_COR_KEEP_IDLE = FALSE; INST lane_0_mgt_i CLK_COR_REPEAT_WAIT = 8; ST lane_0_mgt_i CLK_COR_SEQ_1_1 = 00111110111; IN

ININST lane_0_mgt_i CLK_COR_SEQ_1INST lane_0_mgt_i CLK_COR_SEQ_1_4 ST lane_0_mgt_i CLK_COR_SEQ_2_USIN

INST lane_0_mgt_i CLK_COR_SEQ_LEN ST lane_0_mgt_i CLK_CORRECT_USE IN

ININST lane_0_mgt_i MCOMMA_10B_VALUE = 1INST lane_0_mgt_i PCOMMA_10B_VALUE = 0ST lane_0_mgt_i RX_CRC_USE IN

INST lane_0_mgt_i RX_DATA_WIDTH = 2; INST lane_0_mgt_i RX_LOSS_OF_SYNC_FSM = FALSE; INST lane_0_mgt_i RX_LOS_INVALID_INCR = 1; ST lane_0_mgt_i RX_LOS_THRESHOLD = 4; IN

INST lane_0_mgt_i SERDES_10B = FALSE; INST lane_0_mgt_i TERMINATION_IMP = 50; INST lane_0_mgt_i TX_CRC_USE = FALSE; INST lane_0_mgt_i TX_DATA_WIDTH = 2; INST lane_0_mgt_i TX_DIFF_CTRL = 600; INST lane_0_mgt_i TX_PREEMPHASIS = 1;

Figure 25. Original Aurora Constraints Generated in Core Generator


Generate and Instantiate the Chipscope Cores Appendix B ChipScope Pro inserts logic analyzer, bus analyzer, and Virtual I/O low-profile

software cores into your design. These cores allow you to view all the internal luding the IBM CoreConnect Processor

d at or near operating system speed ing up pins for your through the ChipScope

ed controller n using the Chipscope-

Generator

signals and nodes within your FPGA, incl Bus supporting the IBM PowerPC 405 inside Local Bus or On-Chip Periphera

The Virtex-II Pro FGPA. Signals are captureand brought out through the programming interface, free

eddesign, not debug. Captured signals can then be analyzPro Logic Analyzer.

t the integrat The following steps were taken to generate and inser

(ICON) and integrated logic analyzer (ILA) into the desigPro Core Generator.

Go to Start → Program → Chipscope Pro 7.1i → Chipscope Pro Core

Next>

With the ICON (Integrated Controller) option selected, click <


Figure 26. Generate an ICON core

Set the path for the Output Netlist to a subdirectory called cs_cores in the project directory, select Virtex2P as the Device Family, specify the Number of Control Ports as 2 and click <next> to continue

Note: You will connect up two ILA cores to the controller.


Figure 27. Specify ICON options

Verify that a check appears next to Generate HDL Example File, select Verilog as the HDLLanguage, and click <Generate>


igure 28. Generate the ChipscopF e ICON core

e instantiated in the design) icon_xst_example.v (verilog instantiation example)

Open the icon_xst_example.v file with an editor such as Word Pad and review the

instantiation template

Browse to the cs_cores directory and notice the following key files

icon.edn (netlist core that will b


module icon_xst_example ( ); //----------------------------------------------------------------- // // ICON core wire declarations // //----------------------------------------------------------------- wire [35:0] control0; wire [35:0] control1; //----------------------------------------------------------------- // // ICON core instance // //----------------------------------------------------------------- icon i_icon ( .control0(control0), .control1(control1) ); endmodule //------------------------------------------------------------------- // // ICON core module declaration // //------------------------------------------------------------------- module icon ( control0, ); output 5 output 5endmodule Figure 29. ICON XST Verilog Example

Note: The ICON core is already instantiated in the design. Typically, this is a manual process that must be completed by the designer.

control1

[3 :0] control0; [3 :0] control1;


nerate and insert two logic analyzer (ILA) cores into the

design to monitor data that is transmitted/received between the Aurora links. One ILA core will be used to debug transmission/reception between the transmit 1 –

receive 2 path, while the other ILA core will be used to debug between the

e Pro 7.1i → Chipscope Pro Core Generator

e

In this step, you will ge

transmit 2 – receive 1 path.

Go to Start → Program → Chipscop

With the ILA (Integrated Logic Analyzer) option selected, click <Next>

Figure 30. Generate an ILA Cor


Set the path for the Output Netlist to a subdirectory called cs_cores in the project directory, select Virtex2P as the Device Family, specify the Number of Control Ports as 2 and click

and click

Number if Input Trigger Ports: 1

Counter Width: Disabled Match Type: Extended Enable Trigger Sequence: unchecked

<next> to continue

Figure 31. Specify ILA Options

Specify the following options for the Trigger Input and Match Unit Settings<Next>

Trigger Width: 39 # Match Units: 1


Figure 32. Specify ILA Trigger Options

Click to place a check mark next to Data Same as Trigger and click <Next>


igure 33. Specify ILA Data Port Settings

Under HDL Example File Settings, click to place a check mark next to Generate HDL Example File, select Verilog as the HDL Language, specify Xilinx XST as the synthesis tool, and click Generate Core.

Browse to the cs_cores directory and notice the following key files

ila.edn (netlist that will be instantiated into the design as a black box) ila_xst_example.v (instantiation example)

Open the icon_xst_example.v file (see figure below) with an editor such as Word Pad

Copy the declaration and instantiations at the appropriate places in the top-level Verilog

design

F


module ila_xst_example ( ); //----------------------------------------------------------------- // // ILA Core wire declarations // //----------------------------------------------------------------- wire [35:0] control; wire clk; wire [38:0] trig0; //----------------------------------------------------------------- // // ILA core instance // //----------------------------------------------------------------- ila i_ila ( .control(control), .clk(clk), .trig0(trig0) ); endmodule //------------------------------------------------------------------- // // ILA core module declaration // //------------------------------------------------------------------- module ( contr clk, trig0 ); input [35:0] control; input c ; input [ :ndmodule

igure 34. ILA XST Verilog Example

ila

ol,

lk 38 0] trig0;

e

F


aurora quick start

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