automotive interview questions

7/21/2019 Automotive Interview Questions

1/61

Automotive Interview Questions

CAN INTERVIEW QUESTIONS:

1. What is CAN and its uses?

Answer:1. CAN is a multi-master broadcast serial bus standard for connecting electronic

control unit (ECUs).

2. Controllerarea network (CAN or CAN-bus) is a e!icle bus standard designed to allow

microcontrollers a deices to communicate wit! eac! ot!er wit!in a e!icle wit!out a !ost

com"uter.

#. CAN is a message-based "rotocol$ designed s"eci%call& for automotie a""lications but

now also used in ot!er areas suc! as industrial automation and medical e'ui"ment.

. !e Controller Area Network (CAN) bus is a serial as&nc!ronous bus used in

instrumentation a""lications for industries suc! as automobiles.

USES:

*ore reliabl&$ e.g.$ fewer "lug-in connectors t!at mig!t cause

errors.

+iring less com"licated$ more economic.

Eas& to im"lement$ c!anges$ too.

Additional elements (e.g.$ control units) are eas& to integrate.

,nstallation "lace ec!angeable wit!out electric "roblems.

+ire ma& be diagnosed.

2. CAN frae w!r"s?

Answer:/0 1 ominant

Arbitration 0ield 11 bit ,denti%er$ 1 bit (or) 11 bit$ 1$ 1,E$ 13 bit$ 1

Control 0ield ,E$ r4$ bits (5C)

ata 0ield (4-3) 6&tes

CC 0ield 17 bits$ elimiter (1 bit recessie)

AC8 0ield 1 bit$ elimiter (1 bit recessie)

E/0 9 bits recessie


2/61

,0 # bits recessie

&"es of frames ata$ remote$ Error frame and /erload frame

&"es of errors AC8 error$ 6it error$ tu: error$ 0orm error$ CC error

Error frame 4-12 su"er"osition ;ags$ 3 recessie (elimiter)

/erload frame 4-12 su"er"osition ;ags$ 3 recessie (elimiter)

#. Wh$ CAN is ha%in& 12' !hs at ea(h end?

Answer:o minimi


3/61

dominant leel. !is is detected b& node 6 because t!e transmitted alue is not e'ual to t!e

receied alue (Collision etection). At t!is "oint of time node 6 !as lost t!e arbitration$

sto"s t!e transmission of an& furt!er bit immediatel& and switc!es to receie mode$ because

t!e message t!at !as won t!e arbitration must "ossibl& be "rocessed b& t!is node

(Arbitration on *essage ?riorit&)

0or eam"le$ consider t!ree CAN deices eac! tr&ing to transmit messages@

eice 1 address ## (decimal or 44114114441 binar&)

eice 2 address 17 (44414411414)

eice # address 139 (44414111411)

Assuming all t!ree see t!e bus is idle and begin transmitting at t!e same time$ t!is is !ow

t!e arbitration works out. All t!ree deices will drie t!e bus to a dominant state for t!e

start-of-frame (/0) and t!e two most signi%cant bits of eac! message identi%er. Eac!

deice will monitor t!e bus and determine success. +!en t!e& write bit 3 of t!e message ,$

t!e deice writing message , ## will notice t!at t!e bus is in t!e dominant state w!en itwas tr&ing to let it be recessie$ so it will assume a collision and gie u" for now. !e

remaining deices will continue writing bits until bit 7$ t!en t!e deice writing message ,

139 will notice a collision and abort transmission. !is leaes t!e deice writing message ,

17 remaining. ,t will continue writing bits on t!e bus until com"lete or an error is detected.

Notice t!at t!is met!od of arbitration will alwa&s cause t!e lowest numerical alue message

, to !ae "riorit&. !is same met!od of bit-wise arbitration and "rioriti


4/61

"roblem. +it! ND-7 t!e transmitter transmits at most %e consecutie bits wit! t!e same

alue. After %e bits wit! t!e same alue (


5/61

1/. What is the di4eren(e etween fun(ti!n and *h$si(a+ addressin&?

Answer: 0unctional addressing is an addressing sc!eme t!at labels messages based

u"on t!eir o"eration code or content. ?!&sical addressing is an addressing sc!eme t!at

labels messages based u"on t!e "!&sical address location of t!eir source and=or

destination(s).

1. What ha**ens if I ha%e t! send !re than >$tes !f data?

Answer:!e G1# standard !as de%ned a met!od of communicating more t!an 3 b&tes ofdata b& sending t!e data in "ackets as s"eci%ed in t!e rans"ort ?rotocol (?). !ere are two

t&"es of ?$ one for broadcasting t!e data$ and t!e ot!er for sending it to a s"eci%c address.

C consists of com"onents ?N$ 0*,$ /C and C*.

A C is a combination of four inde"endent %elds@ t!e us"ect ?arameter Number (?N) of

t!e c!annel or feature t!at can !ae faultsH a 0ailure *ode ,denti%er (0*,) of t!e s"eci%c

faultH t!e occurrence count (/C) of t!e ?N=0*, combinationH and t!e ?N conersion

met!od (C*) w!ic! tells t!e receiing mode !ow to inter"ret t!e ?N. oget!er$ t!e ?N$

0*,$ /C and C* form a number t!at a diagnostic tool can use to understand t!e failure t!atis being re"orted.

0igure 1 *essage format

1. What is W@2'''?

Answer: 8+? 2444(,/12#4) is a iagnostic communications standard. "eci%es "ossible

s&stem con%gurations using t!e 8 I 5 lines. As 11-2 but limited to t!e "!&sical

c!aracteristics. "eci%es "ossible s&stem con%gurations using t!e 8 I 5 lines.

7 6aud wake u" as 11- 2

New fast initialisation met!od2'. What is O7II?

Answer: /n-6oard iagnostics in an automotie contet is a generic term referring to a

e!icleJs self-diagnostic and re"orting ca"abilit&

21. Wh$ 7ia&n!sti( Standards?

Answer: As s&stems got more com"le t!e link between cause and s&m"tom became less

obious. !is meant t!at electronic s&stems !ad to !ae some leel of self diagnosis and to

communicate to t!e outside world. ,nitiall& man& s&stems used t!eir own "rotocols w!ic!

meant t!at garages !ad to !ae a large number of tools een to diagnose a single e!icle.


6/61

22. What is eant $ %eriB(ati!n and %a+idati!n??

Answer: Keri%cation and Kalidation (KIK) is t!e "rocess of c!ecking t!at a software s&stem

meets s"eci%cations and t!at it ful%lls its intended "ur"ose. ,t is normall& "art of t!e

software testing "rocess of a "roLect.

According to t!e Ca"abilit& *aturit& *odel (C**,-+ 1.1)$

Keri%cation@ !e "rocess of ealuating software to determine w!et!er t!e "roducts ofa gien deelo"ment "!ase satisf& t!e conditions im"osed at t!e start of t!at "!ase.

Kalidation@ !e "rocess of ealuating software during or at t!e end of t!e deelo"ment

"rocess to determine w!et!er it satis%es s"eci%ed re'uirements.

VeriB(ati!n s!ows conformance wit! s"eci%cationH %a+idati!ns!ows t!at t!e

"rogram meets t!e customerJs needs

2#. Can $!u ha%e tw! transitters usin& the sae e3a(t header Be+d?

Answer: No t!at would "roduce a bus con;ict

Unless &ou !ae middleware t!at ensures onl& one node can transmit at a time

0or eam"le use a low "riorit& message as a token to emulate token-"assing

2). CAN *h$si(a+ +a$er %!+ta&e +e%e+s

2,. CAN it tiin&:

According to t!e CAN s"eci%cation$ t!e bit time is diided into four segments. !e

&nc!roni


7/61

egment ?ro"eg is intended to com"ensate for t!e "!&sical dela& times wit!in t!e CAN

network. !e ?!ase 6u:er egments ?!aseeg1 and ?!aseeg2 surround t!e am"le

?oint. !e (e-)&nc!roni


8/61

and 1Os) transmitted in one second in a communication c!annel. A %gure of 244 bits "er

second means 244


9/61

egister s!ould onl& be used for ariables t!at re'uire 'uick access suc! as counters. ,t

s!ould also be noted t!at de%ning VregisterJ goes not mean t!at t!e ariable will be stored in

a register. ,t means t!at it *,WF be stored in a register de"ending on !ardware and

im"lementation restrictions.

stati( ; St!ra&e C+ass

stati(is t!e default storage class for global ariables. !e two ariables below((!untand r!ad) bot! !ae a static storage class.

static int CountHint oadHmain()T"rintf(PXdYnQ$ Count)H"rintf(PXdYnQ$ oad)H

VstaticJ can also be de%ned wit!in a function. ,f t!is is done$ t!e ariable is initali


10/61

"rintf(Pcount is XdYnQ$ count)H write()H

Count in Vsource 1O will !ae a alue of 7. ,f source 1 c!anges t!e alue of count source 2

will see t!e new alue. Fere are some eam"le source %les.

#. What is interru*t?

Answer: ,nterru"ts (also known as tra"s or ece"tions in some "rocessors) are a tec!ni'ue

of dierting t!e "rocessor from t!e eecution of t!e current "rogram so t!at it ma& deal wit!

some eent t!at !as occurred. uc! an eent ma& be an error from a "eri"!eral$ or sim"l&

t!at an ,=/ deice !as %nis!ed t!e last task it was gien and is now read& for anot!er. An

interru"t is generated in &our com"uter eer& time &ou t&"e a ke& or moe t!e mouse. ^ou

can t!ink of it as a !ardware-generated function call.

). What is 0ardware Interru*t?

Answer:!ere are two wa&s of telling w!en an ,=/ deice (suc! as a serial controller or adisk controller) is read& for t!e net se'uence of data to be transferred. !e %rst is bus&

waiting or "olling$ w!ere t!e "rocessor continuousl& c!ecks t!e deiceJs status register until

t!e deice is read&. !is wastes t!e "rocessorJs time but is t!e sim"lest to im"lement. 0or

some time-critical a""lications$ "olling can reduce t!e time it takes for t!e "rocessor to

res"ond to a c!ange of state in a "eri"!eral.

,. What is S!ftware Interru*t?

Answer: A software interru"t is generated b& an instruction. ,t is t!e lowest-"riorit& interru"t

and is generall& used b& "rograms to re'uest a serice to be "erformed b& t!e s&stem

software (o"erating s&stem or %rmware).7i4eren(e etween 0ardware Interru*t and S!ftware Interru*t

An interru"t is a s"ecial signal t!at causes t!e com"uterJs central "rocessing unit to sus"end

w!at it is doing and transfers its control to a s"ecial "rogram called an interru*t hand+er.

!e res"onsibilit& of an interru"t !andler is to determine w!at caused t!e interru"t$ serice

t!e interru"t and t!en return t!e control to t!e "oint from w!ere t!e interru"t was caused.

!e di:erence between hardware interru*tand s!ftware interru*tis as below@

0ardware Interru*t@ !is interru"t is caused b& some eternal deice suc! as re'uest to

start an ,=/ or occurrence of a !ardware failure.

S!ftware Interru*t@ !is interru"t can be inoked wit! t!e !el" of ,N instruction. A"rogrammer triggered t!is eent t!at immediatel& sto"s eecution of t!e "rogram and

"asses eecution oer to t!e ,N !andler. !e ,N !andler is usuall& a "art of t!e o"erating

s&stem and determines t!e action to be taken e.g. out"ut to t!e screen$ eecute %le etc.

!us a software interru"t as itJs name suggests is drien b& a software instruction and a

!ardware interru"t is t!e result of eternal causes.

-. What is Interru*t +aten($? 0!w d! $!u easure interru*t +aten($? 0!w t!

redu(e the interru*t +aten($?


11/61

Answer: ,nterru"t latenc& is t!e time between interru"t re'uest and eecution of %rst

instruction of t!e ,.

+e need a oscillosco"e or a logic state anal&


12/61

0ar%ard ar(hite(ture!as se"arate data and instruction busses$ allowing transfers to be

"erformed simultaneousl& on bot! buses. V!n Neuann ar(hite(ture!as onl& one bus

w!ic! is used for bot! data transfers and instruction fetc!es$ and t!erefore data transfers

and instruction fetc!es must be sc!eduled t!e& cannot be "erformed at t!e same time.

,t is "ossible to !ae two se"arate memor& s&stems for a 0ar%ard ar(hite(ture. As long as

data and instructions can be fed in at t!e same time$ t!en it doesnJt matter w!et!er it

comes from a cac!e or memor&. 6ut t!ere are "roblems wit! t!is. Com"ilers generall&embed data (literal "ools) wit!in t!e code$ and it is often also necessar& to be able to write

to t!e instruction memor& s"ace$ for eam"le in t!e case of self modif&ing code$ or$ if an

A* debugger is used$ to set software break"oints in memor&. ,f t!ere are two com"letel&

se"arate$ isolated memor& s&stems$ t!is is not "ossible. !ere must be some kind of bridge

between t!e memor& s&stems to allow t!is.

Using a sim"le$ uni%ed memor& s&stem toget!er wit! a Farard arc!itecture is !ig!l&

inecient. Unless it is "ossible to feed data into bot! buses at t!e same time$ it mig!t be

better to use a on Neumann arc!itecture "rocessor.

Use !f (a(hes

At !ig!er clock s"eeds$ cac!es are useful as t!e memor& s"eed is "ro"ortionall&

slower. 0ar%ard ar(hite(turestend to be targeted at !ig!er "erformance s&stems$ and so

cac!es are nearl& alwa&s used in suc! s&stems.

V!n Neuann ar(hite(turesusuall& !ae a single uni%ed cac!e$ w!ic! stores bot!

instructions and data. !e "ro"ortion of eac! in t!e cac!e is ariable$ w!ic! ma& be a good

t!ing. ,t would in "rinci"le be "ossible to !ae se"arate instruction and data cac!es$ storing

data and instructions se"aratel&. !is "robabl& would not be er& useful as it would onl& be

"ossible to eer access one cac!e at a time.Cac!es for Farard arc!itectures are er& useful. uc! a s&stem would !ae se"arate cac!es

for eac! bus. r&ing to use a s!ared cac!e on a Farard arc!itecture would be er&

inecient since t!en onl& one bus can be fed at a time. Faing two cac!es means it is

"ossible to feed bot! buses simultaneousl&`.eactl& w!at is necessar& for a Farard

arc!itecture.

!is also allows to !ae a er& sim"le uni%ed memor& s&stem$ using t!e same address

s"ace for bot! instructions and data. !is gets around t!e "roblem of literal "ools and self

modif&ing code. +!at it does mean$ !oweer$ is t!at w!en starting wit! em"t& cac!es$ it isnecessar& to fetc! instructions and data from t!e single memor& s&stem$ at t!e same time.

/biousl&$ two memor& accesses are needed t!erefore before t!e core !as all t!e data

needed. !is "erformance will be no better t!an a on Neumann arc!itecture. Foweer$ as

t!e cac!es %ll u"$ it is muc! more likel& t!at t!e instruction or data alue !as alread& been

cac!ed$ and so onl& one of t!e two !as to be fetc!ed from memor&. !e ot!er can be

su""lied directl& from t!e cac!e wit! no additional dela&. !e best "erformance is ac!ieed

w!en bot! instructions and data are su""lied b& t!e cac!es$ wit! no need to access eternal

memor& at all.


13/61

!is is t!e most sensible com"romise and t!e arc!itecture used b& A*s Farard "rocessor

cores. wo se"arate memor& s&stems can "erform better$ but would be dicult to im"lement

. RISC and CISC di4eren(es?

Answer:

CISC: 9Com"le Instruction Set Com"uter)

E&: ,ntel and A* C?UJs C,C c!i"s !ae a large amount of di:erent and com"le instructions.

C,C c!i"s are relatiel& slow (com"ared to ,C c!i"s) "er instruction$ but use little

(less t!an ,C) instructions.

C,C arc!itecture is to com"lete a task in as few lines of assembl& as "ossible. !is is

ac!ieed b& building "rocessor !ardware t!at is ca"able of understanding and

eecuting a series of o"erations.

,n C,C$ com"iler !as to do er& little work to translate a !ig!-leel language

statement into assembl&. 6ecause t!e lengt! of t!e code is relatiel& s!ort$ er& little

A* is re'uired to store instructions. !e em"!asis is "ut on building com"leinstructions directl& into t!e !ardware.

+!en eecuted$ t!is instruction loads t!e two alues into se"arate registers$ multi"lies

t!e o"erands in t!e eecution unit$ and t!en stores t!e "roduct in t!e a""ro"riate

register.

RISC: 9Reduced Instruction Set Com"uter

E&: A""le$ A* "rocessors

0ewer$ sim"ler and faster instructions would be better$ t!an t!e large$ com"le and

slower C,C instructions. Foweer$ more instructions are needed to accom"lis! a task.

,C c!i"s re'uire fewer transistors$ w!ic! makes t!em easier to design and c!ea"erto "roduce.

itJs easier to write "owerful o"timi


14/61

e"arating t!e P5/AQ and P/EQ instructions actuall& reduces t!e amount of work

t!at t!e com"uter must "erform.

*aLor "roblem of ,C t!e& donJt a:ord t!e wides"read com"atibilit&$ t!at 3S c!i"s

do. CISC RISC

Em"!asis on !ardware Em"!asis on software,ncludes multi-clock

com"le instructions

ingle-clock$

reduced instruction onl&*emor&-to-memor&@P5/AQ and P/EQincor"orated in instructions

egister to register@P5/AQ and P/EQare inde"endent instructions

mall code si


15/61

Assuming t!at t!e alid boot deice is found$ ,/.^ is loaded into memor& and

eecuted.,/.^ consists "rimaril& of initialiEndian and i&>Endian? 0!w (an I deterine whether a a(hineGs

$te !rder is i&>endian !r +itt+e endian? 0!w (an we (!n%ert fr! !ne t! an!ther?

0irst of all$ o &ou know w!at 5ittle-Endian and 6ig-Endian mean

5ittle Endian means t!at t!e lower order b&te of t!e number is stored in memor& at t!e

lowest address$ and t!e !ig!er order b&te is stored at t!e !ig!est address. !at is$ t!e little

end comes %rst.0or eam"le$ a b&te$ #2-bit integer6&te# 6&te2 6&te1 6&te4will be arranged in memor& as

follows@6aseAddress>4 6&te4

6aseAddress>1 6&te1

6aseAddress>2 6&te2

6aseAddress># 6&te#,ntel "rocessors use P5ittle EndianQ b&te order.Q6ig EndianQ means

t!at t!e !ig!er order b&te of t!e number is stored in memor& at t!e lowest address$ and t!e

lower order b&te at t!e !ig!est address. !e big end comes %rst.6aseAddress>4 6&te#

6aseAddress>1 6&te2

6aseAddress>2 6&te16aseAddress># 6&te4*otorola$ olaris "rocessors use P6ig EndianQ b&te order.,n P5ittle

EndianQ form$ code w!ic! "icks u" a 1$ 2$ $ or longer b&te number "roceed in t!e same wa&

for all formats. !e& %rst "ick u" t!e lowest order b&te at o:set 4 and "roceed from t!ere.

Also$ because of t!e 1@1 relations!i" between address o:set and b&te number (o:set 4 is

b&te 4)$ multi"le "recision mat!ematic routines are eas& to code. ,n P6ig EndianQ form$ since

t!e !ig!-order b&te comes %rst$ t!e code can test w!et!er t!e number is "ositie or

negatie b& looking at t!e b&te at o:set


16/61

T

"rintf(P6ig-EndianYnQ)H

And !ere is some code to conert from one Endian to anot!er.int m&reersefunc(int num)

T

int b&te4$ b&te1$ b&te2$ b&te#Hb&te4 M (num I 44444400) 4 H

b&te1 M (num I 44440044) 3 H

b&te2 M (num I 44004444) 1S Hb&te# M (num I 00444444) 2 Hreturn((b&te4 2) (b&te1 1S) (b&te2 3)

(b&te# 4))H

12. @r!&ra t! Bnd if a a(hine is i& endian !r +itt+e endian?41 include stdio.!42 de%ne 6,WEN,AN 44# de%ne 5,5EEN,AN 1

4 intmain()47 T

4S intalueH

49 alue M endian()H43 if(alue MM 1)4 "rintf(*ac!ine is little endianYn$alue)H14 else11 "rintf(*ac!ine is 6ig EndianYn$alue)H12

1# intendian() T1 s!ortintword M 44441H17 c!arZb&te M (c!arZ) IwordH1S return(b&te[4\ 5,5EEN,AN @ 6,WEN,AN)H19

1#. Swa* 2 %aria+es with!ut usin& te*!rar$ %aria+eH

a M a > bb M a b

a M a b

1). Write a *r!&ra t! &enerate the 6i!na((i Series?

includestdio.!

includeconio.!

main()

T

int n$i$c$aM4$bM1H

"rintf(PEnter 0ibonacci series of nt! term @ P)Hscanf(PXdQ$In)H

"rintf(PXd Xd P$a$b)H

for(iM4HiM(n-#)Hi>>)

T

cMa>bH

aMbH

bMcH

"rintf(PXd P$c)H


17/61

getc!()H

/ut"ut @

Enter 0ibonacci series of nt! term @ 9

4 1 1 2 # 7 3

1,. Write a *r!&ra t! Bnd uniue nuers in an arra$?

Answer:for (iM1HiMarra&.lengt!Hi>>) T

foundMfalseH

for (kMi>1HkMarra&.lengt!Hk>>) T

if (arra&[i\MMarra&[k\) foundMtrueH

if (_found) "rintln(arra&[i\)H

1-. Write a C *r!&ra t! *rint Eui+atera+ Trian&+e usin& nuers?41 =Z C "rogram to "rint E'uilateral riangleZ=

42 includestdio.!4# main()4 T

47 inti$L$k$nH4S49 "rintf(Enter number of rows of t!e triangle Yn)H43 scanf(Xd$In)H414 for(iM1HiMnHi>>)11 T12 for(LM1HLMn-iHL>>)1# T1 "rintf( )H

17 1S for(kM1HkM(2Zi)-1Hk>>)19 T13 "rintf(i)H1 24 "rintf(Yn)H21 22 getc!()H

1/. Write a *r!&ra f!r de+eti!n and inserti!n !f a n!de in sin&+e +in"ed +ist?

includestdio.!

includestdlib.!

t&"edef struct NodeT

int dataH

struct Node ZnetH

nodeH

oid insert(node Z"ointer$ int data)

T

=Z ,terate t!roug! t!e list till we encounter t!e last node.Z=

w!ile("ointer-net_MNU55)


18/61

T

"ointer M "ointer - netH

=Z Allocate memor& for t!e new node and "ut data in it.Z=

"ointer-net M (node Z)malloc(si


19/61

free(tem")H

=Z 6eacuse we deleted t!e node$ we no longer re'uire t!e memor& used for it .

free() will deallocate t!e memor&.

Z=

returnH

oid "rint(node Z"ointer)T

if("ointerMMNU55)

T

returnH

"rintf(PXd P$"ointer-data)H

"rint("ointer-net)H

int main()T

=Z start alwa&s "oints to t!e %rst node of t!e linked list.

tem" is used to "oint to t!e last node of t!e linked list.Z=

node Zstart$Ztem"H

start M (node Z)malloc(si


20/61

T

int dataH

scanf(PXdQ$Idata)H

delete(start$data)H

else if('uer&MM#)

T"rintf(P!e list is P)H

"rint(start-net)H

"rintf(PYnQ)H

else if('uer&MM)

T

int dataH

scanf(PXdQ$Idata)H

int status M %nd(start$data)Hif(status)

T

"rintf(PElement 0oundYnQ)H

else

T

"rintf(PElement Not 0oundYnQ)H

1. Can a %aria+e e !th const and volatile? es. !e const modi%er means t!at t!is

code cannot c!ange t!e alue of t!e ariable$ but t!at does not mean t!at t!e alue cannot

be c!anged b& means outside t!is code. 0or instance$ in t!e eam"le in 0A 3$ t!e timer

structure was accessed t!roug! a olatile const "ointer. !e function itself did not c!ange

t!e alue of t!e timer$ so it was declared const. Foweer$ t!e alue was c!anged b&

!ardware on t!e com"uter$ so it was declared olatile. ,f a ariable is bot! const and olatile$

t!e two modi%ers can a""ear in eit!er order.

1. what are C!nstant and V!+ati+e Qua+iBers?

const

constis used wit! a datat&"e declaration or de%nition to s"ecif& an unc!anging alue

Eam"les@ const int five = 5;

const double pi = 3.141593;

constobLects ma& not be c!anged

!e following are illegal@ const int five = 5;


21/61

const double pi = 3.141593;

pi = 3.2;

five = 6;

olatile

olatiles"eci%es a ariable w!ose alue ma& be c!anged b& "rocesses outside t!e

current "rogram

/ne eam"le of a olatileobLect mig!t be a bu:er used to ec!ange data wit! an

eternal deice@ int

check_iobuf(void)

{

volatile int iobuf;

int val;

while (iobuf == 0) {

}

val = iobuf;

iobuf = 0;

return(val);

}

if iobuf!ad not been declared olatile$ t!e com"iler would notice t!at not!ing !a""ens

inside t!e loo" and t!us eliminate t!e loo"

constand olatile can be used toget!er

An in"ut-onl& bu:er for an eternal deice could be declared as const

olatile(or olatile const$ order is not im"ortant) to make sure t!e com"iler knows

t!at t!e ariable s!ould not be c!anged (because it is in"ut-onl&) and t!at its

alue ma& be altered b& "rocesses ot!er t!an t!e current "rogram


22/61

!e ke&words constand olatilecan be a""lied to an& declaration$ including t!ose of

structures$ unions$ enumerated t&"es or t&"edef names. A""l&ing t!em to a declaration is

called 'ualif&ing t!e declaration]t!atJs w!& const and olatile are called t&"e 'uali%ers$

rat!er t!an t&"e s"eci%ers. Fere are a few re"resentatie eam"les@volatile i;

volatile int j;

const long q;

const volatile unsigned long int rt_clk;

struct{

const long int li;

signed char sc;

}volatile vs;

onJt be "ut o:H some of t!em are deliberatel& com"licated@ w!at t!e& mean will be

e"lained later. emember t!at t!e& could also be furt!er com"licated b& introducing

storage class s"eci%cations as well_ ,n fact$ t!e trul& s"ectacular

extern const volatile unsigned long int rt_clk;

is a strong "ossibilit& in some real-time o"erating s&stem kernels.

C!nst

5etJs look at w!at is meant w!en constis used. ,tJs reall& 'uite sim"le@ constmeans t!at

somet!ing is not modi%able$ so a data obLect t!at is declared wit! constas a "art of its t&"e

s"eci%cation must not be assigned to in an& wa& during t!e run of a "rogram. ,t is er& likel&

t!at t!e de%nition of t!e obLect will contain an initiali


23/61

#include

main(){

int i;

const int ci = 123;

/* declare a pointer to a const.. */

const int *cpi;

/* ordinary pointer to a non-const */

int *ncpi;

cpi = &ci;

ncpi = &i;

/*

* this is allowed

*/

cpi = ncpi;

/*

* this needs a cast

* because it is usually a big mistake,


24/61

* see what it permits below.

*/

ncpi = (int *)cpi;

/*

* now to get undefined behaviour...

* modify a const through a pointer

*/

*ncpi = 0;

exit(EXIT_SUCCESS);

}

Example 8.3

As t!e eam"le s!ows$ it is "ossible to take t!e address of a constant obLect$ generate a

"ointer to a non-constant$ t!en use t!e new "ointer. !is is an errorin &our "rogram andresults in unde%ned be!aiour.

!e main intention of introducing const obLects was to allow t!em to be "ut into read-onl&

store$ and to "ermit com"ilers to do etra consistenc& c!ecking in a "rogram. Unless &ou

defeat t!e intent b& doing naug!t& t!ings wit! "ointers$ a com"iler is able to c!eck

t!at constobLects are not modi%ed e"licitl& b& t!e user.

An interesting etra feature "o"s u" now. +!at does t!is mean

char c;

char *const cp = &c;

,tJs sim"le reall&H c"is a "ointer to a c!ar$ w!ic! is eactl& w!at it would be if

t!e constwerenJt t!ere. !e constmeans t!at c"is not to be modi%ed$ alt!oug! w!ateer it

"oints to can be]t!e "ointer is constant$ not t!e t!ing t!at it "oints to. !e ot!er wa& round

isconst char *cp;


25/61

w!ic! means t!at now c" is an ordinar&$ modi%able "ointer$ but t!e t!ing t!at it "oints to

must not be modi%ed. o$ de"ending on w!at &ou c!oose to do$ bot! t!e "ointer and t!e

t!ing it "oints to ma& be modi%able or notH Lust c!oose t!e a""ro"riate declaration.

V!+ati+e

After const$ we treat olatile. !e reason for !aing t!is t&"e 'uali%er is mainl& to do wit! t!e

"roblems t!at are encountered in real-time or embedded s&stems "rogramming using C.

,magine t!at &ou are writing code t!at controls a !ardware deice b& "lacing a""ro"riate

alues in !ardware registers at known absolute addresses.

5etJs imagine t!at t!e deice !as two registers$ eac! 1S bits long$ at ascending memor&

addressesH t!e %rst one is t!e control and status register (csr) and t!e second is a data "ort.

!e traditional wa& of accessing suc! a deice is like t!is@

/* Standard C example but without const or volatile */

/*

* Declare the device registers

* Whether to use int or short

* is implementation dependent

*/

struct devregs{

unsigned short csr; /* control & status */

unsigned short data; /* data port */

};

/* bit patterns in the csr */

#define ERROR 0x1

#define READY 0x2

#define RESET 0x4


26/61

/* absolute address of the device */

#define DEVADDR ((struct devregs *)0xffff0004)

/* number of such devices in system */

#define NDEVS 4

/*

* Busy-wait function to read a byte from device n.

* check range of device number.

* Wait until READY or ERROR

* if no error, read byte, return it

* otherwise reset error, return 0xffff

*/

unsigned int read_dev(unsigned devno){

struct devregs *dvp = DEVADDR + devno;

if(devno >= NDEVS)

return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)

; /* NULL - wait till done */


27/61

if(dvp->csr & ERROR){

dvp->csr = RESET;

return(0xffff);

}

return((dvp->data) & 0xff);

}

Example 8.4

!e tec!ni'ue of using a structure declaration to describe t!e deice register la&out and

names is er& common "ractice. Notice t!at t!ere arenJt actuall& an& obLects of t!at t&"e

de%ned$ so t!e declaration sim"l& indicates t!e structure wit!out using u" an& store.

o access t!e deice registers$ an a""ro"riatel& cast constant is used as if it were "ointing to

suc! a structure$ but of course it "oints to memor& addresses instead.

Foweer$ a maLor "roblem wit! "reious C com"ilers would be in t!e w!ile loo" w!ic! tests

t!e status register and waits for t!e E/or EA^bit to come on. An& self-res"ectingo"timi


28/61

* is implementation dependent

*/

struct devregs{

unsigned short volatile csr;

unsigned short const volatile data;

};

/* bit patterns in the csr */

#define ERROR 0x1

#define READY 0x2

#define RESET 0x4

/* absolute address of the device */

#define DEVADDR ((struct devregs *)0xffff0004)

/* number of such devices in system */

#define NDEVS 4

/*

* Busy-wait function to read a byte from device n.

* check range of device number.

* Wait until READY or ERROR


29/61

* if no error, read byte, return it

* otherwise reset error, return 0xffff

*/

unsigned int read_dev(unsigned devno){

struct devregs * const dvp = DEVADDR + devno;

if(devno >= NDEVS)

return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)

; /* NULL - wait till done */

if(dvp->csr & ERROR){

dvp->csr = RESET;

return(0xffff);

}

return((dvp->data) & 0xff);

}

Example 8.5

!e rules about miing olatileand regular t&"es resemble t!ose for const. A "ointer to

a olatileobLect can be assigned t!e address of a regular obLect wit! safet&$ but it is

dangerous (and needs a cast) to take t!e address of a olatileobLect and "ut it into a "ointer

to a regular obLect. Using suc! a deried "ointer results in unde%ned be!aiour.


30/61

,f an arra&$ union or structure is declared wit! constor olatileattributes$ t!en all of t!e

members take on t!at attribute too. !is makes sense w!en &ou t!ink about it]!ow could a

member of a conststructure be modi%able

!at means t!at an alternatie rewrite of t!e last eam"le would be "ossible. ,nstead of

declaring t!e deice registers to be olatilein t!e structure$ t!e "ointer could !ae been

declared to "oint to a olatilestructure instead$ like t!is@struct devregs{

unsigned short csr; /* control & status */

unsigned short data; /* data port */

};

volatile struct devregs *const dvp=DEVADDR+devno;

ince d""oints to a olatileobLect$ it not "ermitted to o"timi


31/61

,f &ou do want to get a s!ort!and wa& of attac!ing a 'uali%er to anot!er t&"e$ &ou can

use t&"edefto do it@struct x{

int a;

};

typedef const struct x csx;

csx const_sx;

struct x non_const_sx = {1};

const_sx = non_const_sx; /* error - attempt to modify a const */

2'.What are the di4eren(es etween a uni!n and a stru(ture in C?

A union is a wa& of "roiding an alternate wa& of describing t!e same memor& area. ,n t!is

wa&$ &ou could !ae a struct t!at contains a union$ so t!at t!e PstaticQ$ or similar "ortion of

t!e data is described %rst$ and t!e "ortion t!at c!anges is described b& t!e union. !e idea

of a union could be !andled in a di:erent wa& b& !aing 2 di:erent structs de%ned$ and

making a "ointer to eac! kind of struct. !e "ointer to struct PaQ could be assigned to t!e

alue of a bu:er$ and t!e "ointer to struct PbQ could be assigned to t!e same bu:er$ but now

a-some %eld and b-some ot!er%eld are bot! located in t!e same bu:er. !at is t!e idea

be!ind a union. ,t gies di:erent wa&s to break down t!e same bu:er area.

!e di:erence between structure and union are@ 1. union allocates t!e memor& e'ual to t!e

maimum memor& re'uired b& t!e member of t!e union but structure allocates t!e memor&

e'ual to t!e total memor& re'uired b& t!e members. 2. ,n union$ one block is used b& all t!e

member of t!e union but in case of structure$ eac! member !ae t!eir own memor& s"ace

7i4eren(e etween Stu(ture and Uni!n :

Stru(ture Uni!ni. A((ess


32/61

VstructJ ke&word is used to declarestructure. VunionJ ke&word is used to declare union.%. S$nta3struct struct_name

{

structure element 1;

structure element 2;

----------

----------

structure element n;

}struct_var_nm;

union union_name

{

union element 1;

union element 2;

----------

----------

union element n;

}union_var_nm;

%i. E3a*+estruct item_mst

{

int rno;

char nm[50];

}it;

union item_mst

{

int rno;

char nm[50];

}it;

7i4eren(e in their Usa&e:+!ile structure enables us treat a number of di:erent ariables stored at di:erent in

memor& $ a union enables us to treat t!e same s"ace in memor& as a number of di:erent

ariables. !at is a Union o:ers a wa& for a section of memor& to be treated as a ariable of

one t&"e on one occasion and as a di:erent ariable of a di:erent t&"e on anot!er occasion.

!ere is fre'uent re'uirement w!ile interacting wit! !ardware to access access a b&te or

grou" of b&tes simultaneousl& and sometimes eac! b&te indiiduall&. Usuall& union is t!e

answer.

MMMMMMMi:erence +it! eam"leMMMMMMM

5ets sa& a structure containing an int$c!ar and ;oat is created and a union containing int

c!ar ;oat are declared.


33/61

struct T int aH ;oat bH c!ar cH Union UUT int aH ;oat bH c!ar cH

si


34/61

union bar

T

c!ar cH

long lH

c!ar Z"H

H

int main(int argc$c!ar Zarg[\)

T

struct foo m&fooH

union bar m&barH

m&foo.c M 1H

m&foo.l M 25H

m&foo." M P!is is m&fooQH

m&bar.c M 1H

m&bar.l M 25H

m&bar." M P!is is m&barQH

"rintf(Pm&foo@ Xd Xld XsYnQ$m&foo.c$m&foo.l$m&foo.")H

"rintf(Pm&bar@ Xd Xld XsYnQ$m&bar.c$m&bar.l$m&bar.")H

return 4H

MMMMMMMMMM

/n m& s&stem$ , get@

m&foo@ 1 2 !is is m&foo

m&bar@ 144 199S !is is m&bar

MMMMMMMMMM

credit to original aut!or.

Stru(ture:tructure is a combination elements$ w!ic! can be "rede%ned data t&"es or

ot!er structure. !e lengt!=si


35/61

MM Answer MM Union allocates t!e memor& e'ual to t!e maimum memor& re'uired b& t!e

member of t!e union but structure allocates t!e memor& e'ual to t!e total memor& re'uired

b& t!e members. ,n union$one block is used b& all t!e member of t!e union but in case of

structure$ eac! member !ae t!eir own memor& s"ace.

21. What is eant $ stru(ture *addin&?

Answer: com"ilers "ad structures to o"timi


36/61

c2 can t!en a""ear in t!e aailable memor& location$ !oweer l1 must be at a b&te

boundar& so t!ere are # "adding b&tes between c2 and l1

c# t!en a""ear in t!e aailable memor& location$ !oweer because t!e structure contains a

long member t!e structure must be b&te aligned and must be a multi"le of b&tes in si


37/61

l1 b&te 1

l1 b&te 2

l1 b&te #

l1 b&te

s1 b&te 1

s1 b&te 2

c1c2

c#

"adding b&te

"adding b&te

"adding b&te

and is onl& 12 b&tes long.

, s!ould "oint out t!at structure "acking is "latform and com"iler (and in some casescom"iler switc!) de"endent.

*emor& ?ools are Lust a section of memor& resered for allocating tem"oraril& to ot!er "arts

of t!e a""lication

A memor& leak occurs w!en &ou allocate some memor& from t!e !ea" (or a "ool) and t!en

delete all references to t!at memor& wit!out returning it to t!e "ool it was allocated from.

@r!&ra: struct *&tructA T

c!ar aH

c!ar bH

int cH

H

struct *&truct6 T

c!ar aH

int cH c!ar bH

H

int main(oid) T

int si


38/61

"rintf(P6 M XdYnQ$ si


39/61

t!read can call it mean t!ere is se"arate eecution stack and !andling for eac!. o function

s!ould not contain an& static or s!ared ariable w!ic! can !arm or disturb t!e eecution.

*ean function w!ic! can be called b& t!read$ w!ile running from anot!er t!read safel& and

"ro"erl&

E3a*+e:int t;

void swap(int *x, int *y)

{

int s;

s = t; // save global variable

t = *x;

*x = *y;

// hardware interrupt might invoke isr() here!

*y = t;

t = s; // restore global variable

}

void isr()

{

int x = 1, y = 2;

swap(&x, &y);

}

Re(ursi%e fun(ti!n E3a*+e:


40/61

oid doll ( int si

moing down in a linear wa&$ t!e "rocess ste"s are bent u"wards after t!e coding "!ase$ to

form t!e t&"ical K s!a"e. !e K-*odel demonstrates t!e relations!i"s between eac! "!aseof t!e deelo"ment life c&cle and its associated "!ase of testing.

!e K model !as a number of bene%ts@

1. &stems deelo"ment "roLects usuall& !ae a test a""roac!$ or test strateg& document$

w!ic! de%nes !ow testing will be "erformed t!roug!out t!e lifec&cle of t!e "roLect. !e K

model "roides a consistent basis and standard for "art of t!at strateg&.

2. !e K model e"licitl& suggests t!at testing ('ualit& assurance) s!ould be considered

earl& on in t!e life of a "roLect. esting and %ing can be done at an& stage in t!e lifec&cle.Foweer$ t!e cost of %nding and %ing faults increases dramaticall& as deelo"ment

"rogresses. Eidence suggests t!at if a fault uncoered during design costs 1.4 monetar&

unit to correct$ t!en t!e same fault uncoered Lust before testing will cost S.7 units$ during

testing 17 units$ and after release between S4 and 144 units. !e need to %nd faults as soon

as "ossible reinforces t!e need for t!e 'ualit& assurance of documents suc! as t!e

re'uirements s"eci%cation and t!e functional s"eci%cation. !is is "erformed using static

testing tec!ni'ues suc! as ins"ections and walkt!roug!s.

#. ,t introduces t!e idea of s"ecif&ing test re'uirements and e"ected outcomes "rior to"erforming t!e actual tests. 0or eam"le$ t!e acce"tance tests are "erformed against a

s"eci%cation of re'uirements$ rat!er t!an against some criteria dreamed u" w!en t!e

acce"tance stage !as been reac!ed

. !e K model "roides a focus for de%ning t!e testing t!at must take "lace wit!in eac!

stage. !e de%nition of testing is assisted b& t!e idea of entr& and eit criteria. Fence$ t!e

model can be used to de%ne t!e state a delierable must be in before it can enter and leae

eac! stage. !e eit criteria of one stage are usuall& t!e entr& criteria of t!e net. ,n man&


41/61

organi


42/61

White !3 Testin&:*eans testing t!e a""lication wit! coding ="rogramming knowledge.

!at means t!e tester !as to correct t!e code also.

+a(" !3 testin&:esting t!e a""lication wit!out coding ="rogramming knowledge t!at

means t!e tester doesnJt re'uire coding knowledge. Gust !e eamines t!e a""lication

eternal functional be!aiour and WU, features.S+.N! +a(" !3 White !3

1

0ocuses on t!e functionalit& of t!e

s&stem

0ocuses on t!e structure (?rogram) of

t!e s&stem

2

ec!ni'ues used are @ E'uialence "artitioning 6oundar&-alue anal&sis Error guessing ace conditions Cause-e:ect gra"!ing &nta testing tate transition testing Wra"! matri

ec!ni'ues used are@ 6asis ?at! esting 0low Wra"! Notation Control tructure esting

1. Condition esting

2. ata 0low testing

5oo" esting

1. im"le 5oo"s

2. Nested 5oo"s

#. Concatenated 5oo"s

. Unstructured 5oo"s

# ester can be non tec!nical ester s!ould be tec!nical

Fel"s to identif& t!e agueness and

contradiction in functionals"eci%cations Fel"s to identif& t!e logical and codingissues.

2-. What are the t$*es !f testin&s?

unit testing

Com"onent testing

,ntegration testing

&stem testing

2/. The 7i4eren(e etween it Rate and aud Rate?

!e di:erence between 6it and 6aud rate is com"licated and intertwining. 6ot! are

de"endent and inter-related. 6ut t!e sim"lest e"lanation is t!at a 6it ate is !ow man&

data bits are transmitted "er second. A baud ate is t!e number of times "er second a signal

in a communications c!annel c!anges.


43/61

6it rates measure t!e number of data bits (t!at is 4Os and 1Os) transmitted in one second in a

communication c!annel. A %gure of 244 bits "er second means 244


44/61

0las! storage is commonl& used in U6 memor& dries and solid state !ard dries.

EE?/* is used in a ariet& of deices$ from "rogrammable KCs to C "la&ers.

2. Can stru(tures e *assed t! the fun(ti!ns $ %a+ue?

Ans@ &es structures can be "assed b& alue. 6ut unnecessar& memor& wastage.

2. Wh$ (ann!t arra$s e *assed $ %a+ues t! fun(ti!ns?

Ans @ +!en a arra& is "assed to a function$ t!e arra& is internall& c!anged to a "ointer. And"ointers are alwa&s "assed b& reference.

#'. What is eant $ stati( fun(ti!ns?

Ans: stati( fun(ti!nsare functions t!at are onl& isible to ot!er functions in t!e same %le

E3a*+e:

fun(s.( /*************************************

*

* Function declarations (prototypes).

*

*************************************/

/* Func1 is only visable to functions in this file. */

ain.( #include

main()

{

Func1();

Func2();

}


45/61

staticvoid Func1(void);

/* Func2 is visable to all functions. */

void Func2(void);

/*************************************

*

* Function definitions

*

*************************************/

void Func1(void)

{

puts("Func1 called");

}

/*************************************/ void Func2(void)

{

puts("Func2 called"); }

#1.7i4eren(e etween de(+arati!nD deBniti!n K initia+i=ati!n?

Ans:A declaration introduces a name an identi%er to t!e com"iler. ,t tells t!e com"iler

P!is function or t!is ariable eists somew!ere$ and !ere is w!at it s!ould look like.Q

A de%nition$ on t!e ot!er !and$ sa&s@ P*ake t!is ariable !ereQ or P*ake t!is function !ere.Q

,t allocates storage for t!e name. !is meaning works w!et!er

&ouJre talking about a ariable or a functionH in eit!er case$ at t!e "oint of de%nition t!e

com"iler allocates storage.

etern const int M 1H =Z ,nitiali means t!at t!e de%nition eists elsew!ere.

#2. What is the di4eren(e etween *ass $ %a+ue $ referen(e in ( and *ass $

referen(e in (?

@ass $ Referen(e :

In Pass b reference a!!ress of t"e #ariable is passe! to a function. $"ate#er c"an%es ma!e

to t"e formal parameter &ill a'ect to t"e actual parameters

ame memor location is use! for bot" #ariables.(*ormal an! ctual)

it is useful &"en ou re-uire! to return more t"en #alues

@ass $ Va+ue:

In t"is met"o! #alue of t"e #ariable is passe!. C"an%es ma!e to formal &ill not a'ect t"e

actual parameters.

/i'erent memor locations &ill be create! for bot" #ariables.


46/61

0ere t"ere &ill be temporar #ariable create! in t"e function stac1 &"ic" !oes not a'ect

t"e ori%inal #ariable.

##. What is the di4eren(e etween Jash e!r$D E@RO< and EE@RO


47/61

d&namic A* (see A*). A* retains its contents as long as t!e "ower is connected and

is eas& to interface to but uses si transistors "er bit. &namic A* is more com"licated to

interface to and control and needs regular refres! c&cles to "reent its contents being lost.

Foweer$ A* uses onl& one transistor and a ca"acitor "er bit$ allowing it to reac! muc!

!ig!er densities and$ wit! more bits on a memor& c!i"$ be muc! c!ea"er "er bit. A* is

not wort!w!ile for deskto" s&stem memor&$ w!ere A* dominates$ but is used for t!eir

cac!e memories. A* is common"lace in small embedded s&stems$ w!ic! mig!t onl& needtens of kilob&tes or less. 0ort!coming olatile memor& tec!nologies t!at !o"e to re"lace or

com"ete wit! A* and A* include D-A*$ A*$ A-A* and EA A*.

N!n>%!+ati+e e!r$

Non-olatile memor& is com"uter memor& t!at can retain t!e stored information een w!en

not "owered. Eam"les of non-olatile memor& include read-onl& memor& (see /*)$ ;as!

memor&$ most t&"es of magnetic com"uter storage deices (e.g. !ard disks$ ;o""& discs and

magnetic ta"e)$ o"tical discs$ and earl& com"uter storage met!ods suc! as "a"er ta"e and

"unc!ed cards. 0ort!coming non-olatile memor& tec!nologies include 0eA*$ C6A*$

?A*$ /N/$ A*$ acetrack memor&$ NA* and *illi"ede.

#,. What is a reentrant fun(ti!n?

A reentrant fun(ti!nis a function w!ic! can be safel& eecuted (!n(urrent+$. !is means

it s!ould allow a re-entr& w!ile it is running. !e reentrant function s!ould work onl& on t!e

data gien b& t!e calling function. ,t must not !ae an& static data also.

!e term PreentrantQ is used to refer to side wall "ro%les of t!e no us!4?


48/61

o distinguis! between tem"orar& and "ermanent failures eer& CAN bus controller !as two

Error Counters@ !e EC (eceie Error Counter) and t!e EC (ransmit Error Counter). !e

counters are incremented u"on detected errors res"ectiel& are decremented u"on correct

transmissions or rece"tions. e"ending on t!e counter alues t!e state of t!e node isc!anged@ !e initial state of a CAN bus controller is Error Actie t!at means t!e controller

can send actie Error 0lags. !e controller gets in t!e Error ?assie state if t!ere is an

accumulation of errors.

/n CAN bus controller failure or an etreme accumulation of errors t!ere is a state transition

to 6us /:. !e controller is disconnected from t!e bus b& setting it in a state of !ig!-

resistance. The us O4 state sh!u+d !n+$ e +eft $ a s!ftware reset. After s!ftware

reset the CAN us (!ntr!++er has t! wait f!r 12 3 11 re(essi%e its t! transit a

frae. This is e(ause !ther n!des a$ *endin& transissi!n reuests. It isre(!ended n!t t! start an hardware reset e(ause the wait tie ru+e wi++ n!t

e f!++!wed then.

#/. What is Virtua+ fun(ti!na+ us?

Kirtual function bus can be described as a s&stem modeling and communication conce"t. ,t

is logical entit& t!at facilitates t!e

conce"t of relocatabilit& wit!in t!e AU/A software arc!itecture b& "roiding a irtual

infrastructure t!at is inde"endent from an& actual underl&ing infrastructure and "roides all

serices re'uired for a irtual interaction between AU/A com"onents.

#. Intra and Inter ECU (!uni(ati!n?

,ntra-ECU w!ic! denotes t!e communication between two software com"onents residing on

t!e same ECU and ,nter-ECU w!ic! denotes t!e situation w!en two software

com"onents reside on di:erent ECUJs t!at are connected ia a bus network.

#. What is the di4eren(e etween &+!a+ and stati( &+!a+ %aria+es?

F+!a+ %aria+esare ariables de%ned outside of an& function. !eir sco"e starts at t!e

"oint w!ere t!e& are de%ned and lasts to t!e end of t!e %le. !e& !ae eternal linkage$


49/61

w!ic! means t!at in ot!er source %les$ t!e same name refers to t!e same location in

memor&.

Stati( &+!a+ %aria+esare "riate to t!e source %le w!ere t!e& are de%ned and do not

con;ict wit! ot!er ariables in ot!er source %les w!ic! would !ae t!e same name.

)'. 0!w t! a((ess a F+!a+ %aria+es in !ther B+es?

Kariables declared outside of a block are called &+!a+ %aria+es. Wlobal ariables

!ae *r!&ra s(!*e$ w!ic! means t!e& can be accessed eer&w!ere in t!e "rogram$ andt!e& are onl& destro&ed w!en t!e "rogram ends.

Fere is an eam"le of declaring a global ariable@

12#7S9

314

intgnRH == global ariable

intmain()T

intn^H == local ariable n^

== global ars can be seen eer&w!ere in "rogram== so we can c!ange t!eir alues !ere

gnR M 7H == n^ is destro&ed !ere

6ecause global ariables !ae "rogram sco"e$ t!e& can be used across multi"le %les. ,n t!e

section on "rograms wit! multi"le %les$ &ou learned t!at in order to use a function declared

in anot!er %le$ &ou !ae to use a forward declaration$ or a !eader %le.

imilarl&$ in order to use a global ariable t!at !as been declared in anot!er %le$ &ou !ae to

use a forward declaration or a !eader %le$ along wit! t!e e3ternke&word. Etern tells t!e

com"iler t!at &ou are not declaring a new ariable$ but instead referring to a ariabledeclared elsew!ere.

Fere is an eam"le of using a forward declaration st&le etern@

global.c""@12

== declaration of gnKalue

intgnKalue M 7H

main.c""@12

#7S93

== etern tells t!e com"iler t!is ariable is declared elsew!ere

eternintgnKalueH

intmain()T gnKalue M 9H

return4H

Fere is an eam"le of using a !eader %le etern@

global.c""@1 == declaration of gnKalue

intgnKalue M 7H


50/61

2

global.!@

12#7S9

ifndef W5/6A5F == !eader guardsde%ne W5/6A5F== etern tells t!e com"iler t!is ariable is declared elsew!ere

eternintgnKalueHendif

main.c""@12#7S

include global.!

intmain()T gnKalue M 9H

return4H

Wenerall& s"eaking$ if a global ariable is going to be used in more t!an 2 %les$ itJs better to

use t!e !eader %le a""roac!. ome "rogrammers "lace all of a "rograms global ariables ina %le calledglobals.c""$ and create a !eader %le named globals.! to be included b& ot!er

.c"" %les t!at need to use t!em.

5ocal ariables wit! t!e same name as a global ariable !ide t!e global ariable inside t!at

block. Foweer$ t!e global sco"e o"erator (@@) can be used to tell t!e com"iler &ou mean t!e

global ersion@

12#

7S93

intnKalue M 7H

intmain()T intnKalue M 9H == !ides t!e global nKalue ariable nKalue>>H == increments local nKalue$ not global nKalue @@nKalue--H == decrements global nKalue$ not local nKalue

return4H == local nKalue is destro&ed

Foweer$ !aing local ariables wit! t!e same name as global ariables is usuall& a reci"e

for trouble$ and s!ould be aoided w!eneer "ossible. Using Fungarian Notation$ it is

common to declare global ariables wit! a PgQ "re%. !is is an eas& wa& to di:erentiate

global ariable from local ariables$ and aoid ariables being !idden due to naming

collisions.

New "rogrammers are often tem"ted to use lots of global ariables$ because t!e& are eas&

to work wit!$ es"eciall& w!en man& functions are inoled. Foweer$ t!is is a er& bad idea.

,n fact$ global ariables s!ould generall& be aoided com"letel&_

Wh$ &+!a+ %aria+es are e%i+

Wlobal ariables s!ould be aoided for seeral reasons$ but t!e "rimar& reason is because

t!e& increase &our "rogramJs com"leit& immensel&. 0or eam"le$ sa& &ou were eamining a


51/61

"rogram and &ou wanted to know w!at a ariable named gnKalue was used for. 6ecause

gnKalue is a global$ and globals can be used an&w!ere in t!e entire "rogram$ &ouJd !ae to

eamine eer& single line of eer& single %le_ ,n a com"uter "rogram wit! !undreds of %les

and millions of lines of code$ &ou can imagine !ow long t!is would take_

econd$ global ariables are dangerous because t!eir alues can be c!anged b& an& function

t!at is called$ and t!ere is no eas& wa& for t!e "rogrammer to know t!at t!is will !a""en.Consider t!e following "rogram@

12#7S93

1411121#1171S191312421222#2

== declare global ariable

intgn*ode M 1H

oiddoomet!ing()T gn*ode M 2H

intmain()T gn*ode M 1H

doomet!ing()H

== ?rogrammer e"ects gn*ode to be 1 == 6ut doomet!ing c!anged it to 2_

if(gn*ode MM 1) cout No t!reat detected. endlH

else cout 5aunc!ing nuclear missiles... endlH

return4H

Note t!at t!e "rogrammer set gn*ode to 1$ and t!en called doomet!ing(). Unless t!e

"rogrammer !ad e"licit knowledge t!at doomet!ing() was going to c!ange t!e alue of

gn*ode$ !e or s!e was "robabl& not e"ecting doomet!ing() to c!ange t!e alue_

Conse'uentl&$ t!e rest of main() doesnJt work like t!e "rogrammer e"ects (and t!e world is

obliterated).

Wlobal ariables make eer& function call "otentiall& dangerous$ and t!e "rogrammer !as no

eas& wa& of knowing w!ic! ones are dangerous and w!ic! ones arenJt_ 5ocal ariables are

muc! safer because ot!er functions can not a:ect t!em directl&. Conse'uentl&$ global

ariables s!ould not be used unless t!ere is a er& good reason_

)1. What is the use !f C!*+e3 7e%i(e 7ri%ers in AUTOSAR?

ince t!e AU/A la&ered software arc!itecture restricts direct access to !ardware from

u""er la&ers$ an additional conce"t is "roided in order to b&"ass t!at restriction for


52/61

resource critical and=or Non-AU/A com"liant software com"onents. !e Com"le eice

rier "roides an AU/A ,nterface to t!e a""lication la&er and !as direct access to

alues on t!e "!&sical la&er. !is is usuall& used for t!e im"lementation of com"le sensor

or actuator driers t!at need direct control oer t!e underl&ing !ardware.

)2. 0!w t! setD (+earD t!&&+e and (he("in& a sin&+e it in C?

Use t!e bitwise / o"erator () to set a bit.

number M 1 H

!at will set bit .

C+earin& a it

Use t!e bitwise AN o"erator (I) to clear a bit.

number IM j(1 )H

!at will clear bit . ou must inert t!e bit string wit! t!e bitwise N/ o"erator (j)$ t!en

AN it.

T!&&+in& a it

!e R/ o"erator (h) can be used to toggle a bit.

number hM 1 H

!at will toggle bit .

Che("in& a it

ou didnJt ask for t!is but , mig!t as well add it.

o c!eck a bit$ AN it wit! t!e bit &ou want to c!eck@

bit M number I (1 )H

!at will "ut t!e alue of bit into t!e ariable bit.

)2. What is Wat(hd!& tier?A watc!dog timer (or com"uter o"erating "ro"erl& (C/?) timer) is a com"uter !ardware or

software timer t!at triggers a s&stem reset or ot!er correctie action if t!e main "rogram$

due to some fault condition$ suc! as a !ang$ neglects to regularl& serice t!e watc!dog

(writing a Pserice "ulseQ to it$ also referred to as Pkicking t!e dogQ$ P"etting t!e dogQ$

Pfeeding t!e watc!dogQ or Pwaking t!e watc!dogQ). !e intention is to bring t!e s&stem back

from t!e unres"onsie state into normal o"eration. +atc!dog timers can be more com"le$

attem"ting to sae debug information onto a "ersistent mediumH i.e. information useful for

debugging t!e "roblem t!at caused t!e fault. ,n t!is case a second$ sim"ler$ watc!dog timer


53/61

ensures t!at if t!e %rst watc!dog timer does not re"ort com"letion of its information saing

task wit!in a certain amount of time$ t!e s&stem will reset wit! or wit!out t!e information

saed. !e most common use of watc!dog timers is in embedded s&stems$ w!ere t!is

s"eciali


54/61

instance$ eer& time &ou need a "articular be!aior suc! as drawing a line$ instead of writing

out a bunc! of code$ all &ou need to do is call t!e function. 6ut sometimes &ou would like to

c!oose di:erent be!aiors at di:erent times in essentiall& t!e same "iece of code.

Eam"le@ int (Zf") (int$ int)H - 0unction "ointer returning an integer

),. Si=e !f 7atat$*es

Nae 7es(ri*ti!nSi=eL Ran&eL

c!ar C!aracter or small integer.1b&te

signed@ -123 to 129unsigned@ 4 to 277

s!ort int(s!ort) !ort ,nteger.2b&tes

signed@ -#29S3 to #29S9unsigned@ 4 to S77#7

int ,nteger.b&tes

signed@ -2193#S3 to2193#S9unsigned@ 4 to2S927

long int(long) 5ong integer.b&tes

signed@ -2193#S3 to2193#S9unsigned@ 4 to2S927

bool

6oolean alue. ,t can take one of twoalues@ true or false.

1b&te trueor false

;oat 0loating "oint number.b&tes >=- #.e >=- #3 (j9 digits)

double ouble "recision ;oating "oint number.3b&tes

>=- 1.9e >=- #43 (j17digits)

long double

5ong double "recision ;oating "ointnumber.

3b&tes

>=- 1.9e >=- #43 (j17digits)

)-. What is the di4eren(e etween t$*edef K


55/61

t&"edefs can correctl& encode "ointer t&"es.w!ere as E0,NE are Lust re"lacements done

b& t!e "re"rocessor.

0or eam"le$

1. t&"edef c!ar ZtringtH

2. de%ne tringd c!ar Z

#. tringt s1$ s2H tringd s#$ sHs1$ s2$ and s# are all declared as c!ar Z$ but s is declared as a c!ar$ w!ic! is "robabl& not

t!e intention.

)/. What is the di4eren(e etween a a(r! and a fun(ti!n?

*acros are essentiall& s!ort!and re"resentations of arbitrar& sections of t!e source code$

w!ic! makes t!e source code$ w!ile its (t!e macro tem"lateJs) e"ansion re"laces eac! of its

"resence "rior to com"ilation. +!ateer is t!ere to do wit! *acros$ it is done b& t!e

"re"rocessor$ so t!at t!e source code is read& for com"ilation. 0unction is a calling routine$

w!ence a large "rogram is diided into se"arate "ortions$ eac! "ortion doing a se"arate Lob$and "ro"er calling of t!ese "ortions in di:erent "laces combines t!e works done b& t!em

into t!e re'uired com"lete out"ut. !us functions !ae not!ing to do wit! t!e "re"rocessing

"eriod$ t!e& are Lust com"iled. o some etent function and macro is similar$ for a macro can

occasionall& be inoked to "erform a task t!at is generall& entrusted to a function. 6ut t!e

similarit& ends t!ere.

!e di:erences are@

1. *acro consumes less time. +!en a function is called$ arguments !ae to be "assed toit$ t!ose arguments are acce"ted b& corres"onding dumm& ariables in t!e function$

t!e& are "rocessed$ and %nall& t!e function returns a alue t!at is assigned to a

ariable (ece"t for a oid function). ,f a function is inoked a number of times$ t!e

times add u"$ and com"ilation is dela&ed. /n t!e ot!er !and$ t!e macro e"ansion

!ad alread& taken "lace and re"laced eac! occurrence of t!e macro in t!e source code

before t!e source code starts com"iling$ so it re'uires no additional time to eecute.

2. 0unction consumes less memor&. +!ile a function re"lete wit! macros ma& look

succinct on surface$ "rior to com"ilation$ all t!e macro-"resences are re"laced b& t!eir

corres"onding macro e"ansions$ w!ic! consumes considerable memor&. /n t!e ot!er!and$ een if a function is inoked 144 times$ it still occu"ies t!e same s"ace. Fence

function is more amenable to less memor& re'uirements

). What is in+ine fun(ti!n?

,nline function is t!e o"timi


56/61

Ad%anta&es :>

1) ,t does not re'uire function calling oer!ead.

2) ,t also sae oer!ead of ariables "us!="o" on t!e stack$ w!ile function calling.

#) ,t also sae oer!ead of return call from a function.

) ,t increases localit& of reference b& utili


57/61

main()

{

int a, b, c;

#ifdef FIRST

a=2; b=6; c=4;

#else

printf("Enter a:");

scanf("%d", &a);

printf("Enter a:");

scanf("%d", &a);

printf("Enter a:");

scanf("%d", &a);

#endif

additonal code

Note t!at if 0, is de%ned (w!ic! it is in t!e aboe) t!e alues of a$ b and c are !ardcoded

to alues of 2$ S and . !is can sae a lot of time w!en deelo"ing software as it aoids

tediousl& t&"ing eer&t!ing in eac! and eer&time &ou run &our routine. +!en 0, is

de%ned$ all t!at is "assed to t!e com"iler is t!e code between t!e ifdef and t!e else. !e

code between t!e else and t!e endif is not seen b& t!e com"iler. ,t is as if it were all a

comment.

/nce &ou !ae &our routine working$ and desire to insert t!e "rintf and scanfs$ all t!at is

re'uired is to go back and delete t!e t!e de%ne 0,. Now$ t!e com"iler does not see t!eH

a=2; b=6; c=4;


58/61

0!w t! (a+(u+ate CRC Seuen(e in a CAN 6rae?

!e receiers calculate t!e CC in t!e same wa& as t!e transmitter as follows@

1. !e message is regarded as "ol&nom and is diided b& t!e generator "ol&nom@

17

> 1 > 14 > 3 > 9 > > # > 1 .2. !e diision rest of t!is modulo2 diision is t!e CC se'uence w!ic! is transmitted

toget!er wit! t!e message.

#. !e receier diides t!e message inclusie t!e CC se'uence b& t!e generator

"ol&nom.

A CC error !as to be detected$ if t!e calculated result is not t!e same as t!at receied in

t!e CC se'uence. ,n t!is case t!e receier discards t!e message and transmits an Error

0rame to re'uest retransmission.

,1. 7i4eren(e etween stati( and d$nai( RA


59/61

What is di4eren(e the etween IF and F +!(" in CANa+$=erCAN!e t!!+?

Answer@ !ere are two limitations to t!e Wenerator block t!at limit its e:ectieness in

com"le tasks. !e block is misleading for some "eo"le because it re'uires multi"le windows

for setting u" t!e transmit message list. !e second "roblem is t!e block settings !ae to be

set before t!e CANal&


60/61

?roides Cost aings b& !ortened eelo"ment time

Com"lete$ consistent test coerage.

u""orts automated testing

Enables testing t!e !ardware wit!out building a P"lant "rotot&"eQ

imulator "erforms test outside t!e normal range of o"eration

u""orts re"roducible test runs t!at can assist in uncoering and tracking down !ard

to %nd "roblems. Enables testing wit! less risk of destro&ing t!e s&stem

SI8: ,5 refers to t!e kind of testing done to alidate t!e be!aior of t!e C-code used in t!e

controller. !at code can be auto-generated from t!e model used in algorit!m

deelo"ment. Emmeska& !as a dee" understanding of ,5 testing and auto-code generation

from t!e man& ,5 "roLects we !ae "erformed for our customers.

Testin& and Va+idati!n

?lant model deelo"ed in e!icle simulation enironment is im"orted to imulink as a

librar&.

Controller is tested in loo" wit! t!e "lant for di:erent routes and s"eed "ro%les.

Controller is tested for di:erent fault modes of t!e s&stem using WU, KisualConne

RTOS Questi!n:

What is RTOS?

eal-ime /"erating &stem is a multitasking o"erating s&stem intended for real-time

a""lications. ,t is used on eer& deice=s&stem needing real time o"erations t!at means

o"erations based not onl& on correctness but also u"on t!e time (clock c&cles) in w!ic! t!e&

are "erformed.

,n general$ an o"erating s&stem (/) is res"onsible for managing t!e !ardware resources ofa com"uter and !osting a""lications t!at run on t!e com"uter. An / "erforms t!ese

tasks$ but is also s"eciall& designed to run a""lications wit! er& "recise timing and a !ig!

degree of reliabilit&. !is can be es"eciall& im"ortant in measurement and automation

s&stems w!ere downtime is costl& or a "rogram dela& could cause a safet& !a


61/61

im"ortant to kee" u" wit! t!e ideo stream. 0or t!is a""lication$ a soft real-time o"erating

s&stem ma& suce. An / can guarantee t!at a "rogram will run wit! er& consistent

timing. eal-time o"erating s&stems do t!is b& "roiding "rogrammers wit! a !ig! degree of

control oer !ow tasks are "rioritiTie OSs 7i4er fr! Fenera+>@ur*!se OSs?

/"erating s&stems suc! as *icrosoft +indows and *ac / can "roide an ecellent "latformfor deelo"ing and running &our non-critical measurement and control a""lications.

Foweer$ t!ese o"erating s&stems are designed for di:erent use cases t!an real-time

o"erating s&stems$ and are not t!e ideal "latform for running a""lications t!at re'uire

"recise timing or etended u"-time. !is section will identif& some of t!e maLor under-t!e-

!ood di:erences between bot! t&"es of o"erating s&stems$ and e"lain w!at &ou can e"ect

w!en "rogramming a real-time a""lication.

Interru*t 8aten($

,nterru"t latenc& is measured as t!e amount of time between w!en a deice generates aninterru"t and w!en t!at deice is sericed. +!ile general-"ur"ose o"erating s&stems ma&

take a ariable amount of time to res"ond to a gien interru"t$ real-time o"erating s&stems

must guarantee t!at all interru"ts will be sericed wit!in a certain maimum amount of time

,n ot!er words$ t!e interru"t latenc& of real-time o"erating s&stems must be bounded

automotive interview questions

Documents